JPH10135454A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent grooves and vicinity from cracking due to the bonding pressure by forming the grooves crossing a major surface of a semiconductor substrate, except its portions just beneath bonding pads. SOLUTION: Al bonding pads 23 are formed on stripe-like diffused regions 22 and linear grooves 21 between these regions 22 and to be electrically connected to externals. The grooves beneath the bonding pads 23 are not cross as in prior art but linear only and hence the linear grooves 21 are filled with polysilicon of gate electrodes 15. Hence the stress round the linear groove 21 is little and a layer insulating film, gate electrodes, gate oxide film, diffused regions 22 and peripheries of the linear grooves 21 never crack due to the bonding pressure to result in that poor characteristics or poor reliability never occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a groove formed in a substrate and having a bonding pad, and more particularly to a groove structure immediately below the bonding pad.

[0002]

2. Description of the Related Art Conventional UMOS type power MOSFET
FIG. 2 is a plan view showing the bonding pad of FIG.
Shown in

A groove 1 having a base region (not shown) and a source region (not shown) formed in the same size and having a gate oxide film (not shown) formed around a large number of square diffusion regions 2. Is surrounding. The grooves are straight groove 1a and cross groove 1b
There is. A bonding pad 3 made of aluminum and connected to the outside by bonding a gold wire, which is hatched, is formed on the many diffusion regions 2 and the grooves 1.

FIG. 3 is a sectional side view of an AA section crossing the straight groove 1a at a right angle in FIG. The same parts as those in FIG. 2 are described with the same numbers.

The structure shown in FIG. 3 will be described.

A p-type base region 12 is formed on a drain region 11 which is an n-type substrate by ion implantation and thermal diffusion, and a high concentration source region 13 is formed on a predetermined region of the base region 12 by ion implantation and thermal diffusion. .

A groove 1 (a straight groove 1 in FIG. 3) extends from the surface of the source region 13 to the drain region 11 through the base region 12.
a), the source region 13 is formed from the bottom of the groove and the side of the groove.
A gate oxide film 14 made of a silicon oxide film is formed on a part of the surface of the substrate. A gate electrode 15 made of polysilicon is formed on the gate oxide film 14 on the surface of the trench 1 and on a part of the source region 13.

An interlayer insulating film 16 made of a silicon oxide film is formed on the gate oxide film 15 of the gate electrode 15 and the source region 13, and the interlayer insulating film 16, the source region 13 and the base region 12 are also source electrodes made of aluminum. Bonding pads 3 are formed.

Subsequently, the cross section B- which crosses the cross groove 1b in FIG.
FIG. 4 is a cross-sectional view of the portion B. 2 and 3 are denoted by the same reference numerals, and differences from FIG. 3 will be described.

The structure shown in FIG. 4 will be described.

The groove 1 (from the surface of the source region 13 to the drain region 11 through the base region 12) (in FIG.
b) is drilled. This cross groove 1b is substantially the same as the linear groove 1a.
It is four times the size.

To this end, a polysilicon gate electrode 15 is formed on a portion of the gate oxide film 14 on the surface of the intersection groove 1b and the source region 13.
Therefore, the intersection groove 1b is not completely filled. Therefore, a recess 15a of polysilicon is formed, which is
Filled with 6. A bonding pad 3 is provided thereon.

[0013]

As described above, the central portion of the intersection groove is not completely filled with the gate electrode, and the unfilled portion is filled with the interlayer insulating film. Are filled with two kinds of materials having different thermal expansion coefficients. On the other hand, the straight groove is filled with only the gate electrode. Therefore, the stress of the cross groove is larger than that of the straight groove. As a result, due to the pressure applied when bonding a fine wire such as a gold wire to the bonding pad on the interlayer insulating film, the interlayer insulating film in the cross groove having a large stress,
Cracks are easily generated in the gate electrode, the gate oxide film, and silicon, which may result in poor characteristics or poor reliability.

[0014]

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems. In a semiconductor device having a groove formed crossing a main surface of a semiconductor substrate and having a bonding pad, the groove is formed by a bonding pad. Except for a portion immediately below, a crossed semiconductor device is provided. in this way,
The intersection of the grooves is not formed under the bonding pad,
Since the groove is filled with the gate electrode, cracks do not occur in the groove and its vicinity due to the pressure during bonding.

The stripe-shaped groove may be formed directly below the bonding pad.

Further, the groove may be an element isolation region or a gate region.

[0017]

FIG. 1 is a plan view showing a bonding pad according to an embodiment of the present invention, a straight groove of a stripe under the bonding pad, and a rectangular diffusion region. Although not shown, an intersection groove is provided in a region other than below the bonding pad.

In the drawing, reference numeral 21 denotes a straight groove having the same width as that of a gate, 22 denotes a diffusion region of a stripe forming a base region (not shown) and a source region (not shown), 23
Is a bonding pad made of aluminum, which is formed on a plurality of stripe-shaped diffusion regions 22 and linear grooves 21 between the diffusion regions 22 and is a region which is electrically connected to the outside, and is indicated by hatching. is there.

The cross-sectional view of the region CC perpendicularly crossing the straight groove 21 is exactly the same as the cross-sectional view of AA in FIG.

The groove under the bonding pad 23 is only the linear groove 21 and has no crossing groove as in the conventional case. Therefore,
The straight groove 21 is filled with polysilicon of the gate electrode 15.

For this reason, the stress around the linear groove 21 is small, and the pressure at the time of bonding causes
6, gate electrode 15, gate oxide film 14, diffusion region 22
Also, no crack is formed around the linear groove 21.
As a result, there is no longer any problem of characteristic failure or reliability failure.

Although the structure in which the gate is formed in the groove 31 has been described, the effect is the same even if the groove is an element isolation region.

[0023]

According to the present invention, since the intersection groove is not formed under the bonding pad, stress in the groove is reduced.
When bonding to the bonding pad, cracks are no longer formed in the vicinity of the groove.

[Brief description of the drawings]

FIG. 1 is a plan view of a bonding pad on a stripe groove showing a main part of an embodiment of the present invention.

FIG. 2 is a plan view of a conventional bonding pad on a groove having an intersection groove.

FIG. 3 is a side sectional view perpendicularly crossing the straight groove of FIG. 1;

FIG. 4 is a cross-sectional side view of the intersection groove of FIG.

[Explanation of symbols]

 21 Straight groove (groove) 23 Bonding pad

Claims (3)

[Claims] 1. A semiconductor device having a bonding pad in which a groove intersecting a main surface of a semiconductor substrate is formed.
A semiconductor device in which the grooves intersect at portions other than immediately below the bonding pads. 2. The semiconductor device according to claim 1, wherein a stripe-shaped groove is formed immediately below said bonding pad. 3. The semiconductor device according to claim 1, wherein said trench is an element isolation region or a gate region.