JP2006216596A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a chip by enabling reducing a lateral stress without changing the height of an aluminum wiring or a chip area. <P>SOLUTION: This semiconductor device has a peripheral section having a first thickness and a wiring forming section having a second thickness thinner than the first thickness. The semiconductor device has a semiconductor substrate 10 having the same bottom surface, and an aluminum wiring layer formed on the wiring forming section of the semiconductor substrate 10. In the semiconductor device, the wiring forming section is arranged adjacently to the peripheral section. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a wiring portion formed on the surface of a resin-encapsulated semiconductor device.

  In the wiring in the chip, if the wiring resistance is large, there arises a problem of causing a delay in signal transmission. Further, there arises a problem that the allowable current amount of the chip cannot be increased. For these reasons, it is necessary to make the wiring in the chip low resistance. In order to reduce the resistance, the wiring cross-sectional area may be increased.

  In order to increase the wiring cross-sectional area, two methods are conceivable: a method of widening the wiring width and a method of increasing the thickness of the wiring. However, the method of widening the wiring width results in a demerit that the cost is increased because a large chip area is required. On the other hand, in the method of increasing the thickness of the wiring, since the lateral stress applied to the aluminum wiring due to a temperature cycle or the like increases, there is a high possibility that the reliability such as an aluminum slide will be affected.

  From the above, in order to reduce the resistance of the wiring in the chip, a technique for increasing the thickness of the aluminum wiring and simultaneously avoiding the lateral stress is indispensable.

  Here, as an example of conventional aluminum wiring, a semiconductor chip 900 having a vertical MOSFET structure is shown in FIG. A plurality of aluminum wirings (field plate 902, ground line 903, and gate finger 904) are formed on the substrate 901. A source electrode 905 is formed on the semiconductor substrate 901 inside the gate finger 904 over almost the entire surface of the substrate inside the gate finger 904.

  In the case of a molded product, the semiconductor chip 900 is mounted on a metallic lead frame using a paste agent and sealed with a resin so as to cover them. In the case of the conventional aluminum wiring, as shown in FIG. 4, the aluminum wiring (field plate 902, ground line 903 and gate finger 904, source electrode 905) protrudes from the upper surface of the semiconductor chip 900. For these reasons, when the temperature changes greatly, a lateral stress is applied to the aluminum wiring due to a difference in expansion coefficient between the resin and the semiconductor chip 900.

In addition, the influence of the lateral stress applied to the aluminum wiring tends to appear on the field plate 902, the ground wiring 903, the gate finger 904, and the like which are aluminum wiring thinner than the source electrode 905 having a large area. Furthermore, since the stress in the lateral direction increases as the distance from the center of the semiconductor chip 900 increases, the field plate 902, the ground wiring 903, and the gate finger 904 disposed in the outer peripheral portion are more easily affected by the stress in the lateral direction. Become.
JP-A-4-155926

  In order to consider the influence of the lateral direction, FIG. 5 shows a schematic sectional view of a conventional aluminum wiring. As shown in FIG. 5A, in the case of a conventional aluminum wiring, an oxide film 93 is formed at a predetermined position on a semiconductor substrate 91, and a gate electrode 94 is formed on the oxide film 93. Thereafter, an interlayer insulating film 92 is formed.

  In the case of the conventional aluminum wiring, the lateral stress described above is applied to the aluminum wiring, and the aluminum wiring is gradually inclined. In addition, when a large stress is applied, the wiring may slide from the base and cracks 95 may occur, resulting in failure to obtain the expected characteristics (see FIGS. 5B and 5C).

  A semiconductor device according to one aspect of the present invention includes a peripheral portion having a first thickness and a wiring formation portion having a second thickness that is thinner than the first thickness, and the bottom surfaces are the same. A wiring board having a substrate and an aluminum wiring layer formed on the wiring forming portion of the semiconductor substrate, wherein the wiring forming portion is disposed adjacent to the peripheral portion. By performing the aluminum wiring as described above, it is possible to suppress the lateral stress applied to the aluminum wiring.

  Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising a peripheral portion having a first thickness and a wiring forming portion having a second thickness smaller than the first thickness, and the bottom surface This is a method for manufacturing a semiconductor device in which the same semiconductor substrate is prepared, aluminum wiring is formed on a wiring forming portion of the semiconductor substrate, and the semiconductor substrate on which the aluminum wiring is formed is resin-sealed. Since the semiconductor substrate in the wiring forming portion is thin, it is possible to suppress the lateral stress stress applied to the aluminum wiring layer.

  According to the aluminum wiring structure of the present invention, it is possible to reduce the lateral stress stress without changing the height of the aluminum wiring and the chip area, and it is possible to contribute to the improvement of the chip reliability.

  FIG. 1 shows a top view of a semiconductor device 1 according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along the line AA of FIG. Hereinafter, the semiconductor device 1 of the present invention will be described with reference to FIGS. 1 and 2.

  The semiconductor device of the first embodiment includes a semiconductor substrate 10, a die pad 17, and a sealing resin 16. The semiconductor substrate 10 is mounted on a die pad, and the semiconductor substrate 10 and the entire die pad 17 are sealed with a sealing resin 16.

  A plurality of aluminum wirings (field plate 11, ground line 12, and gate finger 13) are formed on the semiconductor substrate 10 to be sealed with resin. A source electrode 14 is formed on the semiconductor substrate 10 inside the gate finger 13 over almost the entire surface of the substrate inside the gate finger 13.

  Each of these electrodes is separated by an interlayer insulating film 18. The gate finger 13 is an aluminum wiring formed on the gate electrode 23 made of polysilicon. The gate finger 13 is also a part of the gate electrode. In the following description, the gate finger 13 will be referred to as the gate finger 13 in order to distinguish it from the gate electrode 23 formed of polysilicon described later.

  A well diffusion layer 15 is formed in the semiconductor substrate outside the ground line 12. The well diffusion layer 15 is formed of a well having a conductivity type opposite to that of the semiconductor substrate 10. Here, the well diffusion layer 15, the field plate 11, the ground line 12, and the gate finger 13 described above are each formed in a ring shape. That is, these components are formed so as to surround the source electrode 14 in the order of the well diffusion layer 15, the ground line 12, the field plate 11, and the gate finger 13 from the outside to the inside of the semiconductor substrate 10. .

  A cross-sectional structure of this semiconductor device will be described. The semiconductor substrate 10 is an N-type semiconductor substrate, and a P-type well 21 is formed in a lower region of the gate finger 13. A gate electrode 23 made of polysilicon is formed on the P-type well 21 via an insulating film 19. A gate finger 13 is formed on the gate electrode 23 and is electrically connected to the polysilicon gate electrode 23.

  The P-type well 21 is formed over the entire region surrounded by the gate finger 13. An N-type well 22 is formed in the lower region of the source electrode 14 in the P-type well 21. A drain electrode 20 is formed on the entire back surface of the semiconductor substrate. That is, the semiconductor device of the present invention forms a vertical MOSFET having the surface of the P-type well 21 below the gate finger 13 as a channel region.

  As described above, the ground wiring 12 and the field plate 11 are formed on the semiconductor substrate 10 outside the gate finger 13 (N-type region: see FIG. 2) via the insulating film 19. A P-type well diffusion layer 15 is formed in the semiconductor substrate 10 outside the ground wiring 12.

  Here, as shown in FIG. 2, in the semiconductor device of the present embodiment, the thickness of the semiconductor substrate where the source electrode 14 and the well diffusion layer 15 are formed, the field plate 11, the ground wiring 12, and the gate finger 13. The thickness of the semiconductor substrate at the portion where the wiring is formed is different. More specifically, the semiconductor substrate 10 in the wiring forming portion where the field plate 11, the ground wiring 12, and the gate finger 13 are formed is formed thin, and a recess is formed on the surface of the semiconductor substrate. The reason for this configuration will be described below.

  As described above, the semiconductor device of the present invention is a vertical MOSFET. Such vertical MOSFETs are often used as power MOSs for high voltage devices. In such a power MOS device, the well diffusion layer 15 as described above is generally provided along the outer periphery of the substrate in order to ensure a breakdown voltage.

  In addition, as an electrode for adjusting the width of the depletion layer formed by the well diffusion layer 15, wirings such as the field plate 11 and the ground line 12 are generally provided in a ring shape along the well diffusion layer 15. is there.

  Furthermore, it is desirable to increase the area of the source electrode 14 in order to pass a large current. Therefore, as described above, the field plate 11 or the like, which is an extremely thin wiring compared to the source electrode 14 or the like, is disposed along the outer periphery of the chip.

  Here, FIG. 3 shows an example of the positional relationship between the chip 31, the lead frame 32, and the sealing resin 33. The stress due to the sudden change in the ambient temperature is concentrated at the four corners 34 of the chip 31 and increases. This is because the stress increases as the distance from the center of the chip 31 increases due to the difference in expansion coefficient of each member.

  That is, the influence of stress due to the difference in expansion coefficient is likely to appear on the field plate 11, the ground wiring 12, the gate finger 13, and the like which are thinner than the source electrode 14 having an extremely large area.

  From the above, in the present invention, a concave portion is formed on the surface of the semiconductor substrate of the wiring forming portion, and the wiring is embedded in the concave portion, thereby reducing the influence of the lateral stress on the aluminum wiring.

  The reduction of the lateral stress will be described below. In the first embodiment, the semiconductor substrate 10 at the center side of the well diffusion layer 15 is dug by an etching method, so that the thickness of the substrate where the well diffusion layer 15 is formed is equal to the thickness of the semiconductor substrate 10 in the wiring formation portion. It is characterized by being thicker.

  In order to cope with the lateral stress, if the height of the aluminum wiring is lowered, the resistance of the wiring when a large current flows is affected. Therefore, in the first embodiment according to the present invention, the semiconductor substrate at the center side of the well diffusion layer 15 is made thinner than the semiconductor substrate at the portion where the well diffusion layer 15 is formed, and aluminum wiring is provided on the semiconductor substrate. Is going.

  Therefore, the difference in height between the upper surface of the aluminum wiring of the field plate 11, the ground line 12, and the gate finger 13 in the first embodiment and the upper surface of the semiconductor substrate including the well diffusion layer 15 is a substrate having a uniform thickness. By making it smaller than the difference between the height of the upper surface of the aluminum wiring and the height of the upper surface of the well diffusion layer 15 when the aluminum wiring is performed on the aluminum wiring, the aluminum wiring of the field plate 11, the ground line 12, and the gate finger 13 is applied. Corresponds to lateral stress.

  The present invention is effective by reducing the difference between the height of the upper surface of the aluminum wiring and the height of the upper surface of the semiconductor substrate including the well diffusion layer 15 while keeping the thickness of the aluminum wiring. Lateral stress can be reduced without making the difference in height between the upper surface of the aluminum wiring and the upper surface of the semiconductor substrate including the well diffusion layer 15 completely zero.

  For example, when the aluminum wiring is cracked when the thickness of the aluminum wiring is 4 μm, the semiconductor substrate upper surface including the well diffusion layer 15 and the aluminum wiring are reduced by reducing the thickness of the semiconductor substrate in the portion where the aluminum wiring is performed by 2 μm. Even if the difference in height from the upper surface is suppressed to 2 μm, it is strengthened against lateral stress.

  The height of aluminum wiring and the degree of influence of stress are largely due to complex factors such as package, layout, and environment, but if the difference in height between the upper surface of the aluminum wiring and the upper surface of the semiconductor substrate including the well diffusion layer 15 is halved, If the height of the upper surface of the aluminum wiring is the same as the height of the upper surface of the semiconductor substrate including the well diffusion layer 15, the possibility of cracking in the aluminum wiring can be completely suppressed. .

  In the first embodiment, there is no need to reduce the thickness of the aluminum wiring in order to cope with the lateral stress. That is, by reducing the thickness of the semiconductor substrate where aluminum wiring is performed, it is possible to reduce lateral stress stress without reducing the cross-sectional area of the aluminum wiring. Accordingly, the present invention can suppress an increase in resistance of the aluminum wiring and can contribute to an improvement in chip reliability.

  In products that handle high power, thick aluminum wiring must be used to pass a large current. However, there is a need to reduce the chip area for cost reduction. In such a case, the present invention can be used as a useful means because it can avoid the lateral stress without changing the height of the aluminum wiring.

  From the above, in the first embodiment, an aluminum wiring structure capable of reducing the lateral stress stress without changing the thickness of the aluminum wiring by thinning the semiconductor substrate where aluminum wiring is performed is provided. It becomes possible to take.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. In this embodiment, the vertical MOS element has been described as an example. However, the present invention can be applied to any semiconductor element such as a light emitting element, a bipolar transistor, and a MOS element. It is not limited to only.

  Furthermore, in the present embodiment, the upper surface of the semiconductor substrate including the well diffusion layer 15 is used. Similarly, even when the thin semiconductor substrate 10 is formed, the lateral stress applied to the aluminum wiring can be reduced if the outermost semiconductor substrate is thicker than the well diffusion layer 15.

  From the above, in the first embodiment, the lateral stress stress applied to the field plate 11 and the ground line 12 is reduced by forming a recess in the wiring forming portion inside the well diffusion layer 15. As a result, problems such as cracks in the aluminum wiring can be suppressed, and a highly reliable semiconductor chip can be produced.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

Structure diagram of aluminum wiring structure according to the first embodiment Sectional view of the aluminum wiring structure according to the first embodiment Positional relationship of chip, lead frame, resin protective film Structure diagram of a conventional semiconductor chip having a vertical MOSFET structure Cross-sectional schematic diagram of conventional aluminum wiring

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Aluminum wiring structure 10 in connection with Embodiment 1 Semiconductor substrate 11 Field plate 12 Ground line 13 Gate finger 14 Source electrode 15 Well diffusion layer 16 Sealing resin 17 Die pad 18 Interlayer insulating film 19 Insulating film 20 Drain electrode 21 P layer well 22 N layer well 23 Polysilicon gate electrode 31 Chip 32 Lead frame 33 Sealing resin 34 Four corners 91 Oxide insulating film 92 Interlayer insulating film 93 Insulating film 94 Aluminum wiring
95 crack 900 conventional semiconductor chip 901 substrate 902 field plate 903 ground line 904 gate finger 905 source electrode 906 well diffusion layer 907 insulation film 908 drain electrode 909 p layer well 910 n layer well 911 polysilicon gate electrode 912 interlayer insulation film

Claims (10)

A semiconductor substrate having a peripheral portion having a first thickness and a wiring forming portion having a second thickness smaller than the first thickness, and having the same bottom surface;
An aluminum wiring layer formed on the wiring forming portion of the semiconductor substrate,
A semiconductor device in which the wiring forming portion is disposed adjacent to the peripheral portion. The semiconductor device according to claim 1,
A semiconductor device in which an insulating film is formed between the wiring layer and the wiring forming portion. The semiconductor device according to any one of claims 1 and 2,
A semiconductor device in which a well having a conductivity type opposite to that of the semiconductor substrate is formed in the peripheral portion. A semiconductor device according to any one of claims 1 to 3,
The wiring layer is a semiconductor device formed in a ring shape along the periphery of the chip. A semiconductor device according to any one of claims 1 to 4, wherein
The semiconductor device, wherein the wiring layer is a wiring layer to which a predetermined potential is applied. A semiconductor device according to any one of claims 1 to 5, wherein
The semiconductor device, wherein the wiring layer is a power MOS gate wiring. Preparing a semiconductor substrate having a peripheral portion having a first thickness and a wiring forming portion having a second thickness smaller than the first thickness and having the same bottom surface;
Forming aluminum wiring on the wiring forming portion of the semiconductor substrate;
A method of manufacturing a semiconductor device in which the semiconductor substrate on which the aluminum wiring is formed is resin-sealed. A method for manufacturing a semiconductor device according to claim 7, comprising:
A method of manufacturing a semiconductor device, wherein an insulating film is formed between the wiring layer and the wiring forming portion. A method for manufacturing a semiconductor device according to claim 7, wherein:
A method of manufacturing a semiconductor device, wherein a well having a conductivity type opposite to that of the semiconductor substrate is formed in the peripheral portion. A method of manufacturing a semiconductor device according to any one of claims 7 to 9,
A method of manufacturing a semiconductor device, wherein the wiring layer is formed in a ring shape along the peripheral portion.

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