JPH1013250A - Reed-solomon error-correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the circuit to have provision for high-speed processing in a small hardware scale with respect to the Reed-Solomon error-correction circuit, used for the error correction system. SOLUTION: A memory 101 receives a reception packet 1 and delays it by 2 packets and provides an output of the result as a delay packet 3. A syndrome-generating circuit 102 receives the reception packet 1 for providing an output of a syndrome 2. An error-correction circuit 103 receives the syndrome 2 and the delay packet 3 and obtains an error location polynomial and an error evaluation polynomial from the syndrome 2, by using its internal error location polynomial/error evaluation polynomial calculation circuit, obtains an error included in the delay packet 3 based on the error location polynomial and the error evaluation polynomial, by using its internal correction circuit, eliminates an error from the delay packet 3 and provides an output of a decoded packet 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Reed-Solomon error correction circuit used as an error correction method.

[0002]

2. Description of the Related Art A Reed-Solomon error correction circuit is used as an error correction method in various fields such as a recording medium such as an optical disk and a digital transmission system such as digital satellite broadcasting. In recent years, as the capacity of recording and transmission has been increased, Reed-Solomon error correction circuits corresponding to high-speed processing have been developed.

Hitherto, a Reed-Solomon error correction circuit corresponding to high-speed processing has been known from Japanese Patent Application Laid-Open No. 3-195216.

The Reed-Solomon error correction circuit includes a syndrome generation circuit (corresponding to the syndrome generation circuit in the Reed-Solomon error correction circuit of the present invention) and a circuit for deriving an error locator polynomial (the error correction circuit in the Reed-Solomon error correction circuit of the present invention). , An error position detection circuit, an error pattern detection circuit, an AND gate, and an EXOR gate (internal error correction circuit in the Reed-Solomon error correction circuit of the present invention) And a delay circuit (corresponding to a memory in the Reed-Solomon error correction circuit of the present invention).

The circuit for deriving the error locator polynomial of the Reed-Solomon error correction circuit, as described in the above-mentioned publication, needs to include many Galois field arithmetic circuits between shift registers in order to cope with high-speed processing. There is. Therefore, there is a problem that the hardware scale is large.

Further, in order to suppress an increase in internal delay and power consumption due to a large hardware scale, operation is performed using a received symbol clock without using a high-speed clock. For this reason, it takes one packet to process the derivation circuit for the error locator polynomial.

Therefore, it is necessary to perform at least a parallel operation by a three-stage pipeline processing of a syndrome generation circuit, an error position polynomial derivation circuit, an error position detection circuit, an error pattern detection circuit, an AND gate, and an EXOR gate. The delay circuit must hold data for three packets, and the hardware scale is further increased.

[0008]

As described above, the conventional Reed-Solomon error correction circuit has a problem that the hardware scale becomes large in order to cope with high-speed processing.

A Reed-Solomon error correction circuit according to the present invention comprises:
The purpose is to support high-speed processing on a small hardware scale.

[0010]

In order to solve this problem, a Reed-Solomon error correction circuit according to the present invention is arranged such that a syndrome generation circuit and the error correction circuit perform a parallel operation by two-stage pipeline processing. It is composed.

Further, the error correction circuit of the Reed-Solomon error correction circuit according to the present invention employs 1/1/3 of the cycle of the received symbol clock.
It is configured to operate in synchronization with a clock having a period of N (N ≧ 1; N is an integer).

Further, the error locator polynomial / error evaluation polynomial calculator of the Reed-Solomon error correction circuit of the present invention does not include a Galois field arithmetic circuit between the registers of the shift register, and has a Galois field having the output of the last stage of the shift register as an input. Only an arithmetic circuit is provided.

As a result, the Reed-Solomon error correction circuit of the present invention supports high-speed processing with a small hardware scale.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a Reed-Solomon error correction circuit for receiving a Reed-Solomon encoded and transmitted packet, performing Reed-Solomon decoding on the received packet, and outputting a decoded packet. A memory for inputting a packet, delaying and outputting a delayed packet, a syndrome generating circuit for inputting the received packet and outputting a syndrome, and an error for inputting the delayed packet and the syndrome and outputting the decoded packet. A correction circuit, wherein the error correction circuit inputs the syndrome, outputs an error position polynomial and an error evaluation polynomial, an error position polynomial / error evaluation polynomial calculation circuit, the delay packet, the error position polynomial, Input an error evaluation polynomial, the error location polynomial and the error evaluation polynomial Find the error included in the delay packet, remove the error from the delay packet, and comprises a correction circuit that outputs the decoded packet, the error position polynomial / error evaluation polynomial calculation circuit, a plurality of shift registers, A Galois field arithmetic circuit having a shift register final stage output as input, wherein the syndrome generation circuit and the error correction circuit perform a parallel operation by pipeline processing for each packet, and the error correction circuit 1 / N of the clock cycle (N ≧ 1; N is an integer)
And operates in synchronization with a clock having a period of, thereby supporting high-speed processing with a small hardware scale.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a Reed-Solomon error correction circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a received packet, 2
Is a syndrome, 3 is a delay packet, 4 is a decoded packet, 5 is an error locator polynomial, 6 is an error evaluation polynomial, and 7 is a clock having a cycle of 1/4 of the cycle of the received symbol clock. 101 is a memory for receiving the received packet 1 and delaying it by two packets and outputting it as the delayed packet 3; 102 is a syndrome generating circuit for receiving the received packet 1 and outputting the syndrome 2;
An error correction circuit 103 receives the delay packet 3 and the syndrome 2 and outputs a decoded packet 4.

The syndrome generation circuit 102 and the error correction circuit 103 have a pipeline configuration for each packet. The error correction circuit 103 is supplied with the clock 7 having a cycle that is １ ／ of the cycle of the received symbol clock.

FIG. 2 is a block diagram showing the internal configuration of the error correction circuit 103. In FIG. 2, reference numeral 104 denotes an error position polynomial / error evaluation polynomial calculation circuit that inputs the syndrome 2 and outputs an error position polynomial 5 and an error evaluation polynomial 6. 105, the delay packet 3, the error locator polynomial 5, and the error evaluation polynomial 6 are input, and the error locator polynomial 5 is input.
This is a correction circuit that obtains an error included in the delay packet 3 from the error evaluation polynomial 6, removes the error from the delay packet 3, and outputs a decoded packet 4.

FIG. 3 is a block diagram showing the internal configuration of the error position polynomial / error evaluation polynomial calculation circuit 104. In FIG. 3, 8 and 9 are candidates for an error evaluation polynomial.
10 and 11 are error position polynomial candidates. 106
Inputs the syndrome 2 as an initial value, then sequentially inputs the output of the Galois field arithmetic circuit to the first stage, performs a shift operation, outputs the data of the last stage, and corrects the stored data after the operation is completed. The shift register 107 that outputs as the evaluation polynomial candidate 8 inputs a constant as an initial value, and then sequentially inputs the Galois field arithmetic circuit output to the first stage, performs a shift operation, and outputs data of the last stage. After completion of the operation, the shift register 108 outputs the stored data as a candidate 9 for the error evaluation polynomial. A shift register 108 inputs a constant as an initial value, and then sequentially inputs the output of the Galois field arithmetic circuit to the first stage to perform a shift operation. To output the data of the last stage, and after the operation, output the stored data as a candidate 10 for the error locator polynomial.
In step 09, a constant is input as an initial value, and then the output of the Galois field arithmetic circuit is sequentially input to the first stage, a shift operation is performed, the data of the final stage is output, and after the operation is completed, the stored data is read out. This is a shift register that outputs as an error locator polynomial candidate 11.

Reference numeral 110 denotes shift registers 106 to 109
Input the data of the last stage, perform Galois field arithmetic,
The Galois field arithmetic circuit 111 for outputting the result includes error evaluation polynomial candidates 8 and 9 and error position polynomial candidates 10 and 11
, And outputs the error position polynomial 5 and the error evaluation polynomial 6.

The operation of the thus configured Reed-Solomon error correction circuit of this embodiment will be described.

The memory 101 receives the received packet 1, delays it by two packets, and outputs it as a delayed packet 3. This corresponds to the fact that the syndrome generation circuit 102 and the error correction circuit 103 have a two-stage pipeline configuration for each packet.

The syndrome generation circuit 102 receives the received packet 1 and outputs a syndrome 2.

The error correction circuit 103 receives the syndrome 2 and the delay packet 3 and calculates an error position polynomial 5 and an error evaluation polynomial 6 from the syndrome 2 by an error position polynomial / error evaluation polynomial calculation circuit 104. 10
In step 5, the error contained in the delay packet 3 is obtained from the error position polynomial 5 and the error evaluation polynomial 6, the error is removed from the delay packet 3, and the decoded packet 4 is output.

The syndrome generation circuit 102 and the error correction circuit 103 perform a parallel operation by pipeline processing for each packet.

The error correction circuit 103 operates in synchronization with the clock 7 having a cycle of 1/4 of the cycle of the received symbol clock.

The operation of the error position polynomial / error evaluation polynomial calculation circuit 104 inside the error correction circuit 103 will be described.

The shift register 106 has the syndrome 2
And the shift registers 107 to 109 store constants,
Enter as initial value.

Thereafter, the shift registers 106 to 109
Sequentially inputs the output of the Galois field arithmetic circuit 110 to the first stage, performs a shift operation, and outputs the data of the last stage.

The Galois field arithmetic circuit 110 receives the data of the last stage of the shift registers 106 to 109, performs a Galois field operation, and outputs the result.

After the operation is completed, the shift registers 106 to 10
Reference numeral 9 outputs the stored data as error evaluation polynomial candidates 8 and 9 and error location polynomial candidates 10 and 11, respectively.

The selector 111 receives the error evaluation polynomial candidates 8 and 9 and the error position polynomial candidates 10 and 11 and outputs an error position polynomial 5 and an error evaluation polynomial 6.

By performing such an operation, the Reed-Solomon error correction circuit of the present embodiment performs error correction.

As described above, the Reed-Solomon error correction circuit according to the embodiment of the present invention performs the same operation as the conventional Reed-Solomon error correction circuit. However, an error locator polynomial derivation circuit of the conventional Reed-Solomon error correction circuit (corresponding to the error locator polynomial / error evaluation polynomial calculation circuit of the Reed-Solomon error correction circuit of the present invention) has many Galois fields between the shift registers. While the arithmetic circuit is provided, the error position polynomial / error evaluation polynomial calculation circuit 104 of the Reed-Solomon error correction circuit of the present embodiment is provided.
Has no Galois field arithmetic circuit between the registers of the shift register, and has only a Galois field arithmetic circuit that receives the output of the last stage of the shift register as input. Therefore, the hardware scale is small.

Therefore, since the internal delay and the power consumption are small, a high-speed clock can be used. As described above, the operation is performed in synchronization with the clock 7 having a quarter of the cycle of the received symbol clock. It becomes possible. Therefore, unlike the Reed-Solomon error correction circuit according to the present embodiment, the error position polynomial / error evaluation polynomial calculation circuit 1 which does not include the Galois field arithmetic circuit between the shift registers.
The configuration of No. 04 can cope with sufficiently high-speed processing, and can cope with high-speed processing by parallel operation by two-stage pipeline processing.
As a result, since the memory 101 only needs to hold data for two packets, the hardware scale is further reduced.

In the above description, the error correction circuit 10
3 is configured to operate with a clock having a cycle of 1/4 of the cycle of the received symbol clock, but other cycles, for example, 1/2 or 1/8 can be used.

In the above description, the error locator polynomial
Although four shift registers are provided in the error evaluation polynomial calculation circuit 104, other numbers may be used. For example, the present invention can be embodied in various forms, such as vertically arranging two pieces or dividing it into eight pieces.

Furthermore, inside the error position polynomial / error evaluation polynomial calculation circuit 104, the output of the last stage of the shift register is input again to the first stage of the shift register via the Galois field arithmetic circuit, so that the output of the shift register appears to be apparent. A Galois field arithmetic circuit is provided between the registers, and the same operation as the configuration provided in the subsequent stage of the shift register can be performed.

According to the present invention, the packet received is Reed-Solomon coded and transmitted without being caught by any difference between these small forms, performs Reed-Solomon decoding on the received packet, and outputs the decoded packet. In a Reed-Solomon error correction circuit, a memory for inputting a received packet, delaying and outputting as a delayed packet, a syndrome generating circuit for inputting the received packet and outputting a syndrome, and inputting the delayed packet and the syndrome,
An error correction circuit that outputs a decoded packet, the error correction circuit inputs a syndrome, outputs an error position polynomial and an error evaluation polynomial, an error position polynomial / error evaluation polynomial calculation circuit, and a delay packet and an error position polynomial And an error evaluation polynomial, an error locator polynomial and an error evaluation polynomial, determine an error contained in the delay packet, remove the error from the delay packet, and output a decoded packet. The error evaluation polynomial calculation circuit includes a plurality of shift registers and a Galois field arithmetic circuit that receives the output of the shift register last stage as an input.The syndrome generation circuit and the error correction circuit
The parallel operation is performed by pipeline processing, and the error correction circuit performs 1 / N (N ≧ 1; N) of the cycle of the received symbol clock.
(Integral). It operates in synchronization with a clock having a cycle of (integer), thereby supporting high-speed processing with a small hardware scale.

[0040]

As described above, according to the present invention, a Reed-Solomon error correction circuit capable of high-speed processing with a small hardware scale can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a Reed-Solomon error correction circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram showing an internal configuration of an error correction circuit 103;

FIG. 3 shows an error location polynomial / error evaluation polynomial calculation circuit 10
4 is a block diagram showing the internal configuration of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Received packet 2 Syndrome 3 Delayed packet 4 Decoded packet 5 Error location polynomial 6 Error evaluation polynomial 7 Clock of 1/4 cycle of the received symbol clock 8,9 Error evaluation polynomial candidate 10,11 Error location polynomial candidate 101 Memory 102 Syndrome generation circuit 103 Error correction circuit 104 Error position polynomial / error evaluation polynomial calculation circuit 105 Correction circuit 106 to 109 Shift register 110 Galois field arithmetic circuit 111 Selector

Claims (1)

[Claims] 1. A Reed-Solomon error correction circuit that receives a Reed-Solomon encoded and transmitted packet, performs Reed-Solomon decoding on the received packet, and outputs a decoded packet. A memory that outputs the received packet as a delayed packet, a syndrome generation circuit that inputs the received packet, and outputs a syndrome, and an error correction circuit that inputs the delayed packet and the syndrome and outputs the decoded packet, The error correction circuit inputs the syndrome, outputs an error locator polynomial and an error evaluation polynomial, an error locator polynomial / error evaluation polynomial calculator, and receives the delay packet, the error locator polynomial, and the error evaluation polynomial. And calculating the delay packet from the error locator polynomial and the error evaluation polynomial. A correction circuit for determining an error included in the delay packet, removing the error from the delayed packet, and outputting the decoded packet. The error position polynomial / error evaluation polynomial calculation circuit includes a plurality of shift registers and a final shift register. A Galois field arithmetic circuit having a stage output as an input, wherein the syndrome generation circuit and the error correction circuit perform a parallel operation by pipeline processing for each packet, and the error correction circuit has a cycle of a reception symbol clock. Of 1
A Reed-Solomon error correction circuit that operates in synchronization with a clock having a period of / N (N ≧ 1; N is an integer).