JPH1012814A - Semiconductor stack - Google Patents

Semiconductor stack

Info

Publication number
JPH1012814A
JPH1012814A JP17747396A JP17747396A JPH1012814A JP H1012814 A JPH1012814 A JP H1012814A JP 17747396 A JP17747396 A JP 17747396A JP 17747396 A JP17747396 A JP 17747396A JP H1012814 A JPH1012814 A JP H1012814A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor
semiconductor element
semiconductor elements
water
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17747396A
Other languages
Japanese (ja)
Inventor
Yoshie Kaneda
美江 金田
Kenichi Onda
謙一 恩田
Hiroshi Narita
博 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17747396A priority Critical patent/JPH1012814A/en
Publication of JPH1012814A publication Critical patent/JPH1012814A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the fall of the energizable current by housing a semiconductor element of a different-diameter electrode in a semiconductor stack incorporated without deviated weight, for improved reliability of the semiconductor element. SOLUTION: Related to a semiconductor stack comprising different multiple pressure welding type semiconductor elements 2, 4 and 44 of electrode diameters 3, 5 and 45 arrayed in series, a water-cooling fin 1 for cooling the semiconductor elements 2, 4 and 44, and an electrode lead-out metal plate 6, among the multiple pressure welding type semiconductor elements 2, 4 and 44, the semiconductor element 2 having the electrode of largest diameter is, through the water-cooling fin 1, adjoined by the semiconductor element 4 having the electrode of the second largest diameter, for arraying. Thus, a deviated weight applied to a periphery part of the semiconductor elements having the electrode of largest diameter is reduced, so pressure welding at the electrode surface of largest diameter is made even, for even flow of current inside the semiconductor element.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、圧接型の半導体素
子を複数個直列に並べて構成した半導体スタックに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor stack in which a plurality of press-contact type semiconductor elements are arranged in series.

【0002】[0002]

【従来の技術】一般に、電力変換装置に使用されている
半導体素子には、図8に示すように、スイッチ素子とダ
イオードがある。ここで、電力変換装置が負荷側から電
力を回生する時をみると、スイッチ素子のゲートタンオ
フサイリスタ28〜31に流れる電流と同じ電流が還流
ダイオード32〜35に流れる。しかしながら、還流ダ
イオード32〜35は、ゲートタンオフサイリスタ28
〜31に比べて、電流密度が高いため、還流ダイオード
32〜35の電極径はゲートタンオフサイリスタ28〜
31より小さくなる。また、スナバダイオード20〜2
3は、瞬時的にゲートタンオフサイリスタ28〜31に
流れる電流と同じ電流が流れるが、平均電流が小さいた
め、還流ダイオード32〜35よりさらに小さい電極径
となる。このように、電力変換装置には異なる電極径を
持つ半導体素子が少なくとも3種類用いられている。こ
のような電極径の異なる半導体素子を水冷フィンを有す
るスタックに収めるとき、従来は、一般に同一の電極径
をもつ半導体素子同志を同一スタック内で水冷フィンを
介して狭持圧接する構造をとっている。しかし、この構
成をとると、スタック間に配線が生じ、この配線のイン
ダクタンスの低減が図れないため、半導体素子に生じる
サージ電圧や高周波の振動電圧、振動電流等が大きくな
る、という問題がある。そこで、スタック間の配線を回
避するために、電極径が異なる半導体素子同志を水冷フ
ィンを介してスタックに収め、狭持圧接することが行わ
れている。
2. Description of the Related Art Generally, a semiconductor element used in a power conversion device includes a switch element and a diode as shown in FIG. Here, when the power converter regenerates power from the load side, the same current as the current flowing through the gate tan-off thyristors 28 to 31 of the switch element flows through the freewheel diodes 32 to 35. However, the free-wheeling diodes 32 to 35 are
Since the current density is higher than that of the rectifier diodes 32 to 35, the electrode diameter of the return diodes 32 to 35 is
It becomes smaller than 31. In addition, snubber diodes 20 to 2
In No. 3, the same current as the current flowing through the gate tan-off thyristors 28 to 31 flows instantaneously, but since the average current is small, the electrode diameter becomes smaller than that of the freewheel diodes 32 to 35. Thus, at least three types of semiconductor elements having different electrode diameters are used in the power converter. Conventionally, when such semiconductor elements having different electrode diameters are accommodated in a stack having water-cooled fins, generally, semiconductor elements having the same electrode diameter have a structure in which the semiconductor elements having the same electrode diameter are sandwiched and pressed through water-cooled fins in the same stack. I have. However, with this configuration, a wiring is generated between the stacks, and the inductance of the wiring cannot be reduced. Therefore, there is a problem that a surge voltage, a high-frequency vibration voltage, a vibration current, and the like generated in the semiconductor element increase. Therefore, in order to avoid wiring between the stacks, semiconductor elements having different electrode diameters are accommodated in the stacks via water-cooled fins, and are pressed in a narrow pressure.

【0003】[0003]

【発明が解決しようとする課題】しかし、このような電
極径が異なる半導体素子同志を狭持圧接した半導体スタ
ックであっても、次の問題がある。すなわち、電極径が
大きな半導体素子と電極径が小さな半導体素子が水冷フ
ィンを介して隣接する部分では、電極径の大きな半導体
素子の電極周辺部で加重が低下し、中心部で加重が高く
なる。この状態の半導体素子内部のシリコンウェハと電
極の接触する部分をみると、加重の高い中心部では接触
抵抗が低くなり、逆に、周辺部では接触抵抗が高くな
る。この結果、半導体素子を流れる電流は、中心部に集
中して流れることになる。また、加重の低い電極周辺部
ではシリコンウェハと電極面の熱抵抗が大きくなり、半
導体の周辺部では温度上昇が大きくなってしまう。この
ような半導体素子内部の電流の集中や局部的な温度上昇
は、半導体素子の信頼性や通電可能電流の低下を引き起
こす。このような問題は、電極径の差が大きな半導体素
子同志を水冷フィンを介して圧接するほど顕在化する。
However, even a semiconductor stack in which semiconductor elements having different electrode diameters are held in pressure contact with each other has the following problem. That is, in a portion where a semiconductor element having a large electrode diameter and a semiconductor element having a small electrode diameter are adjacent to each other via a water-cooled fin, the load decreases at the periphery of the electrode of the semiconductor element having a large electrode diameter and increases at the center. Looking at the contact portion between the electrode and the silicon wafer inside the semiconductor element in this state, the contact resistance is low in the central portion where the load is high, and conversely, the contact resistance is high in the peripheral portion. As a result, the current flowing through the semiconductor element flows intensively at the center. In addition, the thermal resistance between the silicon wafer and the electrode surface increases in the peripheral portion of the electrode where the load is low, and the temperature rise increases in the peripheral portion of the semiconductor. Such concentration of the current inside the semiconductor element and a local rise in temperature cause a decrease in the reliability of the semiconductor element and a current that can flow. Such a problem becomes more apparent as the semiconductor elements having a large difference in electrode diameter are pressed against each other via water-cooled fins.

【0004】本発明の課題は、異径電極の半導体素子を
偏加重なく一体化した半導体スタックに収めると共に、
半導体素子の信頼性を向上させ、通電可能電流の低下を
防止することにある。
[0004] It is an object of the present invention to accommodate semiconductor elements having different-diameter electrodes in an integrated semiconductor stack without biasing load.
An object of the present invention is to improve the reliability of a semiconductor element and prevent a decrease in a current that can flow.

【0005】[0005]

【課題を解決するための手段】上記課題は、直列に配列
される電極径の異なる複数の圧接型の半導体素子のう
ち、最大径の電極をもつ半導体素子に水冷フィンを介し
て2番目に大きい径の電極をもつ半導体素子を隣接して
配列することによって、解決される。また、直列に配列
される電極径の異なる複数の圧接型の半導体素子のう
ち、最大径の電極をもつ半導体素子がゲートターンオフ
サイリスタ(GTO)であるとき、GTOのカソード電
極側に水冷フィンを介して2番目に大きい径の電極をも
つ半導体素子を隣接して配列することによって、解決さ
れる。また、直列に配列される電極径の異なる複数の圧
接型の半導体素子を配列するとき、電極径の異なるそれ
ぞれの圧接型の半導体素子の間に水冷フィンを介して高
剛性の金属導体を配置することによって、解決される。
ここで、直列に配列される電極径の異なる複数の圧接型
の半導体素子は、電力変換装置の上アーム回路および上
アーム回路を形成するクランプダイオード、横流防止ダ
イオード、スナバダイオード、ゲートターンオフサイリ
スタ(GTO)および還流ダイオードであり、また、電
力変換装置の上アーム回路および上アーム回路を形成す
る半導体素子群を上アーム半導体スタックと下アーム半
導体スタックに分割すると共に併設し、上下アーム回路
間の配線を短くする。
An object of the present invention is to provide, among a plurality of press-contact type semiconductor elements having different electrode diameters arranged in series, a semiconductor element having an electrode having the largest diameter via a water-cooled fin. The problem is solved by arranging adjacent semiconductor elements having diameter electrodes. When a semiconductor element having the largest diameter electrode among a plurality of pressure-contact type semiconductor elements having different electrode diameters arranged in series is a gate turn-off thyristor (GTO), a water-cooled fin is provided on the cathode electrode side of the GTO. The problem is solved by arranging adjacently the semiconductor elements having the second largest diameter electrodes. Further, when arranging a plurality of press-contact type semiconductor elements having different electrode diameters arranged in series, a high-rigidity metal conductor is disposed between the press-contact-type semiconductor elements having different electrode diameters via water-cooling fins. It is solved by.
Here, the plurality of press-contact type semiconductor elements having different electrode diameters arranged in series include a clamp diode, a cross current prevention diode, a snubber diode, and a gate turn-off thyristor (GTO) forming the upper arm circuit of the power converter and the upper arm circuit. ) And a return diode, and the upper arm circuit and the semiconductor element group forming the upper arm circuit of the power conversion device are divided into an upper arm semiconductor stack and a lower arm semiconductor stack, and are provided side by side. shorten.

【0006】本発明は、最大径の電極をもつ半導体素子
の周辺部にかかる偏加重を緩和し、最大径の電極面の圧
接を均一化する。これにより、電流が半導体素子内部を
均一に流れ、半導体素子の信頼性を向上させ、通電可能
電流の低下を防止する。また、ゲートターンオフサイリ
スタ(GTO)のカソード側の電極面が均一に加重され
るように半導体素子を配置するため、半導体素子内部に
集中する電流を緩和する。また、剛性の高い金属導体に
よって水冷フィンの剛性を補い、電極径の大きい半導体
素子の電極面の加重を均一化するため、電流を半導体素
子内部に均一に流す。また、電力変換装置の配線インダ
クタンスを低減し、高周波振動を抑制する。これによ
り、電力変換装置の低損失、高信頼性が図られ、小形化
も可能になる。
The present invention alleviates the biasing load applied to the peripheral portion of the semiconductor element having the largest diameter electrode and makes the pressure contact of the largest diameter electrode surface uniform. As a result, the current flows uniformly inside the semiconductor element, thereby improving the reliability of the semiconductor element and preventing a decrease in the current that can be passed. In addition, since the semiconductor element is arranged so that the electrode surface on the cathode side of the gate turn-off thyristor (GTO) is uniformly weighted, current concentrated inside the semiconductor element is reduced. In addition, in order to supplement the rigidity of the water-cooled fins with a highly rigid metal conductor and to make the load on the electrode surface of the semiconductor element having a large electrode diameter uniform, a current is uniformly flowed inside the semiconductor element. Further, the wiring inductance of the power converter is reduced, and high-frequency vibration is suppressed. Thereby, low loss and high reliability of the power converter are achieved, and downsizing is possible.

【0007】[0007]

【発明の実施の形態】以下、本発明を実施形態の図面を
用いて説明する。図1は、本発明に基づく半導体スタッ
クの一実施形態を示し、異径電極の半導体素子を同一の
半導体スタックに組み込んだ平面図である。図1におい
て、1は水冷フィン、2は一体の半導体スタック内の圧
接型半導体素子のうち、最大径の電極をもつ半導体素
子、3は半導体素子2の両電極、4は一体の半導体スタ
ック内の圧接型半導体素子のうち、2番目に大きい径の
電極をもつ半導体素子、5は半導体素子4の両電極、4
4は一体の半導体スタック内の圧接型半導体素子のう
ち、3番目に大きい径の電極をもつ半導体素子、45は
半導体素子44の両電極、6は電極の取り出し用金属板
を表わす。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the drawings of embodiments. FIG. 1 is a plan view showing an embodiment of a semiconductor stack according to the present invention, in which semiconductor elements having electrodes having different diameters are incorporated in the same semiconductor stack. In FIG. 1, reference numeral 1 denotes a water-cooled fin, 2 denotes a semiconductor element having the largest diameter electrode among the pressure-contact type semiconductor elements in the integrated semiconductor stack, 3 denotes both electrodes of the semiconductor element 2, and 4 denotes an electrode in the integrated semiconductor stack. Among the press-contact type semiconductor elements, a semiconductor element having an electrode having the second largest diameter, 5 are both electrodes of the semiconductor element 4,
Reference numeral 4 denotes a semiconductor element having a third largest diameter electrode among the press-contact type semiconductor elements in the integrated semiconductor stack, 45 denotes both electrodes of the semiconductor element 44, and 6 denotes a metal plate for extracting an electrode.

【0008】本実施形態は、各1個の最大径の電極をも
つ半導体素子2および2番目に大きい径の電極をもつ半
導体素子4と、2個の3番目に大きい径の電極をもつ半
導体素子44を圧接する場合を示し、図示のように、最
大径の電極3をもつ半導体素子2の一方に水冷フィン1
を介して2番目に大きい径の電極5をもつ半導体素子4
を配列し、さらに、水冷フィン1を介して3番目に大き
い径の電極45をもつ半導体素子44を配列する。ま
た、最大径の電極をもつ半導体素子2の他方に水冷フィ
ン1を介して3番目に大きい径の電極45をもつ半導体
素子44を配列し、電極取り出し用金属板を設ける。こ
のように、各半導体素子を配列した構造とすると、最大
径の半導体素子2の電極面3と2番目に大きい径の半導
体素子の電極5が接する面積は、最大径の半導体素子2
の電極面3と3番目に大きい径の半導体素子の電極面4
5が接する面積より広くなる。このため、水冷フィン1
を介して圧接するとき、最大径の電極3と3番目に大き
い径の電極45の間に介在する水冷フィン1は、電極面
の小さい電極面45の側に大きく反り、大きい電極径の
電極3の圧接が不十分になるに比し、最大径の電極3と
2番目に大きい径の電極5の間に介在する水冷フィン1
は、電極面45の側への反りが小さく、大きい電極径の
電極3が均一に圧接されることになる。
In this embodiment, a semiconductor element 2 having one largest diameter electrode and a semiconductor element 4 having a second largest diameter electrode and a semiconductor element 2 having two third largest diameter electrodes are provided. 44 shows a case where the water-cooled fin 1 is attached to one of the semiconductor elements 2 having the electrode 3 having the largest diameter.
Element 4 having an electrode 5 of the second largest diameter via
Are arranged, and a semiconductor element 44 having an electrode 45 having the third largest diameter is arranged via the water-cooled fins 1. Further, the semiconductor element 44 having the third largest diameter electrode 45 is arranged on the other side of the semiconductor element 2 having the largest diameter electrode via the water-cooled fins 1, and a metal plate for taking out the electrode is provided. As described above, if each semiconductor element is arranged, the area where the electrode surface 3 of the semiconductor element 2 having the largest diameter and the electrode 5 of the semiconductor element having the second largest diameter are in contact with each other is equal to the semiconductor element 2 having the largest diameter.
Electrode surface 3 and the electrode surface 4 of the semiconductor element having the third largest diameter
5 is larger than the area in contact. Therefore, the water-cooled fin 1
When pressed against each other, the water-cooled fin 1 interposed between the electrode 3 having the largest diameter and the electrode 45 having the third largest diameter is greatly warped toward the electrode surface 45 having the smaller electrode surface, and the electrode 3 having the larger electrode diameter is formed. The water-cooled fin 1 interposed between the electrode 3 having the largest diameter and the electrode 5 having the second largest diameter,
In this case, the warp toward the electrode surface 45 is small, and the electrode 3 having a large electrode diameter is uniformly pressed.

【0009】本実施形態では、異径電極の半導体素子を
同一の半導体スタックに組み込むとき、最大径の電極を
もつ半導体素子2に隣接して2番目に大きい径の電極5
をもつ半導体素子4を配列することにより、最大径の電
極面の圧接が均一化され、これにより、電流が半導体素
子内部を均一に流れ、従来例のような電流が半導体素子
内部に集中したり、また、局部的な温度上昇を引き起こ
す、という弊害をなくすることができる。この結果、半
導体素子の信頼性を向上させ、通電可能電流の低下を防
止することができる。なお、本実施形態において、2番
目に大きい径の電極5をもつ半導体素子4が2個以上使
用するときは、最大径の電極をもつ半導体素子2の両側
に隣接することは云うまでもない。
In this embodiment, when the semiconductor elements having different diameter electrodes are incorporated into the same semiconductor stack, the second largest diameter electrode 5 is located adjacent to the semiconductor element 2 having the largest diameter electrode.
By arranging the semiconductor elements 4 having the same shape, the pressure contact of the electrode surface having the maximum diameter is made uniform, whereby the current flows uniformly inside the semiconductor element, and the current as in the conventional example concentrates inside the semiconductor element. In addition, it is possible to eliminate the adverse effect of causing a local temperature rise. As a result, it is possible to improve the reliability of the semiconductor element and prevent a decrease in the current that can flow. In the present embodiment, when two or more semiconductor elements 4 having the second largest diameter electrode 5 are used, it is needless to say that they are adjacent to both sides of the semiconductor element 2 having the largest diameter electrode.

【0010】ここで、図8に示した電力変換装置に用い
られる半導体素子の例では、スイッチ素子28〜31の
電極径が最も大きく、次いで、還流ダイオード32〜3
5、スナバダイオード20〜23の順になる。この場
合、スイッチ素子の両側にスナバダイオードを配置した
のでは、スイッチ素子の上下に設けられる水冷フィン
は、それぞれスナバダイオード側に反ることになり、ス
イッチ素子の両方の電極側で加重が低下することにな
る。このような問題を軽減するため、本実施形態では、
最も大きい電極径のスイッチ素子に隣接して2番目に大
きい電極径の還流ダイオードを配置することにした。
Here, in the example of the semiconductor element used for the power converter shown in FIG. 8, the electrode diameter of the switch elements 28 to 31 is the largest, and then the freewheel diodes 32 to 3
5. The order of the snubber diodes 20 to 23 is as follows. In this case, if the snubber diodes are arranged on both sides of the switch element, the water-cooled fins provided above and below the switch element are respectively warped to the snubber diode side, and the load is reduced on both electrode sides of the switch element. Will be. In order to reduce such a problem, in the present embodiment,
The reflux diode having the second largest electrode diameter is arranged adjacent to the switch element having the largest electrode diameter.

【0011】図2は、水冷フィン1の上面図、図3は、
水冷フィン1の断面図である。図中、42は水路(パイ
プ)、43は水の出入り口、41は水冷フィン1ふた、
49はろう付け部を示す。水冷フィン1は、水の出入り
口43から水をパイプ42に流し、半導体素子を冷却す
る。
FIG. 2 is a top view of the water-cooled fin 1, and FIG.
FIG. 3 is a cross-sectional view of the water cooling fin 1. In the figure, 42 is a water channel (pipe), 43 is a water inlet / outlet, 41 is a water-cooled fin 1 lid,
Reference numeral 49 denotes a brazing portion. The water-cooled fins 1 flow water from the water inlet / outlet 43 into the pipe 42 to cool the semiconductor element.

【0012】図4は、本発明の他の実施形態を示す。図
4において、図1と同一部分に同一符号を付ける。本実
施形態では、最大径の電極をもつ半導体素子をゲートタ
ーンオフサイリスタ(GTO)7とし、2番目に大きい
電極をもつ半導体素子4をGTO7のカソード側に配列
する。ここで、図5、図6を用いて、GTO7を圧接し
たときの電流の流れを説明する。図5は、カソード9側
の電極に偏加重が生じ、図6は、アノード8側の電極に
偏加重が生じた場合を示す。図中、8はGTOのアノー
ド側の電極、9はGTOのカソード側の電極、46はG
TO、48はユニットGTOを表わす。図5に示すよう
に、カソード側の電極9に加圧の強い部分47が生じた
場合、加圧の強い部分47の一つのユニットGTO48
の接触抵抗が低くなり、電流は、この接触抵抗の小さい
ユニットGTO48に集中(矢印のように)することに
なる。このため、カソード側の電極9における電流集中
は避けられない。一方、図6に示すように、アノード側
の電極8に加圧の強い部分47が生じた場合、加圧の強
い部分47の一つのユニットGTO48の接触抵抗が低
くなり、電流は、この接触抵抗の小さいユニットGTO
48に集中するが、カソード側の電極9の加重が均一で
あれば、アノード側からカソード側に流れていく途中で
拡散(矢印のように)し、各ユニットGTO48に分散
して流れる。以上のことから、GTOのカソード側の電
極面9が均一に加重されるように半導体素子を配置する
ことが重要である。そこで、本実施形態では、図4のよ
うに、GTO7の次ぎに大きい径の電極をもつ半導体素
子4をGTOのカソード側の電極9に配列する。これに
より、本実施形態では、電流が半導体素子内部に集中す
ることを緩和することができる。
FIG. 4 shows another embodiment of the present invention. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the present embodiment, the semiconductor element having the largest diameter electrode is a gate turn-off thyristor (GTO) 7, and the semiconductor element 4 having the second largest electrode is arranged on the cathode side of the GTO 7. Here, the flow of current when the GTO 7 is pressed is described with reference to FIGS. FIG. 5 shows a case where biased load occurs on the electrode on the cathode 9 side, and FIG. 6 shows a case where biased load occurs on the electrode on the anode 8 side. In the figure, 8 is the GTO anode electrode, 9 is the GTO cathode electrode, and 46 is the GTO electrode.
TO, 48 represents the unit GTO. As shown in FIG. 5, when a strongly pressurized portion 47 is formed on the cathode 9, one unit GTO 48 of the strongly pressurized portion 47 is formed.
, The current is concentrated (as indicated by the arrow) on the unit GTO 48 having the small contact resistance. Therefore, current concentration at the cathode-side electrode 9 is inevitable. On the other hand, as shown in FIG. 6, when a strongly pressurized portion 47 is formed on the anode 8, the contact resistance of one unit GTO 48 of the strongly pressurized portion 47 decreases, and the current is reduced by the contact resistance. Small unit GTO
However, if the weight of the electrode 9 on the cathode side is uniform, it is diffused (as indicated by an arrow) while flowing from the anode side to the cathode side, and is dispersed and flows to each unit GTO 48. From the above, it is important to arrange the semiconductor elements so that the cathode-side electrode surface 9 of the GTO is uniformly weighted. Therefore, in the present embodiment, as shown in FIG. 4, the semiconductor element 4 having an electrode having the next largest diameter after the GTO 7 is arranged on the cathode 9 of the GTO. Thereby, in the present embodiment, it is possible to reduce the concentration of the current inside the semiconductor element.

【0013】図7は、本発明の他の実施形態を示す。図
4において、図1と同一部分に同一符号を付ける。図
中、10は焼きましのない高剛性の金属導体を示す。本
実施形態は、3番目に大きい径の電極をもつ半導体素子
44と最大径の電極をもつ半導体素子の間、また、2番
目に大きい径の電極をもつ半導体素子44と最大径の電
極をもつ半導体素子の間にそれぞれ水冷フィン1を介し
て金属導体10を挿入する。
FIG. 7 shows another embodiment of the present invention. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the drawing, reference numeral 10 denotes a high-rigidity metal conductor without annealing. The present embodiment has the semiconductor element 44 having the third largest diameter electrode and the semiconductor element having the largest diameter electrode, and has the semiconductor element 44 having the second largest diameter electrode and the largest diameter electrode. The metal conductors 10 are inserted between the semiconductor elements via the water cooling fins 1 respectively.

【0014】ここで、図3に示すように、水冷フィン1
にはろう付け部49がある。このろう付け部49は、水
路42を塞ぐためのふた41をろう付けして水漏れを防
止するものであり、ろう付けの際、水冷フィン1は一旦
高温状態になり、その後ゆっくり冷されて室温に至る。
この工程で水冷フィン1は、焼きましを受けるため、剛
性が弱くなる。このため、電極径の小さい半導体素子と
電極径の大きい半導体素子を隣接させるときに、電極径
の小さい半導体素子側に水冷フィン1が反り、電極径の
大きい半導体素子の電極面では、周辺の加重が低下す
る、という問題が生じる。
Here, as shown in FIG.
Has a brazing portion 49. The brazing portion 49 is for brazing the lid 41 for closing the water channel 42 to prevent water leakage. At the time of brazing, the water-cooled fins 1 are once brought to a high temperature state, and then slowly cooled to room temperature. Leads to.
In this step, the water-cooled fins 1 are subjected to annealing, and thus have reduced rigidity. For this reason, when a semiconductor element having a small electrode diameter and a semiconductor element having a large electrode diameter are adjacent to each other, the water-cooling fin 1 warps toward the semiconductor element having a small electrode diameter, and the peripheral surface of the electrode surface of the semiconductor element having a large electrode diameter is weighted. Is reduced.

【0015】そこで、本実施形態は、電極径の小さい半
導体素子と電極径の大きい半導体素子の間に水冷フィン
1を介して金属導体10を挿入し、剛性の高い金属導体
10が水冷フィン1の剛性を補い、電極径の大きい半導
体素子の電極面の加重を均一化する。これにより、本実
施形態では、電流が半導体素子内部を均一に流れ、従来
例のような電流が半導体素子内部に集中したり、また、
局部的な温度上昇を引き起こす、という弊害をなくする
ことができ、この結果、半導体素子の信頼性を向上さ
せ、通電可能電流の低下を防止することができる。
Therefore, in this embodiment, a metal conductor 10 is inserted between a semiconductor element having a small electrode diameter and a semiconductor element having a large electrode diameter via a water-cooling fin 1, and the metal conductor 10 having high rigidity is The rigidity is compensated and the load on the electrode surface of the semiconductor element having a large electrode diameter is made uniform. Thereby, in the present embodiment, the current flows uniformly inside the semiconductor element, and the current as in the conventional example concentrates inside the semiconductor element.
The adverse effect of causing a local temperature rise can be eliminated, and as a result, the reliability of the semiconductor element can be improved and a decrease in the current that can be conducted can be prevented.

【0016】図9は、本発明を図8に示す電力変換装置
に用いられる半導体素子に適用した他の実施形態を示
す。ここで、図8の電力変換装置は、1相分の回路構成
37を示し、同一構成が3相あり、3相の出力を負荷
(図示せず)に供給する。1相分の回路構成37は、直
流電源11、電源コンデンサ12,13、クランプコン
デンサ14,15、クランプダイオード16,17、横
流防止タイオード18,19、スナバダイオード20,
21,22,23、スナバコンデンサ24,25,2
6,27、GTO28,29,30,31、還流ダイオ
ード32,33,34,35、アノードリアクトル36
からなる。また、半導体素子群38を上アーム回路、半
導体素子群39を下アーム回路とする。
FIG. 9 shows another embodiment in which the present invention is applied to a semiconductor element used in the power converter shown in FIG. Here, the power converter of FIG. 8 shows a circuit configuration 37 for one phase, which has the same configuration in three phases and supplies three-phase outputs to a load (not shown). The circuit configuration 37 for one phase includes a DC power supply 11, power supply capacitors 12 and 13, clamp capacitors 14 and 15, clamp diodes 16 and 17, cross current prevention diodes 18 and 19, a snubber diode 20,
21, 22, 23, snubber capacitors 24, 25, 2
6, 27, GTOs 28, 29, 30, 31, reflux diodes 32, 33, 34, 35, anode reactor 36
Consists of The semiconductor element group 38 is an upper arm circuit, and the semiconductor element group 39 is a lower arm circuit.

【0017】図9において、図8の回路図と同一部分は
同一符号を付ける。図中、40は絶縁スペーサを示す。
図9の左側は上アーム回路38の半導体スタックであ
り、半導体素子は、図示の上から下に向けて、横流防止
タイオード18、スナバダイオード20、GTO28、
還流ダイオード32の順に配列し、絶縁スペーサ40を
介してクランプダイオード16、さらに絶縁スペーサ4
0を介して還流ダイオード33、GTO31、スナバダ
イオード22の順に配列する。また、水冷フィン1は各
半導体素子間に配置し、還流ダイオード32とクランプ
ダイオード16および還流ダイオード33とクランプダ
イオード16のそれぞれの水冷フィン1の間に絶縁スペ
ーサ40を挿入する。そして、図9の右側は下アーム回
路39の半導体スタックであり、半導体素子は、図示の
上から下に向けて、横流防止タイオード19、スナバダ
イオード21、GTO29、還流ダイオード35の順に
配列し、絶縁スペーサ40を介してクランプダイオード
17、さらに絶縁スペーサ40を介して還流ダイオード
34、GTO28、スナバダイオード23の順に配列す
る。また、水冷フィン1は各半導体素子間に配置し、還
流ダイオード35とクランプダイオード17および還流
ダイオード34とクランプダイオード17のそれぞれの
水冷フィン1の間に絶縁スペーサ40を挿入する。
In FIG. 9, the same parts as those in the circuit diagram of FIG. In the figure, reference numeral 40 denotes an insulating spacer.
The left side of FIG. 9 shows a semiconductor stack of the upper arm circuit 38. The semiconductor elements are arranged from the top to the bottom in the figure, and the anti-cross current diode 18, the snubber diode 20, the GTO 28,
The freewheeling diodes 32 are arranged in this order, and the clamp diode 16 and the insulating spacer 4 are interposed via the insulating spacer 40.
The freewheeling diode 33, the GTO 31, and the snubber diode 22 are arranged in this order via 0. Further, the water-cooled fins 1 are arranged between the respective semiconductor elements, and insulating spacers 40 are inserted between the respective water-cooled fins 1 of the freewheel diode 32 and the clamp diode 16 and between the freewheel diode 33 and the clamp diode 16. The right side of FIG. 9 is a semiconductor stack of the lower arm circuit 39. The semiconductor elements are arranged in the order of the crossflow prevention diode 19, the snubber diode 21, the GTO 29, and the freewheel diode 35 from the top to the bottom of the figure. The clamp diode 17 is arranged via the spacer 40, and the freewheel diode 34, the GTO 28, and the snubber diode 23 are arranged in this order via the insulating spacer 40. Further, the water-cooled fins 1 are arranged between the respective semiconductor elements, and the insulating spacers 40 are inserted between the free-wheel diodes 35 and the clamp diodes 17 and between the free-wheel diodes 34 and the clamp diodes 17.

【0018】通常、上アーム回路38の半導体スタック
と下アーム回路39の半導体スタックは上下に積み重
ね、一体に構成する。このため、半導体スタックが上下
に長くなり、大型化すると共に、上下アーム回路間の配
線が長くなり、この配線によるインダクタンスが増加す
る。これに比し、図9の実施形態では、半導体スタック
を上アーム回路38の半導体スタックと下アーム回路3
9の半導体スタックに分け、図示のように併設する構成
とすることにより、半導体スタックが小型化し、同時
に、上下アーム回路間の配線が短くなり、配線によるイ
ンダクタンスが低減する。このように、図9の実施形態
では、電力変換装置に半導体素子の圧接力を改善した半
導体スタックを用い、さらに、上アーム回路の半導体ス
タックと下アーム回路の半導体スタックに分け、併設す
る構成とすることにより、配線インダクタンスの低減お
よび高周波振動の抑制が可能となり、電力変換装置の低
損失、高信頼性が図られると共に、小形化も可能にな
る。なお、図8の電力変換装置において、図4および図
7の実施形態を適用できることは云うまでもない。
Normally, the semiconductor stack of the upper arm circuit 38 and the semiconductor stack of the lower arm circuit 39 are vertically stacked and integrally formed. For this reason, the semiconductor stack becomes longer and shorter, which increases the size of the semiconductor stack. In addition, the wiring between the upper and lower arm circuits becomes longer, and the inductance due to this wiring increases. On the other hand, in the embodiment of FIG. 9, the semiconductor stack is connected to the semiconductor stack of the upper arm circuit 38 and the lower arm circuit 3.
By dividing the semiconductor stack into nine semiconductor stacks and providing them side by side as shown in the figure, the semiconductor stack is reduced in size, and at the same time, the wiring between the upper and lower arm circuits is shortened, and the inductance due to the wiring is reduced. As described above, in the embodiment of FIG. 9, the power conversion device uses a semiconductor stack in which the pressure contact force of the semiconductor element is improved, and is further divided into the semiconductor stack of the upper arm circuit and the semiconductor stack of the lower arm circuit, and is provided in parallel. By doing so, it is possible to reduce the wiring inductance and suppress high-frequency vibrations, thereby achieving low loss and high reliability of the power converter, and also enabling downsizing. It goes without saying that the embodiments of FIGS. 4 and 7 can be applied to the power converter of FIG.

【0019】[0019]

【発明の効果】以上説明したように、本発明によれば、
異径電極の半導体素子を同一の半導体スタックに組み込
むとき、最大径の電極をもつ半導体素子の周辺部にかか
る偏加重を緩和することができ、これにより、最大径の
電極面の圧接が均一化され、電流が半導体素子内部を均
一に流れ、従来例のような電流が半導体素子内部に集中
したり、また、局部的な温度上昇を引き起こす、という
弊害をなくすることができ、この結果、半導体素子の信
頼性を向上させ、通電可能電流の低下を防止することが
できる。また、ゲートターンオフサイリスタ(GTO)
のカソード側の電極面が均一に加重されるように半導体
素子を配置することにより、電流が半導体素子内部に集
中することを緩和することができる。また、剛性の高い
金属導体によって水冷フィンの剛性を補うことができ、
電極径の大きい半導体素子の電極面の加重を均一化する
ことができ、電流を半導体素子内部に均一に流すことが
可能になる。また、電力変換装置の配線インダクタンス
の低減および高周波振動の抑制が可能となり、電力変換
装置の低損失、高信頼性が図られると共に、小形化も可
能になる。
As described above, according to the present invention,
When semiconductor elements with different diameter electrodes are integrated into the same semiconductor stack, the bias load applied to the periphery of the semiconductor element having the largest diameter electrode can be reduced, thereby making the pressure contact of the largest diameter electrode surface uniform. As a result, it is possible to eliminate the disadvantage that the current flows uniformly inside the semiconductor element and that the current is concentrated inside the semiconductor element and causes a local temperature rise as in the conventional example. It is possible to improve the reliability of the element and prevent a decrease in current that can flow. Gate turn-off thyristor (GTO)
By arranging the semiconductor element such that the electrode surface on the cathode side is uniformly weighted, it is possible to reduce the concentration of the current inside the semiconductor element. In addition, the rigidity of the water-cooled fins can be supplemented by a highly rigid metal conductor,
The load on the electrode surface of the semiconductor element having a large electrode diameter can be made uniform, and the current can flow uniformly inside the semiconductor element. In addition, the wiring inductance of the power converter can be reduced and high-frequency vibration can be suppressed, so that the power converter can have low loss and high reliability, and can be downsized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に基づく半導体スタックの一実施形態FIG. 1 shows one embodiment of a semiconductor stack according to the present invention.

【図2】水冷フィンの上面図FIG. 2 is a top view of a water-cooled fin.

【図3】水冷フィンの断面図FIG. 3 is a sectional view of a water-cooled fin.

【図4】本発明の他の実施形態FIG. 4 shows another embodiment of the present invention.

【図5】ゲートターンオフサイリスタ(GTO)の断面
FIG. 5 is a sectional view of a gate turn-off thyristor (GTO).

【図6】ゲートターンオフサイリスタ(GTO)の断面
FIG. 6 is a sectional view of a gate turn-off thyristor (GTO).

【図7】本発明の他の実施形態FIG. 7 shows another embodiment of the present invention.

【図8】電力変換装置の回路図FIG. 8 is a circuit diagram of a power converter.

【図9】本発明を電力変換装置に適用した他の実施形態FIG. 9 is another embodiment in which the present invention is applied to a power converter.

【符号の説明】[Explanation of symbols]

1 水冷フィン 2 最大径の電極をもつ半導体素子 3 半導体素子2の両電極 4 2番目に大きい径の電極をもつ半導体素子 5 半導体素子4の両電極 44 3番目に大きい径の電極をもつ半導体素子 45 半導体素子44の両電極 6 電極の取り出し用金属板 7 ゲートターンオフサイリスタ(GTO) 8 ゲートターンオフサイリスタのアノード側の内部電
極 9 ゲートターンオフサイリスタのカソード側の内部電
極 10 金属導体 16、17 クランプダイオード 18、19 横流防止ダイオード 20〜23 スナバダイオード 28〜31 ゲートターンオフサイリスタ(GTO) 32〜35 還流ダイオード 40 絶縁スペーサ
DESCRIPTION OF SYMBOLS 1 Water-cooled fin 2 Semiconductor element with the largest diameter electrode 3 Both electrodes of the semiconductor element 4 4 Semiconductor element with the second largest diameter electrode 5 Both electrodes of the semiconductor element 4 44 Semiconductor element with the third largest diameter electrode 45 Both electrodes of the semiconductor element 44 6 Metal plate for extracting electrodes 7 Gate turn-off thyristor (GTO) 8 Internal electrode on the anode side of the gate turn-off thyristor 9 Internal electrode on the cathode side of the gate turn-off thyristor 10 Metal conductor 16, 17 Clamp diode 18 , 19 Cross current prevention diode 20-23 Snubber diode 28-31 Gate turn-off thyristor (GTO) 32-35 Freewheeling diode 40 Insulating spacer

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 直列に配列される電極径の異なる複数の
圧接型の半導体素子と、前記半導体素子を冷却する水冷
フィンと、電極取り出し用金属板から構成される半導体
スタックにおいて、前記複数の圧接型の半導体素子のう
ち、最大径の電極をもつ半導体素子に前記水冷フィンを
介して2番目に大きい径の電極をもつ半導体素子を隣接
して配列することを特徴とする半導体スタック。
1. A semiconductor stack comprising a plurality of press-contact type semiconductor elements having different electrode diameters arranged in series, water-cooling fins for cooling the semiconductor elements, and a metal plate for extracting electrodes, wherein the plurality of press-contact type semiconductor elements are provided. A semiconductor stack, wherein a semiconductor element having a second largest diameter electrode is arranged adjacent to a semiconductor element having a largest diameter electrode among the semiconductor elements having a maximum diameter through the water cooling fin.
【請求項2】 直列に配列される電極径の異なる複数の
圧接型の半導体素子と、前記半導体素子を冷却する水冷
フィンと、電極取り出し用金属板から構成される半導体
スタックにおいて、前記複数の圧接型の半導体素子のう
ち、最大径の電極をもつ半導体素子がゲートターンオフ
サイリスタ(GTO)であるとき、前記GTOのカソー
ド電極側に前記水冷フィンを介して2番目に大きい径の
電極をもつ半導体素子を隣接して配列することを特徴と
する半導体スタック。
2. In a semiconductor stack comprising a plurality of pressure-contact type semiconductor elements having different electrode diameters arranged in series, water-cooling fins for cooling the semiconductor elements, and a metal plate for extracting electrodes, the plurality of pressure-contact-type semiconductor elements are provided. When the semiconductor element having the largest diameter electrode among the semiconductor elements of the type is a gate turn-off thyristor (GTO), the semiconductor element having the second largest diameter electrode on the cathode electrode side of the GTO via the water-cooled fins Are arranged adjacent to each other.
【請求項3】 直列に配列される電極径の異なる複数の
圧接型の半導体素子と、前記半導体素子を冷却する水冷
フィンと、電極取り出し用金属板から構成される半導体
スタックにおいて、前記電極径の異なるそれぞれの圧接
型の半導体素子の間に前記水冷フィンを介して高剛性の
金属導体を配置することを特徴とする半導体スタック。
3. A semiconductor stack comprising a plurality of press-contact type semiconductor elements having different electrode diameters arranged in series, water-cooling fins for cooling the semiconductor elements, and an electrode extraction metal plate, wherein A semiconductor stack, wherein a high-rigidity metal conductor is disposed between different press-contact type semiconductor elements via the water-cooled fin.
【請求項4】 請求項1から請求項3のいずれかにおい
て、直列に配列される電極径の異なる複数の圧接型の半
導体素子は、電力変換装置の上アーム回路および上アー
ム回路を形成するクランプダイオード、横流防止ダイオ
ード、スナバダイオード、ゲートターンオフサイリスタ
(GTO)および還流ダイオードであることを特徴とす
る半導体スタック。
4. The pressure-contact type semiconductor element according to claim 1, wherein the plurality of pressure-contact type semiconductor elements having different electrode diameters are arranged in series, and the clamp forms an upper arm circuit and an upper arm circuit of the power converter. A semiconductor stack comprising a diode, a cross-flow prevention diode, a snubber diode, a gate turn-off thyristor (GTO) and a freewheeling diode.
【請求項5】 請求項4において、電力変換装置の上ア
ーム回路および上アーム回路を形成する半導体素子群を
上アーム半導体スタックと下アーム半導体スタックに分
割すると共に併設し、上下アーム回路間の配線を短くす
ることを特徴とする半導体スタック。
5. The power conversion device according to claim 4, wherein an upper arm circuit of the power converter and a semiconductor element group forming the upper arm circuit are divided into an upper arm semiconductor stack and a lower arm semiconductor stack and are provided side by side, and wiring between the upper and lower arm circuits is provided. A semiconductor stack characterized by shortening the length of the semiconductor stack.
JP17747396A 1996-06-18 1996-06-18 Semiconductor stack Pending JPH1012814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17747396A JPH1012814A (en) 1996-06-18 1996-06-18 Semiconductor stack

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17747396A JPH1012814A (en) 1996-06-18 1996-06-18 Semiconductor stack

Publications (1)

Publication Number Publication Date
JPH1012814A true JPH1012814A (en) 1998-01-16

Family

ID=16031540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17747396A Pending JPH1012814A (en) 1996-06-18 1996-06-18 Semiconductor stack

Country Status (1)

Country Link
JP (1) JPH1012814A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100411169C (en) * 2004-11-12 2008-08-13 国际商业机器公司 Apparatus and methods for cooling semiconductor integrated circuit chip packages

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100411169C (en) * 2004-11-12 2008-08-13 国际商业机器公司 Apparatus and methods for cooling semiconductor integrated circuit chip packages
US7888786B2 (en) 2004-11-12 2011-02-15 International Business Machines Corporation Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device
US7948077B2 (en) 2004-11-12 2011-05-24 International Business Machines Corporation Integrated circuit chip module with microchannel cooling device having specific fluid channel arrangement
US8115302B2 (en) 2004-11-12 2012-02-14 International Business Machines Corporation Electronic module with carrier substrates, multiple integrated circuit (IC) chips and microchannel cooling device

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