JPH10125696A - Manufacture of field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive reduction in source resistance and gate resistance as well as high breakdown strength by forming a T-type gate electrode at an offset position inside a recess. SOLUTION: A buffer layer 12, an active layer 13, an etching stopper layer 14 and a cap layer 15 are provided on a semi-insulating semiconductor substrate 11, and a first resist film 16 having two first openings 16a, 16b are formed thereon (a). The cap layer 15 is etched so as to form a recess 15a to be connected under two openings (b). A second resist film 17 is formed so as to form a hardly soluble resist mixed layer 18 on the interface of both resists (c). The second resist film 17 is exposed and developed, so as to form a second opening 17a in the undercut shape on the first opening 16a on one side (d). A gate electrode 20 is formed (f) by deposition (e) of a gate metal, and a lift-off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a Schottky gate type field effect transistor,
The present invention relates to a method for manufacturing a field-effect transistor having a T-type gate electrode, the T-type gate electrode being arranged in an offset state in a recess.

[0002]

2. Description of the Related Art In a field effect transistor using a Schottky gate, a recess structure has been employed in order to improve the breakdown voltage and reduce the source resistance Rs. Further, a two-stage recess structure has been employed to further improve the characteristics. FIG. 10 is a sectional view in the order of steps showing a method for manufacturing such a two-stage recessed field effect transistor proposed in Japanese Patent Application Laid-Open No. 3-108344. Hereinafter, the conventional manufacturing method described in the above publication will be described with reference to FIGS.

[0003] As shown in FIG.
A stopper layer 405 is deposited at a position corresponding to the depth of the second recess in the semiconductor active layer 402 formed on
After forming the drain electrode 403 and the source electrode 404 on the semiconductor active layer 402, the photoresist layer 4
06 is laminated. Next, as shown in FIG. 10B, openings for gate patterning are formed in the photoresist layer 406 by photolithography. Next, as shown in FIG. 10C, the active layer 402 immediately above the stopper layer 405 is etched by isotropic wet etching until reaching the stopper layer 405 to form a recess region 407.

Next, when the etching is further advanced in FIG. 10D, the semiconductor active layer 402 and the stopper layer 40 are formed.
Due to the etching selectivity with 5, the stopper layer 405 is hardly etched and the etching proceeds only in the lateral direction, so that the width of the recess region 407 is increased. Next, FIG.
As shown in (e), the stopper layer 405 is selectively etched away by anisotropic RIE using the photoresist layer 406 as a mask. Thereby, a two-stage recess is formed. Next, as shown in FIG. 10F, a gate electrode metal 408 is deposited on the entire surface by a vacuum evaporation method or the like. Next, unnecessary gate electrode metal on the photoresist layer 406 is removed by a lift-off method, and a gate electrode 408a is formed in the recess region 407. Then, as shown in FIG. Is completed.

[0005]

In a field-effect transistor having a recess, the gate electrode may be formed with an offset in order to improve the reverse breakdown voltage and reduce the source resistance Rs. Since the gate electrode is formed at the center of the recess (the first recess), the gate electrode cannot be offset. In the case where the length of the gate electrode is to be reduced for the purpose of improving the performance of the transistor, the deposition metal adheres to the side portion of the resist layer 406 during the deposition of the gate electrode metal, and the opening is gradually closed. In addition, the gate cross-sectional shape may be triangular, and the gate resistance may increase, leading to a reduction in transistor gain. Therefore, the problem to be solved by the present invention is, firstly, to be able to form a gate electrode at an offset position in a recess, and secondly, to be able to form a T-type gate electrode. That is.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a method of manufacturing a field-effect transistor according to the present invention comprises:
(1) A first resist material is applied on a semiconductor substrate on which a channel layer, an electron supply layer and / or an etching stopper layer, and a cap layer have been epitaxially grown in order from a lower layer to form a first resist film. Exposure to
Forming two first openings at a predetermined interval by performing development; and (2) etching the cap layer by using the first resist film as a mask to form a gap between the first and second openings. Forming a continuous recess in a region including the region; and (3) forming a second resist film by applying a second resist material, and a portion where the first resist film and the second resist film are in contact with each other. Forming a resist mixed layer comprising a mixture of both resist materials in the second step;
Exposing and developing the resist film to form a second opening having an opening width larger than the first opening and having an undercut shape on one of the first openings; (5)
Forming a gate electrode having a T-shaped cross section by depositing a gate electrode forming material and lift-off.

Another method for manufacturing a field-effect transistor according to the present invention comprises the following steps: (1) a channel layer,
An electron supply layer and / or a first etching stopper layer,
A first layer is formed on a semiconductor substrate on which a spacer layer, a second etching stopper layer, and a cap layer are epitaxially grown.
Forming a first resist film by applying the resist material of
Exposing and developing this to form two first openings at a predetermined interval; (2) etching the cap layer using the first resist film as a mask to form a first opening;
Forming a continuous first-stage recess in a region including a region between the second openings; and (3) removing the second etching stopper layer, and then applying a second resist material to form a second recess.
Forming a resist film, and forming a resist mixed layer composed of a mixture of both resist materials at a portion where the first resist film and the second resist film are in contact with each other; and (4) exposing the second resist film to light. Developing a second opening on one of the first openings, the second opening having an opening width larger than the first opening and having an undercut shape;
(5) a step of etching the spacer layer using the second resist film and the resist mixed layer as a mask to form a second recess, and (6) a cross-sectional shape of T due to deposition and lift-off of a gate electrode forming material. Forming a mold gate electrode.

[Operation] In the present invention, two openings are formed on the first resist film at a distance of at least half the width of the umbrella of the T-type gate, and one recess structure is formed by isotropic etching through the openings. Thereafter, a second resist film is applied and formed, and an opening having a width larger than this opening is formed on one of the openings by exposure and development to form a resist film having a T-type profile. Since the gate electrode is formed, a T-shaped gate electrode can be formed at an offset position in the recess.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1F are cross-sectional views in the order of steps for explaining the first embodiment of the present invention. First, on a semi-insulating semiconductor substrate 11, a buffer layer 12, an active layer 13 (corresponding to a channel layer + an electron supply layer in the case of HEMT), an etching stopper layer 14, and a cap layer 15 for making ohmic contact are epitaxially grown in order. Let it. Next, an inactive region is formed on the semiconductor substrate having the epitaxially grown layer by mesa formation, ion implantation, etc. to define an active region.
A pair of ohmic electrodes (not shown) serving as source / drain electrodes are formed. Next, a first resist material is applied on the epitaxial growth layer to form a first resist film 16.
To form The first resist film is exposed and developed to form two first openings 16a and 16b at an interval of at least the half width of the umbrella portion of the T-shaped gate to be formed [FIG. ]. That is, from the center of the first opening 16a on the gate electrode formation side to the first opening 16b on the buried side.
The following condition is imposed on the distance d to the end near the opening 16a. d ≧ (half-width of T-shaped gate head pattern)

Next, the cap layer 15 is formed by using the first resist film as a mask and the etching stopper layer 14 as a stopper.
Isotropically etched. At this time, over-etching is performed so as to form a recess 15a that is connected between the two openings and that also extends outside the first openings 16a and 16b (FIG. 1B). Next, the etching stopper layer 14
Is removed by a surface treatment using diluted hydrochloric acid or the like, and a second resist material is applied to the entire surface to form a second resist film 17.
To form At this time, a poorly soluble resist mixture layer 18 made of a mixture of both resist materials is formed at the interface between the first resist film 16 and the second resist film 17.
(C)]. Next, by performing exposure and development, the second resist film 17 on the first opening 16a on the gate electrode forming side has an undercut shape so that the opening width is larger than the first opening and lift-off is possible. Opening 17a having
To form At this time, since the resist mixed layer 18 remains as it is, the recess side portion is filled, and the first opening 16a is formed.
Is reduced in width. As a result, a T-shaped profile having a shape obtained by combining the reduced first opening and the second opening is finally formed (FIG. 1D). From the above,
In the present invention, the first opening 16a on the gate electrode formation side is formed.
The following constraints are imposed on the opening width of the recess and the depth of the recess 15a. (Width of first opening 16a) ≧ (lateral film thickness of resist mixed layer 18 × 2) (depth of recess 15a + thickness of etching stopper layer 14)
= (Cap layer thickness + etching stopper layer thickness) ≤ (film thickness of mixed layer 18 in vertical direction) Finally, a gate metal film 19 is deposited (FIG. 1 (e)) and lifted off to form a T-shaped cross section. The gate electrode 20 is formed (FIG. 1F).

In the above embodiment, the first resist film and the second resist film are formed under the following conditions: a resist mixed layer can be formed; the resist mixed layer can remain after the second opening is formed; Any combination that satisfies that it has etching resistance and that the second resist film can form an undercut opening can be used. As a material satisfying these conditions, for example, a resist for electron beam exposure is used as a resist material for forming a first resist film, and a positive photoresist is used as a resist material for forming a second resist film. Can be mentioned. When a positive photoresist is used as the second resist film, an image can be reversed by performing an image reverse process after performing a negative exposure. In the above embodiment, a spacer layer can be inserted between the cap layer and the first resist film in order to improve the adhesion of the first resist film. If the active layer 13 has an electron supply layer and this layer has a function as an etching stopper, the etching stopper layer 14 can be omitted. Further, the source / drain electrodes can be formed after the formation of the gate electrode.

FIGS. 2 (a) to 2 (c) are cross-sectional views in the order of main steps for explaining a second embodiment of the present invention. The steps up to the formation of the second opening 27a in the second resist film 27 are the same as in the case of the first embodiment shown in FIGS. 1A to 1D, and a description thereof will be omitted. I do. Also, in FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals with the same last digit. FIG.
As shown in (a), after forming the second opening 27a,
While monitoring the current value between the source and the drain, the active layer 2
3 is etched to a desired depth to form a second-stage recess at a position offset from the first-stage recess. Thereafter, a gate electrode forming material is deposited to form a gate metal film 29 (FIG. 2B), and lift-off is performed to form a gate electrode 30 having a T-shaped cross section (FIG. 2C).
According to the second embodiment, the two-step recess structure can alleviate the electric field and improve the thickness resistance.

FIGS. 3A to 3D are sectional views in the order of steps for explaining a third embodiment of the present invention. First,
Buffer layer 32 and active layer 3 on semi-insulating semiconductor substrate 31
3 (corresponding to the channel layer + electron supply layer in the case of HEMT), first etching stopper layer 34, spacer layer 3
5. The second etching stopper layer 36 and the cap layer 37 for making ohmic contact are sequentially epitaxially grown. Next, if necessary, define the active area,
After forming the ohmic electrode, a first resist material is applied on the epitaxial growth layer to form a first resist film 38 (FIG. 3A). Then, FIG.
By performing the same step as the step shown in (d), two first openings are formed in the first resist film, the cap layer is etched, and the second etching stopper layer is removed. A second opening 39a is formed in the resist film 39. Thereafter, the spacer layer 35 is etched using the second resist film 39 and the resist mixed layer 40 as a mask and the second etching stopper layer 34 as a stopper to form a second recess 35a in the first recess [FIG. 3
(B)]. Finally, the first etching stopper layer 34 is selectively removed by washing with water or the like, and a gate electrode forming material is deposited to form a gate metal film 41 (FIG. 3C). A mold gate electrode 42 is formed (FIG. 3D).

According to the third embodiment, since the bottom surface of the second recess is defined by the second etching stopper layer, the second recess can be formed at an accurate depth. , And the degree of freedom of the width of the second recess is increased. Also in this embodiment, when the active layer 33 has an electron supply layer and this layer has a function as an etching stopper, the first etching stopper layer 34 may be omitted. it can.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Will be explained. [First Embodiment] FIGS. 4 (a) to 4 (d) and FIGS. 5 (e) to 5 (e)
(H) shows the main steps in the first embodiment of the present invention.
FIG. 4 is a process order sectional view showing a state in which First, semi-insulating Ga
MBE (Molecular Beam Epitaxy;
I-GaAs buffer layer 102 by a molecular beam growth method.
(Thickness: 500 nm), i-Al_0.20Ga_0.80As buff
Layer 103 (200 nm thick), i-In_0.15Ga_0.85
As channel layer 104 (15 nm thick), n-Al_0.20
Ga_0.80As electron supply layer 105 (donor concentration 2 × 10 ¹⁸
cm^-3, Thickness 40 nm), i-Al_0.20Ga_0.80Ase
Switching stopper layer 106 (5 nm thick), n⁺ -Ga
As cap layer 107 (donor concentration 3 × 10¹⁸cm^-3,
(Thickness: 80 nm). This epitaxial
After forming a mesa on the substrate and performing element isolation, a pair of
Forming an electrode (not shown). Next, this web
C. Electron beam resist OEBR-100 manufactured by Tokyo Ohkasha
0 is spin-coated to form the first resist film 108
[FIG. 4 (a)]. Next, exposure with an electron beam and development
To form a recess between the source and drain electrodes
At an interval equal to or greater than the half width of the umbrella portion of the T-shaped gate,
Separated by at least 5 μm, the opening width of which is about 0.18 μm.
First openings 108a and 108b are formed [FIG.
(B)].

Next, an aqueous citric acid solution (citric acid: H ₂ O)
= 1: 1) and a 30% aqueous hydrogen peroxide solution in a ratio of 3: 1 using a GaAs / AlGaAs selective etchant, using the first resist film as a mask, and using i-Al _0.20 Ga
_{Using the 0.80} As etching stopper layer 106 as a stopper, the n ⁺ -GaAs cap layer 107 is selectively etched away. During this etching, the opening 108
When the cap layer immediately below a and 108b is removed, the etching proceeds in the lateral direction, forming a recess 107a that connects under both openings and extends in the left-right direction (FIG. 4C). Next, the etching stopper layer 106 is etched away by treatment with dilute hydrochloric acid and washing with water, and then a positive photoresist THMR-i manufactured by Sumitomo Chemical Co., Ltd.
P3300 is applied to the entire surface of the wafer, and the second resist film 1
09 is formed. At this time, a resist mixed layer 110 in which both resist materials are mixed is formed at the interface between the first resist film 108 and the second resist film 109 [FIG.
(D)]. Next, the first electrode on the gate electrode formation side is irradiated with ultraviolet light.
The T-type gate umbrella pattern is negatively exposed on the opening 108a (FIG. 5E). Next, baking at 108 ° C. is performed in an NH ₃ atmosphere as an image reverse process, and then,
The entire surface of the wafer is exposed to ultraviolet light and developed to remove unexposed portions of the second resist film 109 during negative exposure (see FIG. 5E). As a result, a second opening 109a having an undercut shape is formed on the first opening 108a so that the opening width is larger and lift-off is possible. At this time, since the resist mixed layer 109 is hardly soluble in the alkaline developer NMD-3 manufactured by Tokyo Ohka Co., it remains as it is. Since the thickness of the resist mixed layer 110 is about 80 nm in the vertical direction and about 30 nm in the horizontal direction, the side of the recess is filled, and the opening width of the first opening 108a is reduced to about 0.12 μm, so that the T-shaped profile is formed. Is formed [FIG. 5 (f)]. Next, the gate metal film 11
The Ti which becomes 1 is deposited by 15 nm and the Al by 300 nm by an electron gun vapor deposition apparatus (FIG. 5G), lifted off, and a T-shaped gate electrode 112 is formed at an offset position in the recess [FIG. (H)].

[Second Embodiment] FIGS. 6A to 6D and 7E to 7H are cross-sectional views showing the state of the main steps of a second embodiment of the present invention. is there. First, i-GaAs is formed on a semi-insulating GaAs substrate 201 by MBE.
Buffer layer 202 (500 nm thick), i-Al _0.20 G
a _0.80 As buffer layer 203 (200 nm thick), i-
In _0.15 Ga _{0. 85} As the channel layer 204 (thickness 15n
m), n-Al _0.20 Ga _0.80 As electron supply layer 205 (donor concentration 2 × 10 ¹⁸ cm ⁻³ , thickness 40 nm), i-Al
_0.20 Ga _{0. 80} As etching stopper layer 206 (thickness 5
nm), and an n ⁺ -GaAs cap layer 207 (donor concentration 3 × 10 ¹⁸ cm ⁻³ , thickness 80 nm) is sequentially grown.
After a mesa is formed on the epitaxial substrate to perform element isolation, a pair of ohmic electrodes (not shown) is formed. Next, an electron beam photosensitive resist OEBR-1000 manufactured by Tokyo Ohka Co., Ltd. is spin-coated on this wafer to form a first resist film 208 (FIG. 6A). Next, exposure with an electron beam and development are performed, and the opening width is set to a portion at which a recess between the source and drain electrodes is to be formed at an interval equal to or more than the half width of the umbrella portion of the T-type gate, for example, 0.5 μm or more. 0.18
Two first openings 208a and 208b of about μm are formed (FIG. 6B).

Next, an aqueous citric acid solution (citric acid: H ₂ O)
= 1: 1) and a 30% aqueous hydrogen peroxide solution in a ratio of 3: 1 using a GaAs / AlGaAs selective etchant, using the first resist film as a mask, and using i-Al _0.20 Ga
_The n ⁺ -GaAs cap layer 207 is selectively etched away using the _0.80 As etching stopper layer 206 as a stopper. At the time of this etching, the opening 208
After the cap layer immediately below the a and 208b is removed, the etching proceeds in the horizontal direction, and the first-stage recesses 207a connected under both openings and further expanded in the left and right horizontal directions.
Is formed [FIG. 6 (c)]. Next, the etching stopper layer 206 is selectively removed by treatment with dilute hydrochloric acid and washing with water, and then a positive photoresist THMR-iP3300 manufactured by Sumitomo Chemical Co., Ltd. is applied to the entire surface of the wafer to form a second resist film 209. . At this time, a resist mixed layer 210 in which both resist materials are mixed is formed at the interface between the first resist film 208 and the second resist film 209 [FIG. 6 (d)]. Next, a T-type gate umbrella pattern is negatively exposed to the first opening 208a on the gate electrode formation side with ultraviolet rays (FIG. 7E). Next, a bake at 108 ° C. is performed in an NH ₃ atmosphere as an image reverse process, and thereafter, the entire surface of the wafer is exposed to ultraviolet light and developed to perform a second process.
Of the resist film 209 at the time of negative exposure [FIG.
(See (e)). Thereby, the first opening 20
8a, the second opening 2 having an undercut shape so that the opening width is larger and lift-off is possible.
09a is formed. At this time, the resist mixed layer 210
Is hardly soluble in the alkaline developer NMD-3 manufactured by Tokyo Ohka Co., and therefore remains as it is. Resist mixed layer 2
The thickness of 10 is about 80 nm in the vertical direction and about 30 nm in the horizontal direction
To the extent that the recess side is filled and the first opening 20
The opening width of the opening 8a is also reduced to about 0.12 μm to form a T-shaped profile. Next, using a sulfuric acid-based etchant in which concentrated sulfuric acid, hydrogen peroxide solution and water were mixed at a ratio of 1: 8: 600, while monitoring the current value between the source and the drain, the n-Al _0.20 Ga _0.80 As electron supply layer was used. 205 is etched to a desired depth to form a second-stage recess 205a in the first-stage recess [FIG. 7 (f)]. Next, 15 nm of Ti and 300 nm of Al to be the gate metal film 211 are vapor-deposited by an electron gun vapor deposition apparatus (FIG. 7 (g)), and lift-off is performed to form an offset position in the first recess. A T-shaped gate electrode 212 is formed on the bottom surface of the formed second recess [FIG. 7 (h)].

[Third Embodiment] FIGS. 8A to 8E and FIGS. 9F to 9I are cross-sectional views showing the states of the main steps of a third embodiment of the present invention. is there. First, i-GaAs is formed on a semi-insulating GaAs substrate 301 by MBE.
Buffer layer 302 (thickness 500 nm), i-Al _0.20 G
a _0.80 As buffer layer 303 (200 nm thick), i-
In _0.15 Ga _{0. 85} As the channel layer 304 (thickness 15n
m), n-Al _0.20 Ga _0.80 As electron supply layer 305 (donor concentration 2 × 10 ¹⁸ cm ⁻³ , thickness 40 nm), i-Al
_0.20 Ga _{0. 80} As the first etching stopper layer 306 (thickness: 5nm), i-GaAs spacer layer 307 (thickness 20
nm), i-Al _0.20 Ga _0.80 As second etching stopper layer 308 (thickness 5 nm), n ⁺ -GaAs cap layer 309 (donor concentration 3 × 10 ¹⁸ cm ⁻³ , thickness 80 n)
m) is grown sequentially. After a mesa is formed on the epitaxial substrate to define an active region, a pair of ohmic electrodes (not shown) is formed. Next, an electron beam photosensitive resist OEBR-1000 manufactured by Tokyo Ohka Co., Ltd. is spin-coated on this wafer to form a first resist film 310 [FIG.
(A)]. Next, it is exposed by an electron beam, developed,
T is formed at the part where the recess between the source and drain electrodes is to be formed.
An interval equal to or greater than the half width of the umbrella of the mold gate, for example, 0.5 μm
Two first openings 310a and 310b having an opening width of about 0.18 μm are formed separated by the above [FIG. 8B].

Next, an aqueous citric acid solution (citric acid: H ₂ O)
= 1: 1) and a 30% aqueous hydrogen peroxide solution in a ratio of 3: 1 using a GaAs / AlGaAs selective etchant, using the first resist film as a mask, and using i-Al _0.20 Ga
_{Using the 0.80} As second etching stopper layer 308 as a stopper, the n ⁺ -GaAs cap layer 309 is selectively etched away. At the time of this etching, the opening 31
When the cap layer immediately below Oa and 310b is removed, the etching proceeds in the lateral direction, and a first-stage recess 309a connected under both openings is formed (FIG. 8C).
Next, the second etching stopper layer 308 is etched away by treatment with dilute hydrochloric acid and washing with water, and then a positive photoresist THMR-iP3300 manufactured by Sumitomo Chemical Co., Ltd.
Is applied to the entire surface of the wafer to form a second resist film 311. At this time, a resist mixed layer 312 in which both resist materials are mixed is formed at the interface between the first resist film 310 and the second resist film 311 [FIG. 8D]. next,
The T-type gate umbrella pattern is negatively exposed on the first opening 310a on the gate electrode forming side with ultraviolet rays [FIG.
(E)]. Next, a bake at 108 ° C. is performed in an NH ₃ atmosphere as an image reverse process, and thereafter, the entire surface of the wafer is exposed to ultraviolet light and developed to perform the second resist film 31.
The unexposed portions at the time of negative exposure 1 (see FIG. 8E) are removed. As a result, a second opening 311a having an undercut shape is formed on the first opening 310a so that the opening width is larger and lift-off is possible.
At this time, since the resist mixed layer 312 is hardly soluble in the alkaline developer NMD-3 manufactured by Tokyo Ohka Co., it remains as it is. Since the thickness of the resist mixed layer 312 is about 80 nm in the vertical direction and about 30 nm in the horizontal direction, the recess side is buried, and the opening width of the first opening 310a is also 0.1 mm.
A T-shaped profile is formed by reducing the size to about 2 μm (FIG. 9F). Next, using the resist pattern as a mask and the i-Al _0.20 Ga _0.80 As first etching stopper layer 306 as a stopper, the citric acid-based GaAs described above is used.
/ AlGaAs using selective etchant
The spacer layer 307 is etched to form the second recess 30.
7a is formed [FIG. 9 (g)]. Thereafter, the first etching stopper layer 306 is treated with dilute hydrochloric acid and washed with water.
Is selectively removed, and Ti serving as a gate metal film 313 is reduced to 1
5 nm and Al are vapor-deposited by a 300 nm electron gun vapor deposition apparatus [FIG. 9 (h)], and when lift-off is performed, a T-type is formed in a second-stage recess formed at an offset position in the first-stage recess. The gate electrode 314 of FIG.
(I)].

[0021]

As described above, in the method of manufacturing a field effect transistor according to the present invention, a first resist film having two first openings is formed, and a recess is formed so that a region between the two openings is connected. Is formed, a second resist film having a second opening wider than the first opening is formed on one of the first openings, and a resist mixed layer is formed at the interface between the two resist films. Since the gate electrode is formed by a lift-off method using the layer and the second resist film, according to the present invention, a gate electrode having a T-shaped cross section is formed at an offset position on the recess. be able to. Therefore, according to the present invention, it is possible to provide a high-performance field-effect transistor having a low source resistance and a low gate resistance and a high withstand voltage.

[Brief description of the drawings]

FIG. 1 is a process order sectional view for describing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view in a process order for describing a second embodiment of the present invention.

FIG. 3 is a sectional view illustrating a third embodiment of the present invention in a process order.

FIG. 4 is a part of a process order sectional view for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 5 is a step-by-step sectional view in a step following FIG. 4 for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 6 is a part of a process order sectional view for explaining the manufacturing method of the second embodiment of the present invention.

FIG. 7 is a step-by-step cross-sectional view for explaining the manufacturing method of the second embodiment of the present invention in a step following FIG. 6;

FIG. 8 is a part of a process order sectional view for explaining the manufacturing method of the second embodiment of the present invention.

FIG. 9 is a step-by-step cross-sectional view for explaining the manufacturing method of the third embodiment of the present invention in a step following FIG. 8;

FIG. 10 is a sectional view of a conventional example in the order of steps.

[Explanation of symbols]

11, 21, 31 Semi-insulating semiconductor substrate 12, 22, 32 Buffer layer 13, 23, 33 Active layer 14, 24 Etching stopper layer 15, 25, 37 Cap layer 15a Recess 16, 26, 38 First resist film 16a , 16b First opening 17, 27, 39 Second resist film 17a, 27a, 39a Second opening 18, 28, 40 Resist mixed layer 19, 29, 41 Gate metal film 20, 30, 42 Gate electrode 34 1 etching stopper layer 35 spacer layer 35a second recess 36 second etching stopper layer 101, 201, 301 semi-insulating GaAs substrate 102, 202, 302 i-GaAs buffer layer 103, 203, 303 i-Al _0.20 Ga _0.80 As buffer layer 104,204,304 i-In _0.15 Ga _0.85 As channel 105,205,305 n-Al _0.20 Ga _0.80 As electron supply layer 106,206 n-Al _0.20 Ga _0.80 As etching stopper layer 107,207,309 n ⁺ -GaAs cap layer 107a recess 108,208,310 first resist Membranes 108a, 108b, 208a, 208b, 310a,
310b First opening 109, 209, 311 Second resist film 109a, 209a Second opening 110, 210, 312 Resist mixed layer 111, 211, 313 Gate metal film 112, 212, 314 Gate electrode 205a, 307a Two steps First recesses 207a, 309a First recesses 306 i-Al _0.20 Ga _0.80 As first etching stopper layer 307 i-GaAs spacer layer 308 i-Al _0.20 Ga _0.80 As second etching stopper layer 401 Semiconductor substrate 402 Semiconductor active layer 403 Drain electrode 404 Source electrode 405 Stopper layer 406 Photoresist layer 407 Recess region 408 Gate electrode metal 408a Gate electrode

Claims (7)

[Claims] (1) A first resist film is formed by applying a first resist material onto a semiconductor substrate on which a channel layer, an electron supply layer and / or an etching stopper layer, and a cap layer have been epitaxially grown in order from the lower layer. Forming two first openings at predetermined intervals by exposing and developing the same, and (2) etching the cap layer using the first resist film as a mask to form a second opening. Forming a continuous recess in a region including a region between the first and second openings; (3) applying a second resist material to form a second resist film; A step of forming a resist mixed layer made of a mixture of both resist materials at a portion where the second resist film is in contact; and (4) exposing and developing the second resist film to one of the first openings. Forming a second opening having an opening width larger than the first opening and having an undercut shape thereon; and (5) forming a gate electrode having a T-shaped cross-section by depositing and lift-off of a gate electrode forming material. A method of manufacturing a field-effect transistor. 2. After the step (4), prior to the step (5), a part of the electron supply layer or the channel layer is formed using the second resist film and the resist mixed layer as a mask. 2. The method according to claim 1, further comprising a step of forming a second recess in the recess by etching. (1) A channel layer, an electron supply layer and / or a first etching stopper layer, a spacer layer, a second etching stopper layer, and a cap layer are sequentially formed on a semiconductor substrate on which epitaxial growth has been performed from a lower layer. Forming a first resist film by applying a resist material, and exposing and developing the first resist film to form two first openings at a predetermined interval; (2) the first resist film Forming a continuous first-stage recess in a region including a region between the first and second openings by etching the cap layer using the mask as a mask; and (3) applying a second resist material to form a second recess. Forming a resist film, and forming a resist mixed layer made of a mixture of both resist materials at a portion where the first resist film and the second resist film are in contact with each other; Exposing and developing the dying film to form a second opening having an opening width larger than the first opening and having an undercut shape on one of the first openings; (5) the second opening; Forming the second recess by etching the spacer layer using the resist film and the resist mixed layer as a mask, and (6) forming a gate electrode having a T-shaped cross section by depositing a gate electrode forming material and lift-off. A method of manufacturing a field-effect transistor. 4. The method according to claim 1, wherein after the step (5), prior to the step (6), the first step exposed at the second-stage recess portion.
4. The method according to claim 3, wherein a step of removing the etching stopper layer is added. 5. A step of removing the etching stopper layer or the second etching stopper layer exposed in the recess after the step (2) and prior to the step (3). 4. The method for manufacturing a field effect transistor according to claim 1, wherein: 6. The first resist film is formed of an electron beam exposure type resist, and the second resist film is formed of a positive type photoresist, and the exposure and development in the step (4) are performed by a negative pattern. 4. The method for manufacturing a field-effect transistor according to claim 1, further comprising each of exposure, image reverse processing, overall exposure, and development. 7. The field effect transistor according to claim 1, further comprising a step of forming a pair of ohmic electrodes on both sides of the gate electrode formation scheduled region before the step (1). Manufacturing method.