JPH10123218A - Method and device for testing logic integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the testing device for a logic integrated circuit, which can avoid the collision of data without adding any circuit, terminal and the like to a device to be measured (DUT). SOLUTION: When test data inputted into a DUT 2 and the output data outputted from the DUT 2 collide, the data collision is detected by a collision detecting part 15. The period, wherein the data collision is detected by the collision detecting part 15, is measured by a test control part 11. When the period, wherein the data collision occurs, is measured, the test control part 11 delays the output timing of a variable capability driver part 13, which outputs the test data to the DUT 2, by the above described measured period, and the data collision is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit (for example, a semiconductor integrated circuit) for inputting and outputting data through a bidirectional input / output buffer. The present invention relates to a test method and a test apparatus for a logic integrated circuit to be tested, and more particularly to a method for avoiding collision between output data of a driver unit of a test apparatus of a logic integrated circuit and output data of a logic integrated circuit which is a device under test. The present invention relates to a method and a device for testing a logic integrated circuit.

[0002]

2. Description of the Related Art In a logic integrated circuit in which some logic is formed in an integrated circuit such as a semiconductor integrated circuit, a function test is performed to check whether the logic integrated circuit has a logical function as designed.

As shown in FIG. 8, a test apparatus for performing the function test (a test apparatus for a logic integrated circuit)
51 is a device under test (hereinafter referred to as D
Test data is input to the DUT 57 and output data obtained by processing the test data by the DUT 57;
The logical function of the DUT 57 is tested by comparing it with expected value data. Note that the expected value data means that when the DUT 57 has a desired logical function,
It shows data that will be output in response to the test data.

The test apparatus 51 includes a test control unit 52
A test pattern storage unit 53 containing test data and expected value data corresponding to the test data, a timing generation unit 54, a comparator unit 55 for detecting output data of the DUT 57, and a test pattern input to the DUT 57. And a driver unit 56 that performs the operation.

When testing the DUT 57, the test data stored in the test pattern storage unit 53 is shaped by a clock from the timing generation unit 54,
It is given from the driver unit 56 to the DUT 57.

The output data processed and output by the DUT 57 is converted into a logical value by the comparator unit 55, and the logical value is calculated based on the expected value data stored in the test pattern storage unit 53 and the clock timing from the timing generation unit 54. A comparison determination is made.

However, when the measurement of the DUT 57 is performed by the above method, the input / output switching timing inside the DUT 57, the switching timing between the driver unit 56 and the comparator unit 55 in the test apparatus 51,
That is, since the input / output switching timing of the test device 51 does not always coincide with each other, a collision between the output of the DUT 57 and the driver output of the test device 51 (hereinafter, referred to as a data collision) may occur.

[0008] For example, as shown in FIG. 9 (c), the test apparatus 51 includes a comparator 55 at time t ₂
Switches from a state in which data is input from the DUT 57 to a state in which the driver unit 56 outputs data to the DUT 57. In contrast, as shown in FIG. 9 (b), DUT 57, until the timing of time t ₃ the comparator unit 5
5 to a state of outputting the data, the subsequent timing of time t _3, the first switched to a state of inputting the data from the driver unit 56.

Therefore, during the period when the input / output switching timing between the test apparatus 51 and the DUT 57 does not match, that is, between the time t ₂ and the time t ₃ , the test apparatus 51 and the DUT 57
The test data input to the DUT 57 and the output data from the DUT 57 collide, resulting in a waveform as shown in FIG.

Normally, the current supply capability of the driver unit 56 of the test apparatus 51 is sufficiently higher than that of the DUT 57.
The level of the driver unit 56 has priority. When such a collision occurs, an abnormal current flows to the test apparatus 51 and the DUT 57. As a result, in the DUT 57, there arise problems such as deterioration of the operation margin and inability to accurately measure the power supply current. Further, in the test device 51, the driver unit 56 may be deteriorated or destroyed.

As a method for avoiding the data collision,
As disclosed in Japanese Patent Application Laid-Open No. 59-90066, there is a method of extracting an input / output switching signal from the DUT 57 and controlling the input / output switching timing of the test apparatus 51 using the signal.

[0012]

However, in the method described in Japanese Patent Application Laid-Open No. 59-90066, the DUT 57
It is necessary to take out the input / output switching timing in advance from the DUT5.
7 must be newly provided. Therefore, in such a method, the function test cannot be performed on the conventional DUT 57 which does not have the output circuit and the output terminal for extracting the input / output switching timing, and the test apparatus of the logic integrated circuit is not provided. Problems such as low general versatility arise. In addition, the cost of the DUT 57 is increased.

The present invention has been made in order to solve the above problems, and has as its object to avoid data collision and add a logic integrated circuit without adding any circuit or terminal to the DUT 57. An object of the present invention is to provide a test method and a test apparatus for a logic integrated circuit that can perform a test.

[0014]

According to a first aspect of the present invention, there is provided a method for testing a logic integrated circuit (such as a semiconductor integrated circuit) to which data is input / output through a bidirectional input / output buffer. Providing test data to the logic integrated circuit, and comparing the output data output by the logic integrated circuit with respect to the test data and expected value data corresponding to the test data to perform a test of the logic integrated circuit In order to solve the above problem, before performing a test of the logic integrated circuit by comparing the output data and expected value data,
Detecting the collision between test data input to the logic integrated circuit and output data output by the logic integrated circuit, and correcting the test data output timing so that data collision does not occur if there is a collision. It is characterized by.

In the above test method, before the test of the logical function, the presence or absence of a collision between the test data input to the logic integrated circuit and the output data output by the logic integrated circuit is detected. The test data output timing is corrected so that no data collision occurs. Therefore, unlike the technique disclosed in Japanese Patent Application Laid-Open No. 59-90066, the input / output switching signal is not extracted from the logic integrated circuit.
Data collision at the time of the test can be avoided by taking measures on the test apparatus side.

As described above, by using the test method of the present invention, it is not necessary to change the configuration of the logic integrated circuit, such as adding a circuit or an output terminal. Therefore, the manufacturing cost of the logic integrated circuit does not increase, and the test apparatus can be made more versatile.

The data collision can be detected, for example, by detecting the voltage value of the terminal voltage of the logic integrated circuit at the time of the data collision.

According to a second aspect of the present invention, there is provided a test apparatus for a logic integrated circuit, wherein a test target device is a logic integrated circuit to which data is input / output through a bidirectional input / output buffer, and test data is supplied to the logic integrated circuit. A test of the logic integrated circuit is performed by comparing output data output from the logic integrated circuit with respect to the data and expected value data corresponding to the test data. Output means for outputting test data to the circuit; and data collision based on the terminal voltage of the logic integrated circuit when the test data input to the logic integrated circuit collides with the output data output by the logic integrated circuit. When a collision of data is detected by the collision detection means for detecting, and the collision detection means,
And timing correction means for correcting the output timing of the test data so that data collision does not occur.

According to the above arrangement, when the test data output from the output unit to the logic integrated circuit collides with the output data output from the logic integrated circuit, the collision detection unit detects the data collision. . The collision detecting means detects a data collision based on a voltage value of a terminal voltage of the logic integrated circuit at the time of a data collision. When the data collision is detected, the output timing of the test data is corrected by the timing correction means so that the data collision does not occur.

Thus, data collision can be avoided without extracting the input / output switching signal from the logic integrated circuit. Further, detection of data collision and correction of the output timing of test data can be performed by the test apparatus for a logic integrated circuit of the present invention. Therefore, it is not necessary to change the configuration of the logic integrated circuit, such as adding a circuit or an output terminal. For this reason, the manufacturing cost of the logic integrated circuit does not increase, and the test apparatus for the logic integrated circuit has high versatility.

According to a third aspect of the present invention, in addition to the configuration of the second aspect, the output means includes a variable-capacity driver, and the output means of the test data to be output to the logic integrated circuit is output. It is characterized in that it can be changed.

When data collision is detected based on the terminal voltage of the logic integrated circuit, a certain voltage range is set in advance based on the voltage value when the data collision occurs, and the voltage in this voltage range is detected. When this occurs, a data collision is detected. However, a constant voltage range cannot be set in advance because the voltage value when a data collision occurs is close to the power supply voltage, and the data collision may not be accurately detected.

On the other hand, according to the above configuration, the voltage of the test data output from the output unit can be changed by changing the driver capability of the variable capability driver of the output unit. Therefore, it is possible to adjust the value of the terminal voltage of the logic integrated circuit when data collision occurs by lowering or increasing it to such an extent that a certain voltage range can be set. This enables more reliable data collision detection.

In the case where the terminal voltage of the logic integrated circuit does not fall within the above-mentioned voltage range when a data collision occurs, the output capability of the output device is changed by changing the driver capability of the output device. If the data voltage is changed, the terminal voltage of the device under test at the time of data collision can be set to a value within the reference voltage range.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, a test apparatus (test apparatus for a logic integrated circuit) 1 according to the present embodiment has the following configuration for performing a function test of a DUT 2. The test apparatus 1 includes a test control unit 11, a test pattern storage unit 12 storing test data and expected value data corresponding to the test data, and a variable capacity for outputting the test input pattern to the DUT 2 as an output unit. It has a driver section 13, a comparator section 14 for detecting output data of the DUT 2, a collision detection section 15, and a timing generation section 16.

The collision detecting means for detecting the collision between the output of the DUT 2 and the output of the variable-capacity driver section 13 comprises a test control section 11 and a collision detection section 15, and outputs test data. The timing correction means for correcting the timing includes a test control unit 11 and a variable-capacity driver unit 13.

The test control unit 11 has a CPU (Centra
l Procssing Unit) and controls the operation of each of the above components. In addition, variable capacity driver unit 1
Numeral 3 is for outputting the test data output from the test pattern storage unit 12 to the DUT 2, and by changing the drive capability of the capability variable driver unit 13 itself, the output voltage of the test data can be changed. .

As shown in FIG. 2 or FIG. 3, the variable-capacity driver unit 13 forms the test data input from the test pattern storage unit 12 in a drive waveform shaping unit 13a using a clock generated by a timing generation unit 16 in a waveform. And D through the driver buffer 13b.
Output to UT2.

Here, the variable capacity driver 1 shown in FIG.
3 is provided with a drive current control unit 13c between the drive waveform shaping unit 13a and the driver buffer 13b, and the drive current control unit 13c changes the current supplied to the driver buffer 13b to change the capability. The voltage of the test data output from the driver unit 13 can be changed. The variable-capacity driver unit 13 shown in FIG. 3 includes a resistance control unit 13d at the subsequent stage of the driver buffer 13b, and outputs the variable-capacity driver unit 13d by changing the resistance value of the resistance control unit 13d. The test data voltage can be changed.
The drive current control unit 13c and the resistance control unit 13d
It is controlled by a control signal output from the test control unit 11. With these configurations, the variable capacity driver unit 13
The output test data can set the output voltage at the high level and the low level at each terminal arbitrarily.

As shown in FIG. 4, the collision detecting section 15
Comparator 15a · 1 for comparing UT terminal voltage
5b and an AND gate 15 for detecting the presence or absence of a collision
c. A voltage VrefH, which is a reference upper limit value for detecting a collision, is applied from the test control unit 11 to the positive terminal of the comparator 15a. Further, the DUT is connected to the negative terminal of the comparator 15a.
When the output voltage from the DUT 2 is applied and the output voltage from the DUT 2 is smaller than Vref H, the comparator 15a outputs a high-level signal.

Further, a voltage Vref L, which is a reference lower limit value for detecting a collision, is applied from the test control unit 11 to the minus terminal of the comparator 15b. Further, the DUT2 is connected to the positive terminal of the comparator 15b.
If the output voltage from the DUT 2 is higher than Vref L, the comparator 15b outputs a high-level signal.

When the high level signal is input from both the comparators 15a and 15b, that is, the output voltage from the DUT 2 becomes Vre.
When it is between fH and VrefL, a high level signal is output to the test control unit 11. In this way, if the test control section 11 measures the period during which the collision detection section 15 outputs a high-level signal, the collision occurrence period can be known. However, the terminal voltage of the DUT 2 may be a value within the reference voltage range even if no data collision occurs simply due to the failure of the DUT 2. However, usually, a static test (test for detecting leak and short circuit) of a terminal state is performed before performing this test, and such a case is considered to be almost eliminated by the static test. .

The comparator section 14 converts the data output from the DUT 2 into a logical value, and converts the data and the expected value data input from the test pattern storage section 12 into a clock signal input from the timing generation section 16. The comparison determination is performed at a timing.

Next, the operation of the test apparatus 1 according to the present embodiment will be described. Here, the test apparatus 1 includes a DUT 2
Before performing a function test for checking whether the DUT 2 has the designed logical function, the test apparatus 1
A preliminary test is performed to correct the output timing of the test data to be output to. The preliminary test includes the test data and the DU output from the test apparatus 1 to the DUT 2.
T2 is performed to avoid collision with output data output to the test apparatus 1, and a method thereof will be described below mainly with reference to the flowchart of FIG. Note that FIG.
The processing flow shown in the flowchart of FIG. 4 is for one test data stored in the test pattern storage unit 12, and the above processing flow is performed for all the test data input to the DUT 2.

First, the test data is stored in the test pattern storage unit 12 via the variable-capacity driver unit 13 by the DUT.
2 (S1). The DUT 2 logically converts the given test data and outputs it to the comparator 14 and the collision detector 15 (S2).

However, at this time, the variable capacity driver unit 13
The output voltage of the test data output by the DUT 2 is lowered to the same level as the output voltage of the DUT 2 by the variable-capacity driver unit 13 unlike when the function test is performed. Thus, the terminal voltage of the DUT 2 at the time of data collision becomes, for example, a value near VDD / 2.

This is because the output voltage of the variable-capacity driver unit 13 is lower than that of the DUT 2 as in the execution of the function test.
If the output voltage is too high as compared with the output voltage of DUT2, the terminal voltage of the DUT 2 at the time of data collision becomes a value close to the output voltage of the variable capacity driver unit 13, and it becomes difficult to detect the data collision.

[0039] At this time, the output of the test data of variable capacity driver section 13, as shown in FIG. 5 (c), the time t ₀
Is switched from the input mode to the output mode. Here, the DUT 2 must also switch from the output mode to the input mode at time t ₀ , but in fact, as shown in FIG. 5B, the state of the output mode continues until time t ₁ . . As a result, as shown in FIG. 5A, the output of the capability variable driver unit 13 and the output of the DUT 2 collide during the period from time t ₀ to t ₁ . The terminal voltage of the DUT 2 at the time of the collision differs depending on the terminal form and the like for each terminal. However, if the terminal voltage at the time of the collision is between the reference voltages VrefH and VrefL, it can be detected by the collision detection unit 15. Become. Usually, there are a plurality of the terminals, but the following operation is possible if data collision is detected in at least one of these terminals.

This collision is detected by the collision detection unit 15. As described above, the collision detection unit 15
5a and 15b and an AND gate 15c are provided. As shown in FIG. 6A, the collision detection unit 15 outputs a time t
Until _0, the low output state of the DUT 2, from time t ₀ to t _{1, the} terminal voltage is within the reference range due to collision, and from time t ₁ , the terminal voltage of the DUT 2 indicating the high output state of the variable capacity driver unit 13 Is entered. At this time, the comparator 15a which is a high side comparator collision detection section 15, as shown in FIG. 6 (b), becomes high output until time t _1, the comparator 15b as the low side comparator is in FIG. 6 (c) as shown, a high output from the time t _0. As a result, as shown in FIG.
The AND gate 15c operates from time t ₀ to t ₁ , that is,
The high output is output to the test control unit 11 only during the period in which the collision occurs.

As described above, when the test control unit 11 detects the high output from the collision detection unit 15,
A collision is detected (S3). If a collision is detected (S3
Then, the test control section 11 measures the period during which the high output is performed, and thereby determines the collision occurrence time (S4). The test control unit 11 controls the variable-capacity driver unit 13 for the collision occurrence time thus obtained.
Is shifted (S5) to avoid collision.

However, the terminal voltage of the DUT 2 at the time of collision is D
It is determined by the output voltage and current supply capability of the UT 2 and the drive voltage and current drive capability of the capability variable driver unit 13, and does not always fall within the reference range. Therefore, when the terminal voltage of the DUT 2 at the time of the collision does not become a value within the reference range, that is, when the test control unit 11 does not detect the collision (NO in S3), the drive current control unit 13c sets the capacity. It is determined whether the setting has been completed in the entire range (S6). If the capacity setting has not been performed in the entire range (NO in S6), as described above, the collision period voltages are VrefL and VrefH.
Of the variable-capacity driver unit 13 so as to be near the intermediate voltage of
Is controlled by the test controller 11 to change the driver output voltage (S7).

As described above, when a data collision occurs, the test apparatus 1 according to the present embodiment
Output a high signal only during the collision occurrence period. By measuring the output period of the high signal, the collision occurrence time is obtained. By shifting the output timing of the drive current control unit 13c by the collision occurrence time determined in this way, it is possible to avoid the occurrence of the subsequent collision.

Thus, the test apparatus 1 can perform all operations for avoiding data collision, such as detection of data collision and correction of the output timing of test data. Therefore, it is possible to avoid data collision without changing the configuration of the DUT 2 at all. As a result, the test apparatus 1 can be made highly versatile without increasing the manufacturing cost of the DUT 2.

In this embodiment, the output period of the high signal of the AND gate indicating the collision occurrence period, that is, t ₀ to
A method of avoiding a collision between the DUT output and the variable-capacity driver output by measuring the time t ₁ by the test control unit 11 and correcting the output timing of the test data by the variable-capacity driver unit 13 by that value at the same time. Although described, the capability variable driver unit 1 until the collision period disappears.
The collision can be avoided by sequentially changing the output timing of the test data according to (3). However, if the output timing of the test data is corrected collectively by the variable capability driver unit 13, the output timing of the test data can be corrected quickly.

[0046]

According to the logic circuit test method of the present invention, as described above, the output data is compared with the expected value data to test the logic integrated circuit before the logic integrated circuit is tested. In this configuration, the presence or absence of a collision between the test data and the output data output from the logic integrated circuit is detected, and if there is a collision, the output timing of the test data is corrected so that the data does not collide.

Therefore, when a collision occurs between the test data input to the logic integrated circuit and the output data output from the logic integrated circuit, a test of the logic integrated circuit for comparing the output data with the expected value data is performed. Before the test, the presence or absence of a data collision is detected, and the output timing of the test data is corrected to avoid the data collision. The detection of the data collision and the correction of the output timing of the test data for avoiding the data collision can all be performed by the test apparatus, so that it is not necessary to take out the input / output switching signal from the logic integrated circuit.

Therefore, it is not necessary to make a configuration change such as addition of a circuit or an output terminal to the logic integrated circuit, so that the manufacturing cost of the logic integrated circuit does not increase.
Further, there is an effect that the test apparatus can be made highly versatile.

According to a second aspect of the present invention, there is provided a logic circuit test apparatus comprising:
As described above, the output means for outputting test data to the logic integrated circuit, and the terminal voltage of the logic integrated circuit when the test data input to the logic integrated circuit collides with the output data output by the logic integrated circuit Collision detection means for detecting a data collision based on the data, and timing correction means for correcting the output timing of the test data so that the data collision does not occur when the collision detection means detects the data collision. Configuration.

Therefore, the detection of data collision and the correction of the output timing of the test data can all be performed by the logic integrated circuit test apparatus of the present invention. For this reason, data collision can be avoided without extracting the input / output switching signal from the logic integrated circuit.

Therefore, since it is not necessary to make a configuration change such as addition of a circuit or an output terminal to the logic integrated circuit, the manufacturing cost of the logic integrated circuit does not increase.
Further, there is an effect that the test apparatus for a logic integrated circuit of the present invention has high versatility.

According to a third aspect of the present invention, there is provided a logic circuit test apparatus comprising:
As described above, in addition to the configuration of claim 2, the output means includes a variable-capacity driver, and is capable of changing the output voltage value of the test data output to the logic integrated circuit.

Therefore, in addition to the effect of the configuration of claim 2, by changing the driver capability of the variable capability driver of the output means, the value of the terminal voltage of the logic integrated circuit when data collision occurs can be kept constant. Can be adjusted by lowering or raising it to such an extent that the voltage range can be set. As a result, there is an effect that it is possible to more reliably detect data collision.

Further, when the terminal voltage of the logic integrated circuit does not fall within the above-mentioned voltage range when a data collision occurs, the output capability of the output device is changed by changing the driver capability of the driver. If the data voltage is changed, the terminal voltage of the device under test at the time of data collision can be set to a value within the reference voltage range, and the data collision can be more reliably detected. Play.

[Brief description of the drawings]

FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a structure of a test apparatus for a logic integrated circuit.

FIG. 2 is a block diagram showing an example of the structure of a variable-capacity driver unit of the test apparatus for a logic integrated circuit.

FIG. 3 is a block diagram showing another example of the structure of the variable-capacity driver unit.

FIG. 4 is a circuit diagram showing a structure of a collision detection unit of the test apparatus for a logic integrated circuit.

FIG. 5 is a voltage waveform diagram showing a terminal voltage of the DUT, an output voltage of the DUT, and an output voltage of the variable-capacity driver unit.

FIG. 6 is an output waveform diagram illustrating a terminal voltage of a DUT input to a collision detection unit, a high-side comparator output, a low-side comparator output, and an AND gate output of the collision detection unit.

FIG. 7 is a flowchart showing a procedure of a test method for a logic integrated circuit according to the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional logic integrated circuit test apparatus.

FIG. 9 shows a terminal voltage of a conventional DUT, an output voltage of the DUT,
FIG. 4 is a voltage waveform diagram showing output voltages of a driver and a driver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test apparatus of logic integrated circuit 2 DUT 11 Test control unit 13 Variable capability driver unit 13c Drive current control unit 13d Resistance control unit 15 Collision detection unit

Claims (3)

[Claims] A logic integrated circuit to which data is input / output through a bidirectional input / output buffer is used as a device under test, test data is supplied to the logic integrated circuit, and the logic integrated circuit outputs the test data. In a logic integrated circuit test method for testing a logic integrated circuit by comparing output data with expected value data corresponding to the test data, a test of the logic integrated circuit is performed by comparing the output data with expected value data. Before performing the test, the presence / absence of a collision between the test data input to the logic integrated circuit and the output data output by the logic integrated circuit is detected. If there is a collision, the output timing of the test data is set so as not to cause the data collision. A method for testing a logic integrated circuit, wherein the method is modified. 2. A logic integrated circuit to which data is input / output through a bidirectional input / output buffer is defined as a device under test, test data is supplied to the logic integrated circuit, and the logic integrated circuit outputs the test data. A logic integrated circuit test device for comparing the output data with expected value data corresponding to the test data to test the logic integrated circuit, comprising: output means for outputting test data to the logic integrated circuit; Collision detection means for detecting data collision based on the terminal voltage of the logic integrated circuit when the test data input to the circuit and the output data output by the logic integrated circuit collide with each other; Timing correction means for correcting the output timing of the test data so as to prevent data collision when data is detected. Testing apparatus of logic integrated circuits. 3. The logic integrated circuit according to claim 2, wherein said output means includes a variable-capacity driver, and is capable of changing an output voltage value of test data output to the logic integrated circuit. Testing equipment.