JPH10117139A - Semiconductor logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the semiconductor logic circuit whose load charging (drive) capability is enhanced and circuit operating is quickened that realizes low power consumption by suppressing reduction in a current when the circuit is not in operation. SOLUTION: An n-type HEMT (T3) and an n-type HEMT (T2) are connected in series between a high level power supply VDD and a low level power supply (ground level GND), an output terminal OUT is placed to the connecting point of them, a p-type HEMT (T1) is connected between the high level power supply VDD and a gate of the n-type HEMT T3 and gates of the p-type HEMT T1 and the n-type HEMT T2 are connected in common to an input terminal IN. Thus, the circuit acts like an inverter that provides an output of an inverted level from the output terminal OUT with respect to an input level VIN applied to the input terminal IN.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit using a field effect transistor (FET), and more particularly, to improving both power consumption per chip and deterioration of circuit operation speed due to increase in integration scale. Semiconductor logic circuit.

[0002]

2. Description of the Related Art In recent years, with the rapid spread of computers and information communication devices, integrated circuits (ICs) mounted on them have been developed.
On the other hand, there is an increasing demand for a technology that achieves both a reduction in power consumption and an increase in operating speed. However, generally, an increase in the speed of the circuit operation causes an increase in power consumption, and it is difficult to establish a technique in which both are improved.

[0003]

For example, a semiconductor logic circuit capable of operating at high speed includes a heterojunction bipolar transistor HBT.
itor) and high electron mobility transistor HEMT (High Ele
A device using a compound semiconductor device such as a Ctron Mobility Transisitor is known. As a basic logic circuit using HEMT, DCFL (Direct Coupled FET Log)
ic) There is a circuit that can operate at high speed of about several tens of ps, but is configured using a depletion mode D-HEMT as a load transistor and an enhanced mode E-HEMT as a drive transistor. Is always in the on state, so that when the drive transistor is turned on, a current always flows from the high potential power supply (V _DD ) to the low potential power supply (V _SS , for example, the ground potential GND), and is about several mW / gate. There is a problem of consuming large power.

On the other hand, as a low power consumption semiconductor logic circuit, a complementary HEMT logic circuit (C-HEMT) is known. As shown in FIG. 7, the C-HEMT has a p-type H between a high-potential power supply (V _DD ) and a low-potential power supply (GND).
The EMT (T51) and the n-type HEMT (T52) are connected in series.
An input terminal IN is provided by commonly connecting the gates of the EMTs (T51, T52). In a C-HEMT logic circuit similar to the configuration of such a CMOS circuit, one of the HEMTs (T51, T52) is always turned on and the other is turned off in accordance with the input potential, so that the high potential power supply (V _DD ) Since the current flowing path from the power supply to the low-potential power supply (GND) is cut off, power consumption during operation can be extremely reduced, but there is a problem that the operation speed is as slow as several hundred ps. Such a problem is caused by the fact that the hole mobility of the p-type HEMT (T51) connected to the high potential power supply (V _DD ) side to supply current to the load is about 200 cm ² / Vs, (V _SS) for extremely low as about 1 / 10-1 / 20 compared to a connected n-type HEMT (T52) to the side, the transconductance g _m can not be obtained only about 50 ms / mm, required for charging the load This is because time is increased and high-speed operation at the time of turn-on is hindered. Therefore, p-type HEMT
In order to solve such a problem, it is necessary to increase the mutual conductance g _m expanding the gate width, enlargement of the gate width causes an increase of the input capacitance,
The charging time could not be improved.

[0005] The present invention solves the above-mentioned problems,
It is an object of the present invention to provide a semiconductor logic circuit in which the ability to charge (drive) a load is increased, the circuit operation is speeded up, the current flow when the circuit operation is stopped is suppressed, and the power consumption is reduced. .

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a drain electrode and a source electrode are connected between a high potential power supply and a low potential power supply, respectively. First and second n-type FETs connected to each other; a p-type FET having a source electrode and a drain electrode connected between the high potential power supply and a gate electrode of the first n-type FET; FET gate electrode and the second
And an output terminal provided at a connection point between the first and second n-type FETs.

According to a second aspect of the present invention, in the semiconductor logic circuit according to the first aspect, the first p-type FE is provided.
Between the drain electrode of T and a predetermined low potential power supply.
ET is connected. further,
The invention according to claim 3 is the semiconductor logic circuit according to claim 2, wherein the fourth FET is a p-type FET,
And the source electrode of the fourth FET is the first p-type F
The drain electrode of the ET and the drain electrode of the fourth FET are connected to the drain electrode of the second n-type FET.

According to a fourth aspect of the present invention, in the semiconductor logic circuit according to the second aspect, the fourth FET is provided.
Is an n-type FET, and the drain electrode of the fourth FET is connected to the drain electrode of the first p-type FET, and the source electrode of the fourth FET is connected to a low potential power supply;
Furthermore, a gate electrode of the fourth FET is connected to the input terminal.

According to a fifth aspect of the present invention, in the semiconductor logic circuit according to the first, second, third or fourth aspect, the plurality of p-type FETs in which the first p-type FETs are connected in parallel are provided.
A plurality of n-type FETs in which the second n-type FETs are connected in series, and the input terminal is formed by a plurality of individual terminal groups. Each individually forms a pair with each of the plurality of second n-type FETs, and the gate electrodes of the p-type FET and the n-type FET of each pair are individually connected to a terminal group of the input terminal. It is characterized by being.

According to a sixth aspect of the present invention, in the semiconductor logic circuit according to the first, second, third, or fourth aspect, a plurality of p-type FETs in which the first p-type FETs are connected in series are provided.
A plurality of n-type FETs in which the second n-type FETs are connected in parallel with each other, and the input terminal is constituted by a plurality of individual terminal groups. Each individually forms a pair with each of the plurality of second n-type FETs, and the gate electrodes of the p-type FET and the n-type FET of each pair are individually connected to a terminal group of the input terminal. It is characterized by being.

That is, a feature of the present invention is that a first n-type element for supplying a current to a load and a second n-type element for extracting a charge are connected in series between a high potential power supply and a low potential power supply, A p-type element for controlling the operation of the first n-type element is connected between the high-potential power supply and the first n-type element, and an input potential common to the second n-type element and the p-type element. And an output terminal for extracting an output potential from a connection point between the first and second n-type elements. The first and second n-type elements are provided in accordance with the input potential applied to the input terminal. Are inverted to take out the inverted potential of the input potential from the output terminal.

According to such a configuration of the present invention, a path through which a current flows during a stationary state is not formed by using a p-type element and an n-type element performing the same circuit operation as the conventional C-HEMT on the input side. In addition to reducing power consumption, the load driving capability is improved by using an n-type element having high electron mobility as an FET for supplying current to a load. Furthermore, the occupied area is suppressed without any restriction on the operating characteristics of the p-type HEMT element by controlling the n-type element that supplies current to the load with the p-type element on the input side.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic circuit configuration and operation of a semiconductor logic circuit according to the present invention will be described. FIG. 1 shows a basic circuit configuration of the semiconductor logic circuit according to claim 1;
The change of the operation level is shown in FIG. As shown in FIG. 1, an n-type HEMT (T3) and an n-type HEMT (T2) are connected in series between a high-potential power supply (V _DD ) and a low-potential power supply (ground potential GND). Is provided with an output terminal OUT. Also, a high potential power supply (V _DD ) and n-type HEMT
A p-type HEMT (T1) is connected between the gate of (T3). p-type HEMT (T1) and n-type HEM
The gate of T (T2) is commonly connected to the input terminal IN. Here, in order to simplify the explanation, the p-type HEMT is used.
As (T1), the gate width is 10 μm, and the threshold voltage is −0.
2V, and the n-type HEMTs (T2) and (T3) have a gate width of 20 μm and a threshold voltage of +0.2 V. The threshold voltage of a normal p-type HEMT (T1) is set in a range of about 0 to -0.5V, and the threshold voltage of an n-type HEMT (T2) and (T3) is set in a range of about 0 to + 0.5V. Is done.

Next, a logical operation in such a circuit configuration will be described. When the input potential V _IN is at the L level (〜0 V), the p-type HEMT (T1) is in the on state, and the n-type HEMT
Since (T2) is in the off state, the n-type HEMT (T3)
Of the high potential power supply (V _DD ), and the n-type HEMT (T3) is turned on. At this time, the output potential V _OUT becomes H level (1 V) as shown as point A in FIG. 2, and the n-type HEMT (T
Since 2) is in the off state, no current flows from the high potential power supply (V _DD ) to the low potential power supply (GND). Next, when the input potential V _IN rises, the n-type HEMT (T2) turns on and the p-type HEMT (T1) turns off. At this time, p-type H
The charge stored in the EMT (T1) is an n-type HEMT
Since the gate of (T3) passes through the source and the low potential power supply (GND) via the n-type HEMT (T2), the n-type HEM
The gate potential of T (T3) drops. As a result, n-type H
The EMT (T3) is turned off, and the output potential V _OUT is at the L level (≒ 0 V) as shown as a point B in FIG.

As described above, the basic circuit includes the input terminal IN
Has a function as an inverter that outputs an inverted potential from the output terminal OUT with respect to the input potential V _IN applied to. In particular, when the input potential V _IN is at the L level, the n-type HEMT (T2) is turned off, and the input potential V _IN
Is at the H level, the n-type HEMT (T3) is turned off, so that the high potential power supply (V _DD )
Flow path (V _DD −T) from the power supply to the low-potential power supply (GND)
3-T2-GND) is always shut off and CM
Like the OS inverter, it has a first feature that power consumption can be extremely reduced. In this basic circuit, the current is the current I _A flows down the flow-down path, input and output voltage V _IN, the transition period of the V _OUT as shown in FIG. 2, i.e. whether the current is supplied to the load, or the charge from the load Only when you are pulling out.

Further, the C-HEMT shown in the prior art has a structure in which a current is supplied to a load by using a transistor T51 which is a p-type element. Therefore, the gate width is increased in order to set a large driving capability. Although it is necessary to design, in this basic circuit, an n-type element is used as the transistor T3 for supplying a current to the load, and the transistor T1 of the p-type element may be used merely for setting the gate potential of the transistor T3. . Therefore, this basic circuit has the second feature that the load driving capability can be set large, and the gate width can be reduced because there is no need to set a large driving capability for the transistor T1.
Therefore, the third feature is that the input capacitance can be reduced and the circuit area can be reduced.

In this basic circuit, HEMTs are used as the transistors T1, T2 and T3. However, the present invention is not limited to HEMTs, and the present invention is not limited to HEMTs.
You may comprise using another semiconductor element, such as FET. Next, another basic circuit configuration of the semiconductor logic circuit according to the second, third and fourth aspects will be described with reference to FIGS. The description of the same configuration as that of the basic circuit in FIG. 1 is omitted.

In the basic circuit shown in FIG. 3, a drain of a p-type HEMT (T1) for setting a gate potential of an n-type HEMT (T3) for supplying a current to a load, and an n-type HEMT (T
A p-type HEMT (T4) having a source and a drain connected to a connection point with 2) and (T3), respectively, and a gate connected to a low potential power supply (GND) is provided. Explaining the logical operation in such a circuit configuration, when the input potential V _IN is at the L level, the p-type HEMT (T1) is on, the n-type HEMT (T2) is off, and the p-type HEMT (T4) is off. ) Is in the ON state, so that the n-type HE
The H level is applied to the gate of the MT (T3), the n-type HEMT (T3) is turned on, and the output potential V _OUT becomes the H level. Next, when the input potential V _IN rises,
The n-type HEMT (T2) turns on and the p-type HEMT (T1)
Is turned off, but at this time, the electric charge stored in the p-type HEMT (T1) is quickly discharged to the low potential power supply (GND) via the p-type HEMT (T4) and the n-type HEMT (T2) in the on state. Therefore, the gate potential of the n-type HEMT (T3) drops sharply, the n-type HEMT (T3) is turned off, and the output potential V _OUT becomes L level.

Further, in the basic circuit shown in FIG.
A source and a drain are connected to a drain of the EMT (T1) and a low-potential power supply (GND), respectively.
An n-type HEMT (T5) having a gate connected to N is provided. The logic operation in such a circuit configuration is such that when the input potential V _IN is at the L level, the p-type HEMT (T1) is in the on state, and the n-type HEMTs (T2) and (T5) are in the off state. H at the gate of (T3)
The level is applied, the n-type HEMT (T3) is turned on, and the output potential V _OUT goes to the H level. Next, when the input potential V _IN rises, the n-type HEMTs (T2) and (T5) are turned on and the p-type HEMT (T1) is turned off. At this time, the electric charge accumulated in the p-type HEMT (T1) is Since the power quickly goes to the low potential power supply (GND) via the n-type HEMT (T5), the gate potential of the n-type HEMT (T3) drops sharply, the n-type HEMT (T3) is turned off, and the output potential V _OUT becomes L level.

That is, in the basic circuit of FIG. 1, when the input potential V _IN rises from the L level, the p-type HEMT (T1)
Has been configured to escape from the gate of the n-type HEMT (T3) to the source as a gate leakage current. However, in the basic circuit of another embodiment shown in FIG. 3 and FIG. To reduce the time (turn-off) for lowering the gate potential of the HEMT (T3) to the L level, p
Providing a type HEMT (T4) or an n-type HEMT (T5) to set the gate potential of the n-type HEMT (T3)
It is characterized in that it has a configuration in which charges accumulated in the type HEMT (T1) are positively extracted. for that reason,
By using such a circuit configuration, it is possible to increase the speed of the circuit operation and improve the inverter gain.
According to these circuit configurations, the n-type HEMT (T
3) operates only by a change in the gate potential and does not require a gate current to flow, so that the same characteristics and circuit operation can be realized even with an insulated gate FET such as a MOSFET.

An embodiment applied to a logic circuit according to a semiconductor logic circuit according to claims 5 and 6 will be described below. FIG. 5 shows a first embodiment in which the above-described basic circuit is applied to a two-input NAND circuit. In FIG. 5, an n-type HE is connected between a high potential power supply (V _DD ) and a low potential power supply (GND).
MTs (T31), (T21) and (T22) are connected in series, and an output terminal OUT is provided at a connection point between the n-type HEMTs (T31) and (T21). Further, p-type HEMTs (T11) and (T12) are connected in parallel between the high potential power supply (V _DD ) and the gate of the n-type HEMT (T31). p-type HEMT (T11) and n-type H
The gate of the EMT (T22) is commonly connected to the input terminal IN1, and the p-type HEMT (T12) and the n-type HEMT
The gate of (T21) is commonly connected to the input terminal IN2.

The logic operation in such a circuit configuration will be described with reference to Table 1. Input terminals IN1 and IN2
, When the L level is applied to both, the p-type HEMT (T1
1) and (T12) are turned on, and the n-type HEMT
Since (T21) and (T22) are turned off, n
The gate of the p-type HEMT (T1) is connected to the p-type HEMT (T1).
H level is applied via 1) and (T12), and n level
The type HEMT (T31) is turned on, and the output terminal OU
H level is output to T. When the L level is applied to one of the input terminals IN1 and IN2 and the H level is applied to the other, one of the p-type HEMTs (T11) and (T12) is turned on, and the n-type HEMTs (T21) and (T22) are turned on. ) Is turned off, so that n-type H
P-type HEMT (T11) for the gate of EMT (T31)
And (T12), the H level is applied, the n-type HEMT (T31) is turned on, and the H level is output to the output terminal OUT. Further, when an L level is applied to both the input terminals IN1 and IN2,
Since the p-type HEMTs (T11) and (T12) are turned off and the n-type HEMTs (T21) and (T22) are turned on, the p-type HEMTs (T11) and (T1) are turned on.
The charge stored in 2) flows to the low-potential power supply (GND) as a gate leak current via the n-type HEMT (T31), and the gate potential of the n-type HEMT (T31) drops, and the n-type HEMT (T31) ) Is turned off, and an L level is output to the output terminal OUT.

That is, when one or both of the two inputs are at the L level, at least one of T11 and T12 is turned on to turn on T31 and at least one of T21 and T22 is turned off. Therefore, the output terminal OUT is set to H through T31.
The level (V _DD ) is applied. Also, both inputs are H
In the case of the level, T11 and T12 are turned off, the application of the voltage to the gate electrode of T31 is stopped, and both T21 and T22 are turned on.
An L level (GND) is applied to the UT.

[0024]

[Table 1]

FIG. 6 shows the basic circuit described above in which a two-input NOR
This is a second embodiment applied to a circuit. In FIG. 6, n is connected between a high potential power supply (V _DD ) and a low potential power supply (GND).
The HEMTs (T32) and (T24) are connected in series, and an output terminal OUT is provided at the connection point. Here, an n-type HEMT is provided between the connection point of the n-type HEMTs (T32) and (T24) and the low potential power supply (GND).
An n-type HEMT (T23) is connected in parallel with (T24). In addition, a high potential power supply (V _DD ) and an n-type HEMT (T
P-type HEMTs (T13) and (T14) are connected in series with the gate of (32). p-type HEMT
(T13) and the gate of the n-type HEMT (T24) are commonly connected to the input terminal IN1, and the p-type HEMT (T1)
4) and the gate of the n-type HEMT (T23) are commonly connected to the input terminal IN2.

The logic operation in such a circuit configuration will be described with reference to Table 2. Input terminals IN1 and IN2
, When the L level is applied to both, the p-type HEMT (T1
3) and (T14) are turned on, and the n-type HEMT
Since (T23) and (T24) are turned off, n
The gate of the type HEMT (T32) has a p-type HEMT (T1
H level is applied through 3) and (T14), and n level
The type HEMT (T32) is turned on, and the output terminal OU
H level is output to T. When an L level is applied to one of the input terminals IN1 and IN2 and an H level is applied to the other, one of the p-type HEMTs (T13) and (T14) is turned off, and the n-type HEMTs (T23) and (T24) are turned off. ) Is turned on, the n-type H
The gate potential of the EMT (T32) drops and the n-type HEM
T (T32) is turned off, and L is output to the output terminal OUT.
The level is output. Further, input terminals IN1 and I
When the L level is applied to both N2, the p-type HEMT
(T13) and (T14) are turned off, and n-type H
Since the EMTs (T23) and (T24) are turned on, the charges accumulated in the p-type HEMTs (T13) and (T14) are converted into a low potential power supply (GND) as a gate leak current via the n-type HEMT (T32). ), N-type H
The gate potential of the EMT (T32) drops and the n-type HEM
T (T32) is turned off, and L is output to the output terminal OUT.
The level is output.

That is, when both inputs are at the L level, T13 and T14 are turned on to turn on T32, and both T23 and T24 are turned off. Therefore, the output terminal OUT is connected to the output terminal OUT via T32. H level (V _DD ) is applied. When one or both of the two inputs are at the H level, T13 and T1
4 is turned off and T32
Stops applying voltage to the gate electrode of T23 and T23 and T
Since at least one of the switches 24 is turned on, an L level (GND) is applied to the output terminal OUT.

[0028]

[Table 2]

According to the logic circuits shown in the first and second embodiments, p controls the operation of supplying a current to a load.
N for performing a type of transistor group and charge extracting operation
The transistors of the type transistor group are configured so as to form a pair, and a common input terminal is provided for each pair to form a multi-input circuit configuration. NAND and NOR logic outputs can be obtained by inverting the n-type transistor performing the current supply operation and the n-type transistor performing the charge extracting operation. In particular, when these logic circuits are at rest, an n-type transistor for supplying a current to a load or an n-type transistor for extracting a charge according to the input potential.
Type transistor is turned off,
The current flow path from the high-potential power supply (V _DD ) to the low-potential power supply (GND) is always shut off, and power consumption can be reduced. Further, since an n-type element is used as a transistor for supplying a current to the load, the operation speed can be increased and the load driving capability can be set large. In addition, only by setting the gate potential with a p-type transistor, this n-type element can be used. Since the operation of the p-type transistor can be controlled, the driving characteristics of the p-type transistor are not restricted at all (that is, there is no need to set a large driving capability), and the gate width is reduced to suppress an increase in the circuit area. can do. Furthermore, the semiconductor logic circuit of the present invention
Since it can be configured by the same design method as that of the CMOS, it can be suitably applied to various logic circuits other than the above-described NAND and NOR circuits without adding or changing the method.

In the above embodiment, an example of application to a digital logic circuit has been described. However, if the semiconductor logic circuit of the present invention is operated with a small signal by utilizing the small signal characteristics of the HEMT,
Needless to say, the circuit can be operated as an analog circuit such as an analog amplifier.

[0031]

As described above, according to the semiconductor logic circuit of the present invention, the p-type element and the n-type element which perform the same circuit operation as the C-HEMT are used in the input stage.
Since the path through which current flows when stationary can be cut off, power consumption can be reduced, and the operating speed can be increased by using an n-type element having high electron mobility as the FET that supplies current to the load. In addition, the load driving capability can be improved. Further, by controlling the n-type element for supplying current to the load with the p-type element on the input side, there is no restriction on the operating characteristics of the p-type HEMT element, so that the gate width can be set small and the circuit area can be reduced. Increase can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic circuit configuration (No. 1) of a semiconductor logic circuit according to the present invention.

FIG. 2 is a diagram showing operation levels of a basic circuit configuration (part 1) of a semiconductor logic circuit according to the present invention.

FIG. 3 is a diagram showing a basic circuit configuration (part 2) of the semiconductor logic circuit according to the present invention.

FIG. 4 is a diagram showing a basic circuit configuration (3) of a semiconductor logic circuit according to the present invention.

FIG. 5 is a diagram showing a first embodiment in which the semiconductor logic circuit according to the present invention is applied to a logic circuit (two-input NAND circuit).

FIG. 6 is a diagram showing a second embodiment in which the semiconductor logic circuit according to the present invention is applied to a logic circuit (2-input NOR circuit).

FIG. 7 is a diagram showing a circuit configuration of a conventional complementary HEMT.

[Explanation of symbols]

T1, T4, T11 to T14, T51
p-type HEMT T2, T3, T21 to T24, T31, T32, T52
n-type HEMT IN, IN1, IN2 Input terminal OUT Output terminal V _DD High-potential power supply V _SS (GND) Low-potential power supply

Claims (6)

[Claims] A first and second n-type FETs connected in series with a drain electrode and a source electrode respectively connected between a high-potential power supply and a low-potential power supply; A p-type FET having a source electrode and a drain electrode respectively connected between the gate electrode of the n-type FET and
Having an input terminal commonly connected to the gate electrode of the n-type FET and the gate electrode of the second n-type FET, and an output terminal provided at a connection point between the first and second n-type FETs A semiconductor logic circuit characterized by the above-mentioned. 2. The semiconductor logic circuit according to claim 1, wherein a fourth FET is connected between a drain electrode of said first p-type FET and a predetermined low potential power supply. Semiconductor logic circuit. 3. The semiconductor logic circuit according to claim 2, wherein said fourth FET is a p-type FET, and a source electrode of said fourth FET is connected to a drain electrode of said first p-type FET. A semiconductor logic circuit, wherein a drain electrode of the fourth FET is connected to a drain electrode of the second n-type FET. 4. The semiconductor logic circuit according to claim 2, wherein said fourth FET is an n-type FET, and a drain electrode of said fourth FET is connected to a drain electrode of said first p-type FET. A semiconductor logic circuit, wherein a source electrode of the fourth FET is connected to a low potential power supply, and a gate electrode of the fourth FET is connected to the input terminal. 5. The semiconductor logic circuit according to claim 1, wherein the second n-type FET is formed by a plurality of p-type FETs connected in parallel with the first p-type FET.
ET is constituted by a plurality of n-type FETs connected in series, the input terminal is constituted by a plurality of individual terminal groups, and each of the plurality of first p-type FETs is connected to the plurality of second n-type FETs. Wherein each of the paired FETs is individually formed with a pair, and the gate electrodes of the p-type FET and the n-type FET for each pair are individually connected to a terminal group of the input terminals. circuit. 6. The semiconductor logic circuit according to claim 1, wherein said second n-type FET is formed by a plurality of p-type FETs connected in series with said first p-type FET.
ET is constituted by a plurality of n-type FETs connected in parallel, the input terminal is constituted by a plurality of individual terminal groups, and each of the plurality of first p-type FETs is connected to the plurality of second n-type FETs. Wherein each of the paired FETs is individually formed with a pair, and the gate electrodes of the p-type FET and the n-type FET for each pair are individually connected to a terminal group of the input terminals. circuit.