JPH10116475A - Optical disk recording method, and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical disk recording method which additionally records clock stabilizing information at a discontinuously recording position on the signal track of the optical disk, on which auxiliary signals of a soft- sector system are preformatted. SOLUTION: An auxiliary signal which segments a signal track into unit blocks is preformatted in a region different from the signal track on an optical disk 24, and clock stabilizing information is recorded on a part of the unit block neighboring the discontinuously recording position of the signal track of the optical disk 24. User information is recorded on the remaining part of the unit block next to the discontinuously recording position and thereby, it is stabilized and reproduced. In addition, the recording capacity of the optical disk is enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for recording information on an optical disk in which an auxiliary signal indicating a physical position of a signal track is preformatted in an area different from the signal track, and in particular, to a discontinuity on the signal track. The present invention relates to an optical disk recording method and apparatus for recording information at a recording position.

[0002]

2. Description of the Related Art Conventional compact discs (hereinafter referred to as CDs) and digital versatile discs (Digital Ve
On an optical disc such as an rsatile disc (hereinafter referred to as "DVD"), signal tracks for recording information are formed in a spiral or concentric form. Also, an auxiliary signal has been preformatted on the optical disk so that signal tracks can be randomly accessed. The auxiliary signal divides the signal track into unit storage areas of a fixed size and indicates the physical positions of these unit storage areas.

Auxiliary signals are preformatted on an optical disk in two systems, a hard sector system and a soft sector system. According to the former hard sector method, embossed pits (E
By forming a mbossed Pit, the auxiliary signal is preformatted on the optical disc. Thus, the optical disk (10) in which the auxiliary signal is preformatted
In FIG. 1, a concentric or spiral signal track (12) is divided into sectors (14) of a fixed length as shown in FIG. Each of these sectors (14) has a sector identification signal (16)
And a main information signal section (18). The sector identification signal section 16 includes a synchronization pattern, an address mark, a track number, and a sector number, and is used as an auxiliary signal for indicating a boundary portion between adjacent sectors and for indicating a physical position of the sector. User information is recorded in the main information signal section (18). Such a hard sector type auxiliary signal occupies a part of a signal track on which user information is recorded, thereby reducing the recording capacity of the optical disk.

[0004] The latter soft sector type auxiliary signal is
The recording area of the optical disk can be enlarged by arranging it in another area, the wobble area, other than the signal track of the optical disk. An optical disk in which auxiliary signals are preformatted in this soft sector system has a structure shown in FIG.
As shown in (1), grooves (22) formed in a spiral or concentric form from the center to the outer periphery of the optical disk (hereinafter referred to as groove tracks) are bent at a constant cycle, and between the grooves (22). Are arranged with lands (20) (hereinafter referred to as mountain tracks). Aux signals on the groove track
(22) Bent portions on both sides (hereinafter referred to as “wobble area”
The auxiliary signal is preformatted.

[0005] The user information block recorded on the signal track of the optical disk in which the soft sector auxiliary signal is preformatted includes a user block identification section and a user block information section. The user block identification unit includes a synchronization pattern, an address mark, a track number, a block number, and the like, like the auxiliary signal of the hard sector system. The user block identification unit configured as above indicates the physical position of the signal track of the optical disc during reproduction. Therefore, the auxiliary signal of the soft sector system is mainly used when recording user information on an optical disk.

The auxiliary signal is a transmission speed of user information,
That is, the optical disk is pre-formatted in a form synchronized with a clock signal of a certain cycle to indicate a recording speed and a reproduction speed. In other words, the auxiliary signal preformatted on the optical disc includes a clock signal of a certain cycle. The clock signal included in the user block identification unit and the clock signal included in the hard sector type sector identification signal unit have the same cycle as the user information bit, whereas the clock signal included in the soft sector type auxiliary signal is the user information bit. Has a relatively large cycle. That is, the reference clock signal included in the soft sector type auxiliary signal has a lower frequency than the bits of the user information. by this,
In an optical disk in which a soft sector type auxiliary signal is preformatted, the phase of a clock signal recorded on a signal track can change rapidly. When the phase of the clock signal suddenly changes in this way, the optical disk reproducing apparatus reproduces a clock signal having a cycle different from the bits of the user information, so that among the user information blocks and the like recorded on the signal track, Some user information blocks will not play correctly. Such a phenomenon occurs from a recording position on a signal track of an optical disk on which user information is recorded discontinuously in time (hereinafter, referred to as a “discontinuous recording position”), and also occurs on a signal track of the optical disk. As the number of information files to be recorded increases, it occurs more constantly. That is, the discontinuous recording position is determined when the second information file is recorded from an arbitrary position after an arbitrary time after the first information file is recorded over an arbitrary intermediate position from the start position of the signal track. Occurs when new information is overwritten at an arbitrary position on a recorded signal track.

As shown in FIG. 3, first user information is recorded in a section (S1) from a left side of a signal track (20 or 22) of an optical disk to an arbitrary point (DCP), and the next arbitrary period elapses. Thereafter, if the second user information is recorded rightward from an arbitrary point (DCP, ie, a discontinuous recording position), the phase of the recording clock recorded on the signal track (20 or 22) is as shown in FIG. 4A. At the discontinuous recording position (DC
P) suddenly changes. This is because the recording clock recorded on the signal track (20 or 22) of the optical disk is generated based on the reference clock signal included in the soft sector type auxiliary signal. This recording clock has a large cycle during a period corresponding to a certain section from the discontinuous recording position (DCP) as shown in FIG. 4B by the optical disc reproducing apparatus, or corresponds to a certain section from the discontinuous recording position (DCP) as shown in FIG. 4C. It is regenerated to have a small cycle during the period. As described above, since the recording clock signal recorded in a certain section from the discontinuous recording position (DCP) on the signal track (20 or 22) is reproduced so as to have a large or small cycle, the user information recorded in that section is reproduced. Will not play correctly.

In order to prevent such an error of the user information at the discontinuous recording position on the signal track of the optical disk, a "variable frequency oscillation (Variable F
requency oscilating (hereinafter referred to as "VFO") signal "
A method of adding clock stabilization information has been proposed. Since this clock stabilization information is usually recorded over one sector section from the discontinuous recording position, the signal track of the optical disk is unnecessarily consumed. Accordingly, the method of adding the clock stabilization information has a disadvantage that the recording capacity of the optical disk is significantly reduced as the number of discontinuous recording positions on the signal track of the optical disk increases.

[0009]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for stably reproducing user information and at a discontinuous recording position on a signal track of an optical disk so as to increase the recording capacity of the optical disk. An object of the present invention is to provide an optical disk recording method and apparatus capable of recording user information.

[0010]

In order to achieve the above object, an optical disk recording method according to the present invention is directed to an optical disk recording method in which an auxiliary signal for dividing a signal track into unit blocks is preformatted in an area different from the signal track. The method includes the steps of recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position of a signal track, and recording user information in the remaining part of the unit block.

[0011] Another optical disk recording method according to the present invention comprises:
An auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for instructing a transmission rate of information is transmitted from an optical disk preformatted in another area different from the signal track. A first step of detecting, a second step of recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using an auxiliary synchronization signal and an auxiliary clock, and an auxiliary synchronization signal and an auxiliary clock. And a third step of recording user information in a remaining portion of the unit block adjacent to the discontinuous recording position using a clock.

According to still another optical disk recording method of the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a data transmission speed is provided in another area different from the signal track. A first step of detecting an auxiliary synchronization signal and an auxiliary clock from the preformatted optical disk, a second step of generating a reference clock based on the detected auxiliary clock, and using the detected auxiliary synchronization signal and the reference clock. A third step of recording clock stabilization information in a part of a unit block adjacent to the discontinuous recording position on the signal track, and a step of recording the unit block adjacent to the discontinuous recording position using the clock stabilization information and the reference clock. And a fourth step of recording user information in the remaining part.

According to still another optical disc recording method of the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a data transmission speed is pre-recorded in another area different from the signal track. A first step of detecting an auxiliary clock from a formatted optical disk, a second step of generating a reference clock based on the detected auxiliary clock, a third step of reproducing a synchronization signal recorded on a signal track, and a reproduction step. A fourth step of recording the clock stabilization information in a part of the unit block adjacent to the discontinuous recording position on the signal track using the obtained synchronization signal and the reference clock, and using the clock stabilization information and the reference clock. A fifth step of recording user information in the remaining part of the unit block adjacent to the discontinuous recording position is included.

According to still another optical disc recording method of the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is stored in another area different from the signal track. A first step of detecting an auxiliary synchronization signal and an auxiliary clock from the preformatted optical disk, a second step of generating a reference clock based on the detected auxiliary clock, and a step of reproducing a synchronization signal recorded on a signal track. Three steps, a fourth step of recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using a reproduced synchronization signal, an auxiliary synchronization signal, and a reference clock; User information is recorded in the remaining part of the unit block adjacent to the discontinuous recording position using the segmentation information and the reference clock That a fifth stage.

According to still another optical disc recording method of the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a transmission speed of information is stored in another area different from the signal track. A first step of detecting an auxiliary synchronization signal and an auxiliary clock from a preformatted optical disk, a second step of generating a reference clock based on the detected auxiliary clock, and a step of reproducing a synchronization signal recorded on a signal track. Three steps, a fourth step of recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using a reproduced synchronization signal, an auxiliary synchronization signal, and a reference clock; The fifth step of generating a pseudo-synchronization signal based on the conversion information, The rest of the contact unit blocks including a fifth step of recording the user information.

In another optical disc recording method according to the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a data transmission speed is stored in another area different from the signal track. A first stage for detecting an auxiliary synchronization signal and an auxiliary clock from the preformatted optical disk, a second stage for generating a reference clock based on the detected auxiliary clock, and a reference synchronization signal based on the detected auxiliary synchronization signal Third to generate
And a fourth step of reproducing the synchronization signal recorded on the signal track, and a part of the unit block adjacent to the discontinuous recording position on the signal track using the reproduced synchronization signal, the auxiliary synchronization signal, and the reference clock. And a sixth step of generating a pseudo-synchronization signal based on the clock stabilization information, and a remaining unit block adjacent to the discontinuous recording position using the pseudo-synchronization signal and the reference clock. The seventh step of recording user information in the part of
An eighth step of recording user information in at least one subsequent unit block connected to the unit block adjacent to the discontinuous recording position using the reference synchronization signal and the reference clock is included.

In an optical disk recording apparatus according to the present invention, an auxiliary signal for dividing a signal track into unit blocks has a unit block adjacent to a discontinuous recording position on a signal track of an optical disk preformatted in an area different from the signal track. A first recording unit for recording clock stabilization information in a part and a second recording unit for recording user information in the remaining part of the unit block are provided.

Another optical disk recording apparatus according to the present invention comprises:
An auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for instructing a transmission rate of information is transmitted from an optical disk preformatted in another area different from the signal track. First recording for recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using an auxiliary signal detecting means for detecting and an auxiliary synchronizing signal and an auxiliary clock from the auxiliary signal detecting means. Means and second recording means for recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position using the auxiliary synchronization signal and the auxiliary clock from the auxiliary signal detecting means.

In still another optical disc recording apparatus according to the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is stored in another area different from the signal track. Auxiliary signal detection means for detecting an auxiliary synchronization signal and an auxiliary clock from a preformatted optical disk; reference clock generation means for generating a reference clock based on the auxiliary clock from the auxiliary signal detection means; A first recording unit that records clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using a synchronization signal and a reference clock from a reference clock generation unit; Discontinuous recording position using the clock stabilization information of A second recording means for recording the user information to the rest of the adjacent unit blocks.

According to still another optical disc recording apparatus of the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a transmission speed of information is provided in another area different from the signal track. Auxiliary signal detecting means for detecting an auxiliary clock from a preformatted optical disk; reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means; and reproducing a synchronization signal recorded on a signal track. A reproducing unit for recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using a reproduced synchronization signal from the reproducing unit and a reference clock from a reference clock generating unit; 1 recording means, clock stabilization information from the first recording means, and The rest of the unit block adjacent to the discontinuous recording position using the reference clock comprises a second recording means for recording the user information.

According to still another optical disc recording apparatus of the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is provided in another area different from the signal track. Auxiliary signal detection means for detecting an auxiliary synchronization signal and an auxiliary clock from a preformatted optical disk; reference clock generation means for generating a reference clock based on the auxiliary clock from the auxiliary signal detection means; A reproducing means for reproducing a signal; a reproduced synchronizing signal from the reproducing means; an auxiliary signal from the auxiliary signal detecting means; and a reference clock from the reference clock generating means, which is adjacent to the discontinuous recording position on the signal track. First recording means for recording clock stabilization information in a part of the unit block;
Second recording means is provided for recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position using the clock stabilizing information from the first recording means and the reference clock from the reference clock generating means.

In still another optical disc recording apparatus according to the present invention, an auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for instructing a data transmission speed is provided in another area different from the signal track. Auxiliary signal detection means for detecting an auxiliary synchronization signal and an auxiliary clock from a preformatted optical disk; reference clock generation means for generating a reference clock based on the auxiliary clock from the auxiliary signal detection means; A reproduction means for reproducing a signal; an auxiliary synchronization signal from the auxiliary signal detection means; a reproduced synchronization signal from the reproduction means; and a reference clock from the reference clock generation means, which are adjacent to the discontinuous recording position on the signal track. Recording means for recording clock stabilization information in a part of the unit block, and a first recording means A pseudo-synchronization signal generating means for generating a pseudo-synchronization signal based on the clock stabilization information, and a unit block adjacent to the discontinuous recording position using the pseudo-synchronization signal from the pseudo-synchronization signal and the reference clock from the reference clock generation means. And a second recording means for recording user information in the remaining part of.

In the optical disk recording apparatus according to the present invention, an auxiliary signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating the information transmission speed is preformatted in another area different from the signal track. An auxiliary signal detection unit for detecting an auxiliary synchronization signal and an auxiliary clock from the optical disk, a reference clock generation unit for generating a reference clock based on the auxiliary clock from the auxiliary signal detection unit, and an auxiliary clock from the auxiliary signal detection unit. A reference synchronizing signal generating means for generating a reference synchronizing signal based on the reference signal; a reproducing means reproducing the synchronizing signal recorded on the signal track; an auxiliary synchronizing signal from the auxiliary signal detecting means; Using the reference clock from the clock generation means, it is adjacent to the discontinuous recording position on the signal track. First recording means for recording clock stabilization information in a part of a unit block, pseudo-synchronization generation means for generating a pseudo-synchronization signal based on the clock stabilization information from the first recording means, and pseudo-synchronization signal from the pseudo-synchronization generation means Second recording means for recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position using the reference clock from the reference clock generation means, and a reference synchronization signal and a reference clock from the reference synchronization generation means. A third recording unit for recording user information in at least one subsequent unit block connected to the unit block adjacent to the discontinuous recording position using a reference clock from the generation unit;

[0024]

According to the above construction, in the present invention, the clock stabilization information is provided in the block section adjacent to the discontinuous recording position on the signal track of the optical disk in which the auxiliary signal is preformatted in another area different from the signal track. Recorded with. As a result, the user information recorded in the block section adjacent to the discontinuous recording position on the signal track is reproduced stably, and the recording capacity of the optical disk is increased. According to the present invention, a blank section is selectively generated between the discontinuous recording position on the signal track of the optical disc and the clock stabilization information, based on the relationship between the phases of the reproduction synchronization signal and the auxiliary synchronization signal included in the auxiliary signal. To be done. As a result, the clock stabilization information is recorded in a block section adjacent to the discontinuous recording position so as to be synchronized with the reproduction synchronization signal. Also, the present invention keeps the recording capacity of the optical disk constant by recording information on the optical disk only when the reference clock is synchronized with the auxiliary clock included in the auxiliary signal, and minimizes the occurrence of errors. Become

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. FIG. 5 illustrates an optical disc recording apparatus according to an embodiment of the present invention. In FIG. 5, an optical disk recording device includes a spindle motor (26) for rotating an optical disk (24), a servo unit (30) connected to an optical pickup (28), and a motor drive unit connected to the spindle motor (26). (32) can be said. The optical pickup (28) irradiates one main light beam (MB) and two auxiliary light beams (SB1, SB2) to the track (22) in the groove of the optical disk (24) as shown in FIG. Information is recorded by the light beam (MB), and the pre-formatted auxiliary signal is read by the auxiliary light beams (SB1, SB2). The optical pickup (28) is located between the laser diode (LD) and the photodetector (PD) and splits the laser light beam into a beam splitter (B).
S), an optical disk (24) and a beam splitter (B)
It has an objective lens (OL) installed during S). The objective lens (OL) collects a laser light beam traveling from the beam splitter (BS) toward the optical disk (24).
The beam splitter (BS) is a laser diode (L
The laser light beam from D) is applied to the surface of the optical disk (24) via the objective lens (OL), and the reflected light beam reflected by the optical disk (24) passes through the sensor lens (SL). Via a photodetector (PD). The sensor lens (SL) focuses the light beam traveling from the beam splitter (BS) to the light detector (PD) and adjusts the focus by the astigmatic method. The light beam generated by the laser diode (LD) is divided into three light beams (MB, SB) by a diffraction grating (GT).
1, SB2). And a diffraction grating (GT)
The light beams (MB, SB1, SB2) separated by are passed through a beam splitter (BS) and passed through an objective lens (O).
L), as shown in FIG. 2, the track of the groove of the optical disk (24).
It is focused on (22). Track of groove of optical disk (24)
Light beams (MB, SB1, SB) reflected by (22)
2) is an objective lens (OL) and a beam splitter (B)
The light is focused on the surface of the photodetector (PD) by the sensor lens (SL) via S). The photodetector (PD) converts the auxiliary light beams (SB1, SB2) into electrical signals.
The servo section (30) drives an actuator (ACT) in the optical pickup (28) by an electric signal from the photodetector (PD) to perform focusing servo, tracking servo, and the like. On the other hand, the motor drive unit (32) adjusts the rotation speed of the spindle motor (26) according to a signal from the servo unit (30).

The optical disk recording device further includes a carrier signal detector (34) and an auxiliary signal decoder (36) connected in series to the photodetector (PD) of the optical pickup (28). The carrier signal detector (34) detects the carrier signal (Pc) from the electric signal from the photodetector (PD), and outputs an auxiliary signal decoder (36).
Decodes the auxiliary address (PAdd) and the auxiliary clock (PCLK) from the carrier signal (Pc) and the auxiliary synchronization signal (PYre) as shown in FIG. The auxiliary synchronizing signal (PYre) divides the signal track (20 or 22) of the optical disc (24) into unit blocks of a fixed size, and the auxiliary address (PAdd) indicates a physical position of each unit block. Also, the optical disk recording apparatus according to the embodiment of the present invention provides the auxiliary synchronization signal (P) from the auxiliary signal decoder (36).
Yre) from the reference synchronizing signal generator (38) and the reference clock generator (40) from the stabilizing information control signal (CVFO).
And a reference clock (SCLK) from the reference clock generator (40).
A VFO signal generator (44) for generating an O signal is provided. The reference synchronizing signal generator 38 generates a reference synchronizing signal (SYre) phase-locked to the auxiliary synchronizing signal (PYre). The reference clock generator (40) generates a reference clock (SCLK) as shown in FIG. 6 whose phase and frequency are synchronized with the auxiliary clock (PCLK) from the auxiliary signal decoder (36). The frequency of the reference clock (SCLK) increases from N times the auxiliary clock (PCLK) to M times the auxiliary clock for a certain period from the start of recording. After the elapse of this fixed period, the frequency of the reference clock (SCLK) is again increased from M times the auxiliary clock (PCLK) to the auxiliary clock (PC).
LK). More specifically, the reference clock (SCLK) corresponds to a section from the discontinuous recording position (DCP) to the position on the signal track (20 or 22) of the optical disc 24 where the recording of the VFO signal is completed. During the period, the frequency has a frequency varying from M times the auxiliary clock (PCLK) to N times the auxiliary clock (PCLK). After the VFO signal is recorded, the reference clock (SCLK) is a period or a fixed period corresponding to the section from the end position of the section where the VFO signal is recorded to the end point of the unit block adjacent to the discontinuous recording position (DCP). During a period corresponding to a number of unit blocks, a frequency gradually decreases from M times to N times of the auxiliary clock (PCLK). And the reference clock generator (4
0) is a stabilizing information control signal (CVFO) using a recording start signal (WRsta) as shown in FIG. 6 from the control unit (50) and an auxiliary synchronization signal (PYre) from the auxiliary signal decoder (36). Occurs. This stabilization information control signal (C
VFO) is the signal track (20 or 22) of the optical disk (24)
The VFO signal can be inserted into the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disc (24) where the phase of the clock signal recorded on the optical disk (24) changes rapidly.
As shown in FIG. 6, the stabilization information control signal (CVFO) is such that the VFO signal is recorded in a part of a unit block adjacent to the discontinuous recording position (DCP).
The pulse has a considerably shorter width than the unit block on the signal track (20 or 22) of (24). The reference clock generator (40) uses the reference clock (SCLK) as the auxiliary clock (P
CLK) can generate a locking signal (LK) having a specific logic (e.g., high logic) when the frequency has a multiple of a certain range as compared with the frequency (CLK). The pseudo synchronizing signal generator (42) detects the end point (for example, falling edge) of the stabilization information control signal (CVFO).
, A pseudo synchronization signal (PSre) that maintains a specific logic (for example, high logic) for a certain period. This pseudo synchronization signal (PSre) has a pulse of a specific logic that is narrower than the reference synchronization signal. To this end, the pseudo-synchronous signal generator (42) may include a monostable multivibrator.

Further, the optical disk recording apparatus has a recording information processing section (46) for inputting user information, and a VFO.
VFO signal from signal generator (44) and recording information processor (46)
And a control switch (SW1) for selectively supplying the recording signal from the optical controller (48) to the light controller (48). Record information processing unit (46)
Generates user block information by dividing user information by a certain size, and adds an auxiliary address (P
Add) and the pseudo sync signal (PSre) from the pseudo sync signal generator (42) or the reference sync signal (SYre) from the reference sync signal generator (38) to form a user information block. The recording information processing section (46) controls the control switch (SW1) in accordance with the reference clock (SCLK) from the reference clock generator (40) using the user information as a recording signal.
To supply. The user information block including the pseudo synchronizing signal (PSre) is transmitted by a reference clock (SCLK) having a frequency M times the frequency of the auxiliary clock (PCLK), and thus together with the VFO signal, a signal track (20 or 22) Recorded in one unit block above. That is, the user information block including the pseudo synchronization signal (PSre) has a shorter cycle than the user information block including the reference synchronization signal (SYre) by being temporally compressed. The control switch (SW1) selectively transmits the VFO signal and the recording signal to the light controller (48) according to the logic state of the stabilization information control signal (CVFO) from the reference clock generator (40). More specifically, when the stabilization information control signal (CVFO) maintains a specific logic (that is, high logic), the control switch (SW1) switches the VFO signal from the VFO signal generator (44). Is supplied to the light controller (48). On the contrary,
The stabilization information control signal (CVFO) is based on a base logic (eg,
When the low logic is maintained, the recording signal from the recording information processing section (46) is transmitted to the light controller (48). Light controller (4
8) The laser diode (LD) is turned on and off according to the logical value of the output signal of the control switch (SW1) so that the user information block is a signal track of the optical disc (24), that is, a mountain track (20) or a groove track (22). ). At this time, the unit block adjacent to the discontinuous recording position (DCP) of the signal track (20 or 22), that is, the signal track where the foremost part of the user information is recorded at the start of recording
In an arbitrary unit block on (20 or 22), a pseudo sync signal (PSre) block identification code and a user block information are sequentially recorded starting with a VFO signal which is clock stabilization information as shown in FIG. On the other hand, in each of the block sections separated from the discontinuous recording position (DCP), a reference synchronization signal (SYre) block identification code and user block information are recorded.

Finally, the control unit (50) controls the operation of the servo unit (30) and the motor drive unit (32), and also controls the operation mode of the light controller (48). Further, the control unit 50 generates a recording start signal (WRsta) having a pulse of a specific logic (for example, high logic) at the time of starting recording. The recording start signal (WRsta) is supplied to a reference clock generator (40), and VFO, which is clock stabilization information, is recorded in a fixed section from a recording discontinuity point on a signal track (20 or 22) on the optical disk (24). Allow the signal to be recorded. Further, the control unit (50) can input a locking signal (LK) from the reference clock generator (40). The controller 50 selectively enables the recording operation of the light controller 48 according to the logic state of the locking signal (LK). The control unit (50) controls the optical controller (48) to execute the recording operation only when the locking signal (LK) maintains a specific logic (for example, high logic) so that the recording density of the optical disc (24) is constant. And prevent errors from occurring.

FIG. 7 shows the reference clock generator (4) shown in FIG.
0) is a block showing in detail. In FIG. 7, a reference clock generator (40) includes a frequency divider (54) for inputting a reference clock (SCLK) from a voltage controlled oscillator (52) via a first AND gate (62), and a frequency divider (54). A phase comparator (56) for inputting the output signal of (54) and a frequency comparator (58) are provided. First
The AND gate (62) switches the reference clock (SCLK) supplied from the voltage controlled oscillator (52) to the frequency divider (54) according to the stabilization information control signal (CVFO). The first AND gate (62) prevents the reference clock (SCLK) from the voltage controlled oscillator (52) from being supplied to the frequency divider (54) when the stabilization information control signal (CVFO) maintains a high logic.
That is, the first AND gate (62) supplies a low signal of low logic to the frequency divider (54). As a result, a logic signal of low logic or high logic is also generated in the frequency divider (54). At this time, since the phase comparator 56 compares the phase of the auxiliary clock (PCLK) from the auxiliary signal decoder 36 shown in FIG. 5 with the logic signal from the frequency divider 54, it rapidly increases. A phase error signal having a voltage signal is supplied to an integrator (60). The frequency comparator (58) for comparing the frequency of the logic signal from the frequency divider (54) with the auxiliary clock (PCLK) also supplies a frequency error signal having a rapidly increasing voltage signal to the integrator (60). Integrator (60)
Is the phase error signal from the phase comparator (56) and the frequency comparator
The frequency error signals from (58) are respectively integrated to remove high frequency component noise signals contained in these signals. Integrator
The voltage controlled oscillator (52) uses the integrated phase error signal and frequency error signal from (60) to
The frequency of K) is rapidly increased from N times the auxiliary clock (PCLK) to M times the auxiliary clock (PCLK). As a result, the frequency of the reference clock (SCLK) rapidly increases from N times to M times of the auxiliary clock (PCLK) at the rising edge of the clock stabilization information control signal (CVFO).
M times of the auxiliary clock (PCLK) is maintained until the falling edge instruction of the clock stabilization information control signal (CVFO). On the other hand, when the stabilizing information control signal (CVFO) maintains the low logic, the first AND gate (62) uses the reference clock (SCLK) from the voltage controlled oscillator (52) as the frequency divider.
(54). In this case, the frequency divider (54) uses the reference clock (SCLK) from the first AND gate (62).
Is divided by N. At this time, the phase comparator 56 generates a phase error signal having a voltage signal gradually reduced by a phase difference between the auxiliary clock PCLK and the frequency-divided clock signal from the frequency divider 54. I do. Similarly, a frequency comparator
(58) also generates a frequency error signal whose voltage gradually decreases due to the difference in frequency between the clock signal from the frequency divider (54) and the auxiliary clock (PCLK). Then, the integrator (6
A voltage-controlled oscillator (52) for inputting a phase error signal and a frequency error signal via (0) gradually increases the frequency of the reference clock (SCLK) from M times the auxiliary clock (PCLK) to N times the auxiliary clock (PCLK). Will be lowered. Accordingly, the frequency of the reference clock (SCLK) is maintained for a certain period (for example, the clock stabilization information (CVFO)) from the falling edge of the clock stabilization information control signal (CVFO).
VFO) during the interval from the end position of the section on the signal track (20, 22) where the clock stabilization information is recorded to the end position of the unit block where the clock stabilization information is recorded) from M times the auxiliary clock (PCLK). It gradually decreases up to N times. At the same time, this reference clock (SCLK) is supplied to the VFO signal generator (44) and the recording information processing section (46) shown in FIG. Also, when the frequency-divided reference clock signal has a frequency difference within a certain range as compared with the auxiliary clock (PCLK), that is, the reference clock (SCLK) has a frequency that is N to M times the auxiliary clock (PCLK). , The frequency comparator 58 generates a locking signal (LK) having a specific logic (for example, high logic). This locking signal (LK) is supplied to the control unit (50) shown in FIG.

Then, the reference clock generator (40)
The recording start signal (WRst) from the control unit (50) shown in FIG.
a), and a NAND gate (66) for inputting an auxiliary synchronizing signal (PYre) from the auxiliary signal decoder (36) shown in FIG. The first latch 64 has a specific logic (ie, high logic) at its own set terminal (S).
When a write start signal (WRsta) is input, a high logic output signal is generated at its own output terminal (Q). The NAND gate 66 performs a NAND operation on the output signal of the first latch 64 and the auxiliary synchronizing signal PYre, and selectively toggles the second latch 68 according to the result. That is, the NAND gate 66 generates a low logic pulse only when both the output signal of the first latch 64 and the auxiliary synchronization signal (PYre) maintain the high logic. The second latch (6
8) changes the logic signal on its output terminal (Q) from low logic to high logic from the rising edge of the low logic pulse from the NAND gate (66). The first and second latches (64,
68) is a base information (ie, low logic) stabilization information control signal (CVFO) applied at its own reset terminal (R).
Is initialized by

The reference clock generator (40) has a second AND gate (70) for inputting a reference clock (SCLK) from the voltage controlled oscillator (52) and a counter for inputting an output signal of the second latch (68). (72) and an inverter (74) for inputting a carry signal from the counter (72). 2nd AN
The D gate 70 counters the reference clock (SCLK) from the voltage controlled oscillator 52 only while the stabilization information control signal (CVFO) maintains a specific logic (ie, high logic).
The signal is transmitted to the clock terminal (CLK) of (72). The counter (72) is connected to the second latch (68) toward the reset terminal (R) thereof while a high logic signal is applied to the counter (72).
Reference clock (SCLK) supplied from ND gate (70)
Is counted. Then, the counter (72) generates a high logic carry signal when the count value reaches “K”. After generating the carry signal, the counter 72 stops the counting operation by a low logic signal supplied from the second latch 68 to its reset terminal R. The inverter 74 inverts the carry signal from the counter 72, and uses the inverted carry signal as a stabilizing information control signal (CVFO) as the first and second AND gates 62, 70, and the first and second AND gates. latch
(64, 68) to the control switch (SW1) and the pseudo synchronizing signal generator (42) shown in FIG. As a result, the second latch (68), the second AND gate (70), the counter (72) and the inverter (74) have a certain width from the falling edge of the first auxiliary synchronization signal (PYre) at the start of recording. Performs the function of a monostable pulse generator that generates a stabilized information control signal (CVFO) having a high logic pulse.

FIG. 8 shows a block diagram of an optical disk recording apparatus according to another embodiment of the present invention. The optical disk recording device according to the other embodiment shown in FIG. 8 is different from the optical disk recording device shown in FIG. S
W2). At the same time, the optical disc recording apparatus according to another embodiment is the same as the reference clock generator (40) shown in FIG.
Instead of an adaptive reference clock generator (76).

The adaptive reference clock generator (76) is shown in FIG.
A reference clock (SCKL) as shown in FIG. 9 is generated similarly to the reference clock generator (40) shown in FIG. 9, and the reference clock (SCKL) is used as a recording information processing unit (46) and a VFO signal generator (44) To supply. Then, the adaptive reference clock generator (76) performs the recording start signal (WRst) as shown in FIG.
a) occurs, the first auxiliary synchronization signal (PYre)
Margin control signals (Cs
pc) and a stabilizing information control signal (CVFO).
In response to the margin control signal (Cspc), the second control switch (SW2) selectively connects the recording information processing section (46) to the optical controller (48) to thereby control the signal track (20 or 22) of the optical disk (24). ), A blank section in which no information is recorded is generated. This blank section is a discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disk (24).
And the clock stabilization information section. That is, in the block section adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disk (24), a blank section (SPC), a VFO signal (VFO), a pseudo synchronization A signal (PSre), a block identification signal, and user block information are recorded.

An optical disk recording apparatus according to another embodiment of the present invention comprises a photodetector (P) in an optical pickup (28).
A reproduction signal processing unit (51) for reproducing the output signal of D) and supplying a reproduction synchronization signal (RYre) to the adaptive reference clock generator (76) may be further provided. In this case, the adaptive reference clock generator 76 changes the logic state of the margin control signal (Cspc) according to the relationship between the phases of the reproduction synchronization signal (RYre) and the auxiliary synchronization signal (PYre). As shown in FIGS. 10 and 11, the adaptive reference clock generator (76) sets the phase of the reproduction synchronization signal (SYre) to the auxiliary synchronization signal (PYr).
In the case earlier than e), the blank control signal (Cspc) maintains the base logic (ie, low logic) so that no blank section appears on the signal track (20 or 22) of the optical disc (24). . That is, the signal track of the optical disc (24)
In the unit block adjacent to the discontinuous recording position (DCP) on (20 or 22), a VFO signal (VFO), a pseudo sync signal (PSre), a block identification signal, and user block information are recorded. On the other hand, as shown in FIG. 12, when the phase of the reproduction synchronizing signal (RYre) is later than that of the auxiliary synchronizing signal (PYre), the adaptive reference clock generator (76) sets the margin control signal (Cspc) to the auxiliary synchronizing signal (PYre). From the falling edge to the rising edge of the reproduction synchronizing signal (RYre) to generate a blank section on the signal track (20 or 22) of the optical disc (24). That is, the unit block adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disk (24) has a blank section (SP) as shown in FIG.
C), VFO signal (VFO), pseudo-synchronous signal (PSr)
e), a block identification signal and user block information are recorded.

FIG. 13 is a circuit diagram showing in detail the first embodiment of the adaptive reference clock generator (76) shown in FIG.
In FIG. 13, the adaptive reference clock generator (76)
When compared with the reference clock generator (40) shown in
A third latch (78), a second counter (84), a second inverter (86), a voltage controlled oscillator (52) and a second counter connected in series between the NAD gate (66) and the second latch (68); (84)
Divider connected in series between clock terminals (CLK)
(80) and a third AND gate (82). Further, the adaptive reference clock generator (76) is provided with the first AND shown in FIG.
A reference clock (SCLK) from a voltage controlled oscillator (52), a stabilization information control signal (CVFO) from a first inverter (74) and a second inverter (86) instead of the gate (62)
AND which inputs the margin control signal (Cspc) from the
A gate (88) is provided.

The third latch (78) changes the logic signal on its output terminal (Q) from low logic to high logic at the rising edge of the output signal of the NAND gate (66). That is, the third latch 78 receives the first auxiliary synchronization signal (PYr) after the recording start signal (WRsta) is generated as shown in FIG.
A high logic output signal is generated in response to the falling edge instruction of e). The second frequency divider (80) divides the frequency of the reference clock (SCLK) from the voltage controlled oscillator (52) by N, and supplies the frequency-divided reference clock to the third AND gate (82). The third AND gate 82 receives the divided reference from the second frequency divider 80 only while the margin control signal Cspc maintains a specific logic (ie, high logic) as shown in FIG. The clock is transmitted to the clock terminal (CLK) of the second counter (84). The second counter (84) is added by the frequency-divided reference clock from the third AND gate (82) while a high logic signal is applied from the third latch (78) to its reset terminal (R). Count. Also, the second counter
(84) generates a high logic carry signal when the count value reaches "L". Also, after generating the carry signal, the second counter 84 stops the counting operation by the low logic signal supplied from the third latch 78 to its own reset terminal R. . The second inverter (86) inverts the carry signal from the second counter (84) and converts the inverted carry signal into a margin control signal (Csp).
c) The third and fourth AND gates (82, 88), the third latch (78) and the second control switch (S
W2). As a result, the third latch (78), the third A
At the start of recording, the ND gate 82, the second counter 84, and the second inverter 86 provide the first auxiliary synchronization signal (PY).
It performs the function of a monostable pulse generator that generates a margin control signal (Cspc) having a high logic pulse of a certain width from the falling edge of re). In response to the margin control signal (Cspc), the second latch (68) controls the stabilization information control signal (CVFO).
Determine the point of occurrence of That is, the second latch (68) starts the counting operation of the first counter (72) from the falling edge of the margin control signal (Cspc) from the second inverter (86), and then starts the counting operation from the first inverter (74). Initialization by the low logic stabilization information control signal (CVFO) causes the stabilization information control signal (CVFO) to have a high logic of a fixed width from the falling edge of the margin control signal (Cspc) as shown in FIG. To

On the other hand, the fourth AND gate (88) supplies a reference clock signal (Cspc) and a stabilizing information control signal (CVFO) supplied from the voltage controlled oscillator (52) to the first frequency divider (54) by the voltage controlled oscillator (52). SCLK). 4th AND
The gate 88 receives the reference clock (SCLK) from the voltage controlled oscillator 52 when at least one of the margin control signal (Cspc) and the stabilization information control signal (CVFO) maintains high logic. It is not supplied to the 1 frequency divider (54). That is, the fourth AND gate (88) is connected to the optical disk (24).
During the period when the margin signal and the VFO signal are recorded on the signal track (20 or 22), the reference clock (SCLK) is not supplied to the first frequency divider (54). Unlike this,
The margin control signal (Cspc) and the stabilization information control signal (CV
FO) maintains a low logic, the fourth AND gate
(88) is a reference clock (SCL) from the voltage controlled oscillator (52).
K) is supplied to the first frequency divider (54).

Except for the second and third latches (68, 78), third and fourth AND gates (82, 88), frequency divider (80), second counter (86) and second inverter (86). The description of the operation of the remaining components of the adaptive reference clock generator 76 is the same as that of FIG.

FIG. 14 is a circuit diagram showing in detail a second embodiment of the adaptive reference clock generator (76) shown in FIG. The adaptive reference clock generator (76) shown in FIG. 13 differs from the adaptive reference clock generator (76) shown in FIG. 13 except that the fourth AND gate (88) is replaced by a clock regulator (90).
It has the same circuit configuration as. This clock 90 is a reference clock for a certain period from the time when the margin control signal (Cspc) is enabled (for example, during a period from a discontinuous recording point to a point where one unit block ends). (SCLK) has the frequency of the auxiliary clock (PCL).
M) of K) is kept constant. To this end, the clock controller (90) operates at regular intervals during a period corresponding to one unit block after the blank control signal (Cspc) from the second inverter (86) is changed from low logic to high logic. The reference clock (SCLK) transmitted from the voltage controlled oscillator (52) to the first frequency divider (54) is removed one by one. In this case, the phase error signal generated from the phase comparator (56) and the frequency error generated from the frequency (58) increase and decrease once every fixed cycle. Then, the voltage controlled oscillator 52 responding to the phase error signal and the frequency error signal adjusts the phase and frequency of the reference clock (SCLK) to adjust the reference clock (SCL).
The phase of K) is made to coincide with the phase of the auxiliary clock (PCLK), and the frequency of the reference clock (SCLK) is maintained constant at M times the frequency of the auxiliary clock (PCLK). Conversely, the margin control signal (Csp
c) When the stabilizing information control signal (CVFO) maintains the base logic (low logic), the clock controller 90 uses the reference clock (SCLK) from the voltage controlled oscillator 52 as it is as the first frequency divider. (54) to change the frequency of the reference clock (SCLK) to the auxiliary clock (PCLK).
Is kept constant N times.

FIG. 15 shows the clock controller (9) shown in FIG.
FIG. 2 is a circuit diagram illustrating in detail (0). In FIG. 15, a clock controller (90) is a stabilizing information control signal (CVFO) from the first and second inverters (74, 86) shown in FIG.
OR gate (92) for inputting a margin control signal (Cspc)
And a fifth AND gate commonly receiving a reference clock (SCLK) from the voltage controlled oscillator (52) shown in FIG.
(94), a third frequency divider (96) and an exclusive OR (hereinafter referred to as "XOR") gate (98). The OR gate 92 performs an OR operation on the stabilizing information control signal (CVFO) and the margin control signal (Cspc), and generates a pulse signal that maintains the high logic during the high logic period of the two signals.
The fifth AND gate 94 transmits the reference clock (SCLK) to the clock terminal (CLK) of the third counter (100) while the output signal of the OR gate (92) maintains the high logic. The third counter (100) counts the number of clock signals supplied from the fifth AND gate (94) to its own clock terminal (CLK). On the other hand, the third frequency divider (96) divides the reference clock (SCLK) at a constant frequency division ratio (for example, 4), and divides the frequency-divided reference clock into a sixth AND gate (1).
02) to the fourth counter (104). 4th
The counter (104) counts the number of frequency-divided reference clocks from the sixth AND gate (102). 3rd counter
The count value of (100) and the count value of the fourth counter (104) are compared by the comparator (106). This comparator (106)
Supplies a high logic comparison signal to the sixth AND gate 102 when the two count values are the same, so that the reference clock divided by the third frequency divider 96 is applied to the fourth counter 1.
04) and XOR gate (98).
That is, the sixth AND gate (102) changes the count value of the fourth counter (104) from the start of recording to the third counter (10).
The divided reference clock is supplied to the XOR gate (98) until the count value becomes equal to the count value of (0).
The XOR gate (98) inverts the phase of the reference clock (SCLK) by 180 ° each time the frequency-divided reference clock from the sixth AND gate (102) maintains the high logic, so that the XOR gate (98) shown in FIG. One cycle of the reference clock is eliminated from the reference clock (SCLK) supplied to the one-frequency divider (54). The frequency division ratio of the third frequency divider (96) depends on the width of the high logic of the margin control signal (Cspc) and the stabilization information control signal (C
VFO) is determined by the ratio of the period corresponding to the high logic width to the unit block period.

FIG. 16 is a circuit diagram showing in detail a third embodiment of the adaptive reference clock generator (76) shown in FIG.
This adaptive reference clock generator (76) uses a voltage controlled oscillator (5
2) the reference clock (SCLK) from the first AND gate
The frequency divider includes a first frequency divider (54) input through (108), a phase comparator (56) for inputting an output signal of the first frequency divider (54), and a frequency comparator (58). The first AND gate (108) switches the reference clock (SCLK) according to the switching control signal. The first AND gate (108) prevents the reference clock (SCLK) from the voltage controlled oscillator (52) from being supplied to the first frequency divider (54) when the switching control signal maintains the high logic. That is, the first AND gate (108) supplies a low logic signal to the first frequency divider (54). As a result, a logic signal of low logic or high logic is also generated in the first frequency divider (54). At this time, since the phase comparator 56 compares the phase of the auxiliary clock (PCLK) from the auxiliary signal decoder 36 shown in FIG. 8 with the logic signal from the first frequency divider 54, it rapidly increases. A phase error signal having a voltage signal is supplied to an integrator (60). A frequency comparator (58) that compares the frequency of the logic signal from the first frequency divider (54) with the auxiliary clock (PCLK) also converts a frequency error signal having a rapidly increasing voltage signal into an integrator (6).
0). The integrator (60) integrates the phase error signal from the phase comparator (56) and the frequency error signal from the frequency comparator (58), respectively, and removes a high frequency component noise signal contained in these signals. The voltage-controlled oscillator (5) is controlled by the integrated phase error signal and frequency error signal from the integrator (60).
2) The frequency of the reference clock (SCLK) is increased from N times the auxiliary clock (PCLK) to M of the auxiliary clock (PCLK).
Increase sharply up to twice. As a result, the reference clock (SCL
The frequency of K) sharply increases from N times to M times of the auxiliary clock (PCLK) at the rising edge of the switching control signal, and then to the auxiliary clock (PCLK) until the falling edge of the switching control signal.
Will be maintained at M times. When the switching control signal maintains low logic, the first AND gate (108) uses the reference clock (SCLK) from the voltage controlled oscillator (52) as the first frequency divider.
(54). In this case, the first frequency divider (54) is connected to the first AN
The reference clock (SCLK) from the D gate (108) is divided by N. At this time, the phase comparator (56) operates the auxiliary clock (PC
LK) and a phase error signal having a voltage signal that gradually decreases due to a phase difference between the frequency-divided clock signal from the first frequency divider (54). Similarly, the frequency comparator (58) also uses the clock signal from the first frequency divider (54) and the auxiliary clock (PC
LK) to generate a frequency error signal whose voltage gradually decreases. Then, the voltage controlled oscillator (52) that inputs the phase error signal and the frequency error signal via the integrator (60) increases the frequency of the reference clock (SCLK) from M times the auxiliary clock (PCLK) to the auxiliary clock (PC).
LK). As a result, the frequency of the reference clock (SCLK) is changed for a certain period (for example, the clock) from the falling edge of the switching control signal (that is, the position on the signal track (20 or 22) where the recording of the clock stabilization information ends). An auxiliary clock (P
CLK) gradually decreases from M times to N times. This recording clock (SCLK) is generated by the VFO signal generator shown in FIG.
(44) and the recording information processing section (46). Further, the frequency comparator 58 determines that the frequency-divided reference clock has a frequency difference within a certain range as compared with the auxiliary clock (PCLK), that is, the reference clock (SCLK) has the auxiliary clock (PCLK).
A locking signal LK having a specific logic (e.g., high logic) is generated when the frequency is N to M times higher than that of the clock signal CLK. This locking signal (LK) is supplied to the control unit (50) shown in FIG.

The adaptive reference clock generator (76) receives the first latch (110) from the control unit (50) shown in FIG. 8 for inputting the recording start signal (WRsta) as shown in FIGS. ) And a NAND gate for inputting an auxiliary synchronizing signal (PYre) from the auxiliary signal decoder (36) shown in FIG.
(112) and a second AND gate (116) for inputting a reproduction synchronizing signal (RYre) from the reproduction signal processing section (51) shown in FIG.
Is further provided. The first latch (110) outputs a high logic output signal to its own output terminal (Q) when a specific logic (that is, high logic) recording start signal (WRsta) is input to its own set terminal (S). Occur. The NAND gate 112 performs a NAND operation on the output signal of the first latch 110 and the auxiliary synchronization signal (PYre), and selectively toggles the second latch 114 according to the result. NAND gate (1
12) is an output signal of the first latch 110 and an auxiliary synchronizing signal (PY).
When re) maintains high logic, a pulse of low logic is generated. The second latch (114) changes the signal on its output terminal (Q) from low logic to high logic at the rising edge of the low logic pulse from the NAND gate (112).
On the other hand, the second AND gate (116) performs an AND operation on the output signal of the first latch (110) and the reproduction synchronization signal (RYre) to generate a first AND signal.
When the output signal of the latch (110) maintains the high logic, that is, at the start of recording, the reproduction synchronization is performed only when the first user information block is recorded on the signal track (20 or 22) of the optical disc (24). The signal (RYre) is passed.

The adaptive reference clock generator (76) includes a second frequency divider (118) connected in series to the voltage controlled oscillator (52),
A third AND gate (120), a first counter (122), and a first inverter (124) are provided. The second frequency divider (118) divides the reference clock (SCLK) from the voltage controlled oscillator (52) into a constant frequency division ratio (N), and divides the divided reference clock into a third AND gate (120). To supply. The third AND gate 120 receives the frequency-divided reference clock from the second frequency divider 118 while the margin control signal Cspc maintains a specific logic (ie, high logic). To the clock terminal. The first counter (122) uses the divided reference clock supplied from the third AND gate (120) while a high logic signal is applied from the second latch (114) to its reset terminal (R). Count up. Then, the first counter (122) generates a high logic carry signal when the count value reaches “L”. After the first counter (122) generates a carry signal, the first counter (122) has its own reset terminal (R) from the second latch (114).
The counting operation is stopped by a low logic signal supplied to the counter. Alternatively, the first counter (12
2) when the low-level reproduction synchronization signal (RYre) is input from the second AND gate 116, that is, at the end of the first reproduction synchronization signal (RYre), the specific logic (eg,
High logic). Thereby, the first
The carry signal generated from the counter 122 keeps only the high logic, or has a certain width from the end of the auxiliary synchronizing signal (PYre), that is, the base signal having a width smaller than or equal to the N × L reference clock cycles. It will have a logic (eg, low logic) pulse. The first inverter (12
4) inverts the carry signal from the first counter (122), uses the inverted signal as a margin control signal (Cspc) as a third AND gate (120), and the second control switch (SW2) shown in FIG. ). The margin control signal (Cspc) is used for the operation mode of the first counter (122), that is, the reproduction synchronization signal (RYre) and the auxiliary synchronization signal (PYr).
The pulse having a specific logic (that is, high logic) is selectively provided due to the relationship between the phase and the phase e). The margin control signal (Cspc) is output after the reproduction synchronizing signal (RYre) ends as shown in FIGS. 10 and 11.
If e) is terminated, maintain the base logic (ie, low logic). In this case, the signal tracks (2
No margin section is generated at 0 or 22). On the other hand, when the reproduction synchronization signal (RYre) ends later than the end of the auxiliary synchronization signal (PYre) as shown in FIG. 12, the margin control signal (Cspc) has a pulse of a specific logic. At this time, the pulse of the margin control signal (Cspc) is
It has a width corresponding to a period from the end of the auxiliary synchronization signal (PYre) to the end of the reproduction synchronization signal (RYre). When a specific logical pulse is present in the blank control signal (Cspc), a blank section (SPC) corresponding to the width of the specific logical pulse is generated on the signal track (20 or 22) of the optical disk (24). Will be done.

Further, the adaptive reference clock generator (76) is connected to the output terminal of the second AND gate (116) in series with the fourth
An AND gate (126) and a third latch (128), a fifth AND gate (130), a second counter (132), and a second inverter (134) connected in series to the voltage controlled oscillator (52) are provided. The fourth AND gate (126) receives the blank control signal (Cspc) from the first inverter (124) and the second AND gate (11).
The output signal of (6) is subjected to an AND operation, and the third latch (128) is selectively toggled according to the result of the AND operation. 4th AND gate
(126) is a falling edge of the margin control signal (Cspc), that is, the end point of the margin control signal (Cspc) or the second AND.
At the falling edge of the output signal of the gate 116, that is, at the end of the first reproduction synchronization signal (RYre), the third latch 128
Toggle. At this time, the output signal of the third latch (128) changes from low logic to high logic. The fifth AND gate 130 is a voltage controlled oscillator only while the stabilization information control signal (CVFO) maintains a specific logic (ie, high logic).
The reference clock (SCLK) from (52) is used as the second counter
The signal is transmitted to the clock terminal (CLK) of (132). The second counter 132 receives the reference clock (S) supplied from the fifth AND gate 130 while the high logic signal is applied from the third latch 128 to its reset terminal R.
CLK). Also, the second counter
(132) generates a high logic carry signal when the count value reaches "K". After generating the carry signal,
The second counter (132) stops counting operation in response to a low logic signal supplied from the third latch (128) to its own reset terminal (R). The second inverter (134) inverts the carry signal from the second counter (132) and converts the inverted carry signal into a stabilizing information control signal (CVF).
O) as fifth AND gate (130), third latch (128)
Are supplied to the first control switch (SW1) and the pseudo synchronizing signal generator (42) shown in FIG. This stabilization information control signal (CVFO) is a margin control signal (Cs) as shown in FIG.
When the specific logic pulse is included in pc), the specific logic (for example, high logic) is maintained for a certain period from the end of the margin control signal (Cspc). On the other hand, when the margin control signal (Cspc) does not include a pulse of a specific logic as shown in FIGS.
e) the falling edge, ie for a certain period from the end point,
Maintain high logic. Then, the third latch 128 is initialized by the base information (ie, low logic) stabilization information control signal (CVFO) applied to its own reset terminal (R).

The adaptive reference clock generator (76) comprises a first
A fourth latch (138) toggling according to an output signal of the NAND gate (112), an OR gate (136) for inputting a stabilization information control signal (CVFO) together with a third inverter (140);
Is provided. The OR gate (136) outputs the margin control signal (Csp
c) and a stabilizing information control signal (CVFO) are OR-operated,
The output signal of the second latch (114) is initialized based on the calculated result. The fourth latch (138) is the second latch (114)
Similarly to the above, at the rising edge of the low logic pulse from the first NAND gate 112, ie, at the start of recording, the signal on its own output terminal (Q) is changed from the end of the first auxiliary synchronization signal (PYre). Change from low logic to high logic.
The fourth latch (138) supplies its own output signal to the first AND gate (108) and the second NAND gate (144) as a switching control signal. The third inverter (140) inverts the stabilization information control signal (CVFO) and applies the inverted stabilization information control signal to the toggle terminal (T) of the fifth latch (142). The fifth latch 142 supplies a rising edge of the inverted stabilization information control signal supplied from the third inverter 140 to its toggle terminal T, that is, the end point of the stabilization information control signal CVFO. Generates a high logic signal at its output terminal (Q). The output signal of the fifth latch (142) is supplied to the first latch (110) and the second N
The signal is supplied to an AND gate (144). Second NAND gate
(144) is the output signal of the first latch (110) and the fourth latch (13
8) and the output signal of the fifth latch (142) are ANDed.
Operation is performed to generate a low logic pulse. This 2nd NA
The first, due to the low logic pulse from the ND gate (144),
The output signals of the fourth and fifth latches (110, 138, 142) are initialized. As a result, the output signal of the first latch 110 maintains the high logic from the rising edge of the recording start signal (WRsta), that is, from the start of recording to the falling edge of the stabilization information control signal (CVFO). The switching control signal generated from the fourth latch 138 is a falling edge of the auxiliary synchronizing signal (PYre), that is, a falling edge of the stabilization information control signal (CVFO) from the end point, that is, a stabilization information control signal (CVFO). ) Is maintained at a high logic level until the end of ()). On the other hand, the output signal of the fifth latch (142)
Since the latch 142 forms a circular loop with the second NAND gate 144, it has a high logic pulse form. The first AND gate (108) switches the reference clock (SCLK) supplied from the voltage controlled oscillator (52) to the first frequency divider (54) according to the switching control signal. First AND gate (108)
The reference clock (SCLK) from the voltage controlled oscillator (52) is a variable frequency divider when the switching control signal maintains the high logic.
(54). When the switching control signal maintains low logic, the reference clock (SCLK) from the first AND gate (108) and the voltage controlled oscillator (52) is used as the variable frequency divider.
(54).

FIG. 17 is a circuit diagram showing in detail a fourth embodiment of the adaptive reference clock generator (76) shown in FIG.
The adaptive reference clock generator (76) shown in FIG.
The circuit configuration is the same as that of the adaptive reference clock generator (76) of the third embodiment shown in FIG. 16 except that the ND gate (108) is replaced by a clock controller (146). The clock controller 146 controls the reference clock (SCLK) for a certain period from the time when the switching control signal is enabled (for example, during a period from a discontinuous recording position (DCP) to a point where one unit block ends). ) Is maintained constant at M times the auxiliary clock (PCLK). To this end, the clock controller (146) changes the voltage control oscillator (52) every fixed cycle while the switching control signal from the fourth latch (138) is changed from low logic to high logic and hits one unit block. ), The reference clock (SCLK) transmitted to the first frequency divider (54) is removed one by one. In this case, the phase error signal generated by the phase comparator (56) and the frequency error signal generated by the frequency comparator (58) increase once every certain cycle and then decrease. Then, the voltage controlled oscillator 52 responding to the phase error signal and the frequency error signal adjusts the phase and the frequency of the reference clock (SCLK) to adjust the phase of the reference clock (SCLK) to the phase of the auxiliary clock (PCLK). In addition, the frequency of the reference clock (SCLK) is maintained constant at M times the frequency of the auxiliary clock (PCLK). Then, the clock adjuster (146) removes the OR gate (92) for inputting the stabilization information control signal (CVFO) and the margin control signal (Cspc) among the circuit elements of the clock adjuster (90) shown in FIG. Instead of the fourth in FIG.
This can be realized by supplying a switching control signal from the latch (138).

[0047]

As described above, according to the present invention, clock stabilization information is provided in a block section adjacent to a discontinuous recording position on a signal track of an optical disk in which an auxiliary signal is preformatted in another area different from the signal track. Recorded with user information. As a result, the user information recorded in the block section adjacent to the discontinuous recording position on the signal track is reproduced stably, and the recording capacity of the optical disk is increased. Further, according to the present invention, a blank section is selectively generated between the discontinuous recording position on the signal track of the optical disc and the clock stabilization information by the pre / post relation of the phase of the reproduction synchronization signal and the auxiliary synchronization signal included in the auxiliary signal. Is done. As a result, the clock stabilization information is recorded in a block section adjacent to the discontinuous recording position so as to be synchronized with the reproduction synchronization signal. Further, the present invention records information on the optical disk only when the reference clock is synchronized with the auxiliary clock included in the auxiliary signal, thereby keeping the recording capacity of the optical disk constant and minimizing the occurrence of errors. Can be

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating an optical disk in which a hard sector type auxiliary signal is preformatted.

FIG. 2 is a diagram schematically illustrating an optical disk in which a soft sector type auxiliary signal is pre-formatted.

FIG. 3 shows a state where information is discontinuously recorded on a signal track of the optical disc shown in FIG. 2;

FIG. 4 shows a clock signal recorded on a signal track shown in FIG. 3 and a reproduced state of the clock signal.

FIG. 5 is a block diagram of an optical disc recording device according to an embodiment of the present invention.

6 is an output waveform diagram for each part shown in FIG.

FIG. 7 is a detailed circuit diagram of the reference clock generator shown in FIG. 5;

FIG. 8 is a block diagram of an optical disc recording apparatus according to another embodiment of the present invention.

9 is an output waveform diagram of each portion shown in FIG.

FIG. 10 is an output waveform diagram of each portion shown in FIG.

11 is an output waveform diagram of each part shown in FIG.

12 is an output waveform diagram of each portion shown in FIG.

FIG. 13 is a detailed circuit diagram of a first embodiment of the adaptive reference clock generator shown in FIG. 8;

FIG. 14 is a detailed circuit diagram of a second embodiment of the adaptive reference clock generator shown in FIG.

15 is a detailed circuit diagram of the variable phase delay device shown in FIG.

FIG. 16 is a detailed circuit diagram of a third embodiment of the adaptive reference clock generator shown in FIG.

FIG. 17 is a detailed circuit diagram of a fourth embodiment of the adaptive reference clock generator shown in FIG. 8;

[Explanation of symbols]

 10, 24 optical disc 12 signal track 14 sector 16 sector identification signal section 18 main information signal section 20 ··· Mountain track 22 ··· Groove track 26 ··· Spindle motor 28 ··· Optical pickup 30 ··· Servo unit 32 ··· Motor drive unit 34 Carrier signal detector 36 Auxiliary signal decoder 38 Reference synchronization signal generator 40 Reference clock generator 42 ... Pseudo synchronization signal generator 44... VFO signal generator 46... Recording information processing unit 48... Light controller 50. 51: playback signal processing unit 52: voltage-controlled oscillator 54 first frequency divider 56 phase comparator 58 frequency comparator 60 integrators 62, 108 First AND gates 64, 110 First latch 66, 112 NAND gate 68, 114 Second latch 70, 116 Second AND gate 72, 122 ... first counter 74, 124 ... first inverter 76 ... adaptive reference clock generator 78, 128 ... third latch 80 , 118... Second divider 82, 120... Third AND gate 84, 132... Second counter 86, 134... Second inverter 88 , 126... Fourth AND gate 90, 146. Clock adjuster 92: OR gate 94, 130 Fifth AND gate 96: Third divider 98: XOR gate 100 ..3rd counter 102... 6th AND gate 104... 4th counter 106... Comparator 138... 4th latch 140. .3rd inverter 142... 5th latch

Claims (15)

[Claims] An auxiliary signal for dividing a signal track into unit blocks is clock-stabilized at a part of a unit block adjacent to a discontinuous recording position on a signal track of an optical disk preformatted in another area different from the signal track. An optical disk recording method, comprising: recording information; and recording user information in a remaining portion of the unit block. 2. The optical disc recording method according to claim 1, further comprising the step of sequentially recording user information in a subsequent unit block arranged next to the unit block adjacent to the discontinuous recording position. 3. An auxiliary synchronization signal which divides a signal track into unit blocks and an auxiliary signal including an auxiliary clock indicating an information transmission speed in an area different from the signal track from an optical disk pre-formatted to the auxiliary synchronization signal. A first step of detecting a signal and an auxiliary clock; and a second step of recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track using the auxiliary synchronization signal and the auxiliary clock. And a third step of recording user information in a remaining portion of the unit block adjacent to the discontinuous recording position using the auxiliary synchronization signal and the auxiliary clock. 4. An auxiliary synchronization signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is obtained from an optical disk preformatted in another area different from the signal track. A first step of detecting a signal and an auxiliary clock, a second step of generating a reference clock based on the detected auxiliary clock, and using the detected auxiliary synchronization signal and the reference clock on the signal track. A third step of recording clock stabilization information in a part of the unit block adjacent to the discontinuous recording position; and using the clock stabilization information and the reference clock to record the remaining of the unit block adjacent to the discontinuous recording position. Recording a user information in a portion of the optical disk. 5. An auxiliary clock including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for instructing a transmission rate of information from an optical disk preformatted in another area different from the signal track. A second step of generating a reference clock based on the detected auxiliary clock; a third step of reproducing a synchronization signal recorded on the signal track; a reproduced synchronization signal and a reference A fourth step of recording clock stabilization information in a part of a unit block adjacent to the discontinuous recording position on the signal track using a clock; and a discontinuous recording position using the clock stabilization information and a reference clock. And a fifth step of recording user information in a remaining portion of the adjacent unit block. 6. An auxiliary synchronization signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is obtained from an optical disk preformatted in another area different from the signal track. A first step of detecting a signal and an auxiliary clock; a second step of generating a reference clock based on the detected auxiliary clock; and a third step of reproducing a synchronization signal recorded on the signal track.
And a fourth step of recording clock stabilization information in a part of a unit block adjacent to the discontinuous recording position on the signal track using the reproduced synchronization signal, the auxiliary synchronization signal, and the reference clock; A fifth step of recording user information in a remaining portion of a unit block adjacent to the discontinuous recording position using the clock stabilization information and the reference clock. 7. An auxiliary synchronization signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is obtained from an optical disk preformatted in another area different from the signal track. A first step of detecting a signal and an auxiliary clock; a second step of generating a reference clock based on the detected auxiliary clock; and a third step of reproducing a synchronization signal recorded on the signal track.
A step of recording clock stabilization information in a part of a unit block adjacent to the discontinuous recording position on the signal track using the reproduced synchronization signal, the auxiliary synchronization signal, and the reference clock; A fifth step of generating a pseudo synchronization signal based on the clock stabilization information; and recording user information in a remaining portion of the unit block adjacent to the discontinuous recording position using the pseudo synchronization signal and the reference clock. An optical disc recording method, comprising: 8. An auxiliary synchronization signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is obtained from an optical disk preformatted in another area different from the signal track. A first step of detecting a signal and an auxiliary clock, a second step of generating a reference clock based on the detected auxiliary clock, a third step of generating a reference synchronization signal based on the detected auxiliary synchronization signal, A fourth step of reproducing a synchronization signal recorded on the signal track;
A step of recording clock stabilization information in a part of a unit block adjacent to the discontinuous recording position on the signal track using the reproduced synchronization signal, the auxiliary synchronization signal, and the reference clock; A sixth step of generating a pseudo synchronization signal based on the clock stabilization information; and a step of recording user information in a remaining portion of the unit block adjacent to the discontinuous recording position using the pseudo synchronization signal and the reference clock. 7) recording user information in at least one subsequent unit block connected to the unit block adjacent to the discontinuous recording position using the reference synchronization signal and the reference clock;
And an optical disk recording method. 9. The clock stabilization information is provided in a part of a unit block adjacent to a discontinuous recording position on a signal track of an optical disk in which an auxiliary signal for dividing a signal track into unit blocks is preformatted in an area different from the signal track. An optical disc recording apparatus, comprising: a first recording unit that records a user information; and a second recording unit that records user information in a remaining portion of the unit block. 10. An auxiliary signal including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a transmission rate of information is transferred from an optical disk preformatted in another area different from the signal track. An auxiliary signal detection unit for detecting a synchronization signal and the auxiliary clock; and a part of a unit block adjacent to a discontinuous recording position on the signal track using the auxiliary synchronization signal and the auxiliary clock from the auxiliary signal detection unit. A first recording unit for recording clock stabilization information on the first and second auxiliary synchronization signals from the auxiliary signal detecting unit and the auxiliary clock using the auxiliary information and user information in a remaining portion of the unit block adjacent to the discontinuous recording position. An optical disc recording apparatus, comprising: a second recording unit for recording the information. 11. An auxiliary synchronization signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for instructing a transmission rate of information from an optical disk preformatted in another area different from the signal track. An auxiliary signal detection unit that detects a signal and an auxiliary clock; a reference clock generation unit that generates a reference clock based on the auxiliary clock from the auxiliary signal detection unit; an auxiliary synchronization signal from the auxiliary signal detection unit; A first recording unit that records clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on the signal track using the reference clock from a reference clock generation unit; Using the clock stabilization information and the reference clock from the reference clock generation means, the discontinuous An optical disc recording apparatus comprising: a second recording unit that records user information in a remaining portion of a unit block adjacent to a recording position. 12. An auxiliary clock including an auxiliary synchronizing signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed from an optical disk preformatted in another area different from the signal track. An auxiliary signal detecting means for detecting a reference clock; a reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means; a reproducing means for reproducing a synchronization signal recorded on the signal track; First, clock stabilization information is recorded in a part of a unit block adjacent to a discontinuous recording position on the signal track using a reproduced synchronization signal from a reproducing unit and the reference clock from the reference clock generating unit. Recording means; clock stabilization information from the first recording means; and Optical disk recording apparatus characterized by comprising a second recording means for recording the user information to the rest of the unit blocks by using the reference clock and adjacent to the discontinuous recording position. 13. An auxiliary synchronizing signal which divides a signal track into unit blocks and an auxiliary signal including an auxiliary clock indicating an information transmission speed are obtained from an optical disk preformatted in another area different from the signal track. Auxiliary signal detecting means for detecting a signal and an auxiliary clock; reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means; reproduction for reproducing a synchronization signal recorded on the signal track Means, using the reproduced synchronization signal from the reproducing means, the auxiliary signal from the auxiliary signal detecting means, and the reference clock from the reference clock generating means, adjacent to the discontinuous recording position on the signal track. First recording means for recording clock stabilization information in a part of the unit block, wherein the first recording means And second recording means for recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position using the clock stabilization information from the reference clock generation means and the reference clock from the reference clock generation means. An optical disk recording device characterized by the following. 14. An auxiliary synchronization signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission speed is obtained from an optical disk preformatted in another area different from the signal track. Auxiliary signal detecting means for detecting a signal and an auxiliary clock; reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means; reproduction for reproducing a synchronization signal recorded on the signal track Means, using the auxiliary synchronization signal from the auxiliary signal detection means, the reproduced synchronization signal from the reproduction means, and the reference clock from the reference clock generation means, adjacent to the discontinuous recording position on the signal track. First recording means for recording clock stabilization information in a part of the unit block, wherein the first recording means Pseudo synchronizing signal generating means for generating a pseudo synchronizing signal based on the clock stabilizing information from the computer; and the discontinuous recording using the pseudo synchronizing signal from the pseudo synchronizing signal generating means and the reference clock from the reference clock generating means. An optical disk recording apparatus, comprising: second recording means for recording user information in a remaining portion of a unit block adjacent to a position. 15. An auxiliary synchronizing signal which divides a signal track into unit blocks and an auxiliary signal including an auxiliary clock indicating an information transmission speed are obtained from an optical disk preformatted in another area different from the signal track. Auxiliary signal detecting means for detecting a signal and an auxiliary clock; reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means; and based on the auxiliary clock from the auxiliary signal detecting means. Reference synchronization generating means for generating a reference synchronization signal; reproducing means for reproducing a synchronization signal recorded on the signal track; auxiliary synchronization signal from the auxiliary signal detection means; reproduced synchronization signal from the reproduction means; Discontinuous recording on the signal track using the reference clock from the reference clock generating means First recording means for recording clock stabilization information in a part of a unit block adjacent to a unit, pseudo-synchronization generation means for generating a pseudo-synchronization signal based on the clock stabilization information from the first recording means, A second recording unit that records user information in a remaining portion of a unit block adjacent to the discontinuous recording position using the pseudo synchronization signal from the generation unit and the reference clock from the reference clock generation unit; User information is recorded in at least one subsequent unit block connected to a unit block adjacent to the discontinuous recording position using a reference synchronization signal from a reference synchronization generation unit and the reference clock from the reference clock generation unit. An optical disk recording apparatus comprising: a third recording unit.