JP3884180B2 - Optical disk device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical disc apparatus that records data on an optical disc and reproduces data recorded on the optical disc.
[0002]
[Prior art]
Recently, a digital video disc (DVD) has been developed as an optical disc of a large capacity recording medium, and an optical disc apparatus for recording / reproducing data recorded on the optical disc or reproducing data recorded on the optical disc has been developed. Has been.
[0003]
In such an optical disc apparatus, pits are formed by a mark length recording (mark edge recording) system, and channel data is recorded.
[0004]
In the reproduction circuit in the optical disk apparatus described above, the reproduction signal (after amplification) from the detector of the optical head is binarized by a comparator, and a signal obtained by integrating the binarized signal is fed back as a reference value of the comparator. The slice level control is performed so that the high level time and the low level time of the binarized signal are always constant.
[0005]
In this reproduction circuit, it is assumed that the DSV (Digital Sum Value: summed by letting bit 1 be +1 and bit 0 be −1) is 0, and the data can be reproduced accurately when the data pattern that becomes DSV0 is continuous. .
[0006]
However, in the DVD format, in the case of a special data pattern,
The DSV does not become “0”, and the DSV may monotonously increase or monotonously decrease with the data time, and data may not be reproduced correctly.
[0007]
[Problems to be solved by the invention]
An object of the present invention is to provide an optical disc apparatus capable of correctly reproducing data when a special data pattern is reproduced. Yes.
[0008]
[Means for Solving the Problems]
  The optical disk device of the present invention is an optical disk device for reproducing data recorded on an optical disk, wherein the optical diskOutput playback signal fromAn optical head;The reproduction signal is compared with a first slice level and converted into a first rectangular wave signal and output. When not reset, the first slice level is generated using the first rectangular wave signal. A first binarization circuit that compares the reproduction signal with a second slice level and converts it into a second rectangular wave signal and outputs the second rectangular wave signal; A second binarization circuit generated using the rectangular wave signal and a rectangular wave signal output from the first binarization circuit or a rectangular wave output from the second binarization circuit Either one of the signals is selectively input, and an edge detection unit that obtains an edge detection signal of the rectangular wave signal, and a pulse corresponding to the phase difference between the edge detection signal from the edge detection unit and the reproduction clock Obtaining a phase difference detection signal in which the width of A generating means for generating a raw clock; a demodulating means for demodulating an edge detection signal from the edge detecting means into reproduction data based on the reproduction clock generated by the generating means; and When the pulse width of the phase difference detection signal exceeds a predetermined value, a phase difference variation detection circuit that obtains a phase difference abnormality detection signal, and the phase difference variation detection signal is obtained from the phase difference variation detection circuit. The phase difference detection signal is applied to the second slice level of the second binarization circuit, and the phase difference variation detection circuit outputs the phase difference detection signal to the second slice level of the second binarization circuit. When obtained, a reset means for resetting the first slice level of the first binarization circuit at a predetermined synchronization signal timing for a fixed time; Te, and means for supplying select the second rectangular wave signal from the second binarizing circuit.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an optical disk apparatus according to an embodiment of the present invention will be described with reference to the drawings.
[0011]
FIG. 1 shows an optical disc apparatus. This optical disk device records data on an optical disk (DVD-RAM) 1 and reproduces data from the optical disk 1.
[0012]
This optical disk device is configured as a device that can read data not only from a DVD-RAM but also from other DVD disks and CD disks and write data to a rewritable DVD disk.
[0013]
Therefore, the optical pickup 2 has an objective lens 3 for DVD and an objective lens 4 for CD. In the optical pickup 2, DVD and CD semiconductor laser units (not shown) are provided corresponding to the DVD objective lens 3 and the CD objective lens 4, and the loaded optical disc 1 is a DVD disc. Alternatively, one of the semiconductor laser units is selected depending on whether it is a CD disk, and is energized by the laser control unit 5 to generate a laser beam having a corresponding wavelength. When one of the DVD and CD semiconductor laser units is selected and energized, the laser beam corresponding to the optical disc 1 is directed to the corresponding objective lenses 3 and 4, and the objective lenses 3 and 4 allow the optical disc 1 to be directed. To converge. Data is written to or reproduced from the optical disk 1 by the converged laser beam.
[0014]
The settings of the laser control unit 5 are set by the DVD data processing unit 6, and the settings are a reproduction mode for obtaining a reproduction signal, a recording mode for recording data, an erasing mode for erasing data, and data processing for a DVD disc. Are different between the DVD mode for executing the data processing and the CD mode for executing data processing for the CD disc. That is, in the DVD mode, a semiconductor laser unit for DVD is selected and activated, and in the CD mode, a semiconductor laser unit for CD is selected and activated. The laser beam for DVD or CD has a different level of power in each of the three modes of the reproduction mode, the recording mode and the erasing mode, and the semiconductor laser unit so that the laser beam having the power corresponding to the mode is generated. Is energized by the laser control unit 5.
[0015]
The DVD disk or CD disk is stored directly or in the disk cartridge 1a and is placed by the tray 7 so that the DVD disk 1 or CD disk is placed opposite to the DVD objective lens 3 and the CD objective lens 4. It is transported into the device. A tray motor 8 for driving the tray 7 is provided in the apparatus. The loaded DVD disk 1 or CD disk is rotatably held by a stamper 9 on a spindle motor 10 and is rotated by the spindle motor 10.
[0016]
The optical pickup 2 is placed on a feed mechanism (not shown) driven by a feed motor 11 and is moved in the radial direction of the optical disc 1 by the feed mechanism.
[0017]
The optical pickup 2 has a photodetector (not shown) for detecting the laser beam therein. This photodetector detects the laser beam reflected by the optical disc 1 and returned through the objective lenses 3 and 4. A detection signal (current signal) from the photodetector is converted into a voltage signal by a current / voltage converter (I / V) 12, and this signal is supplied to a reference amplifier (RF amplifier) 13 and a servo amplifier 14. . From the reference amplifier 13, a tracking error signal for reproducing data in the header section 51 described later and an addition signal for reproducing data in the recording area 58 are output to the DVD data processing unit 6. Servo signals (track error signal and focus signal) from the servo amplifier 14 are output to the DVD servo seek control unit 15 in the DVD mode, and are output to the CD servo seek control and CD data processing unit 16 in the CD mode.
[0018]
As a method for optically detecting the amount of focus deviation, for example, the following is available.
[0019]
[Astigmatism Method] An optical element (not shown) that generates astigmatism is arranged in the detection optical path of the laser beam reflected by the light reflecting film or the light reflecting recording film of the optical disc 1, and is placed on the photodetector. This is a method for detecting a change in the shape of the irradiated laser beam. The light detection area is divided into four diagonal lines. The focus error detection signal (focus signal) is obtained by taking the difference between the diagonal sums in the DVD servo seek control unit 15 with respect to the detection signal obtained from each detection area.
[0020]
[Knife Edge Method] This is a method of arranging a knife edge that shields a part of the laser light reflected by the optical disk 1 asymmetrically. The light detection area is divided into two, and a focus error detection signal is obtained by taking a difference between detection signals obtained from the respective detection areas.
[0021]
Usually, either the astigmatism method or the knife edge method is employed.
[0022]
The optical disc 1 has a spiral or concentric track, and information is recorded on the track. Information is reproduced or recorded / erased by tracing the focused spot along the track. In order to stably trace the focused spot along the track, it is necessary to optically detect the relative positional deviation between the track and the focused spot.
[0023]
In general, the following method is used as a method of detecting a track deviation.
[0024]
[Differential Phase Detection] The intensity distribution change on the photodetector of the laser beam reflected by the light reflecting film or the light reflecting recording film of the optical disc 1 is detected. The light detection area is divided into four diagonal lines. For the detection signals obtained from the respective detection areas, the difference between the diagonal sums is taken in the DVD servo seek control unit 15 to obtain a track error detection signal (tracking signal).
[0025]
[Push-Pull Method] Changes in the intensity distribution of the laser beam reflected by the optical disc 1 on the photodetector are detected. The light detection area is divided into two, and a track error detection signal is obtained by taking a difference between detection signals obtained from the respective detection areas.
[0026]
[Twin Spot (Twin-Spot) Method] A diffraction element is arranged in the light transmission system between the semiconductor laser element and the optical disc 1 to divide the light into a plurality of wavefronts, and the amount of reflected light of ± first-order diffracted light irradiated onto the optical disc 1 Detect changes. In addition to the light detection area for detecting the reproduction signal, a light detection area for individually detecting the reflected light amount of the + 1st order diffracted light and the reflected light amount of the −1st order diffracted light is arranged, and a track error detection signal is obtained by taking a difference between the respective detection signals. Get.
[0027]
In the DVD mode, a focus signal, a tracking signal, and a feed signal are sent from the DVD servo seek control unit 15 to the focus and tracking actuator driver and the feed motor driver 17, and the objective lens 3, 4 is subject to focus servo control by the driver 17, and Tracking servo control.
[0028]
Further, an energizing signal is supplied from the driver 17 to the feed motor 11 in accordance with the access signal, and the optical pickup 2 is transported.
[0029]
The DVD servo seek control unit 15 is controlled by the DVD data processing unit 6. For example, an access signal is supplied from the DVD data processing unit 6 to the DVD servo seek control unit 15 to generate a feed signal.
[0030]
Further, the spindle motor driver 18 and the tray motor driver 19 are controlled by a control signal from the DVD data processing unit 6, the spindle motor 10 and the tray motor 8 are energized, the spindle motor 10 is rotated at a predetermined rotational speed, and the tray motor is driven. 8 will properly control the tray.
[0031]
A reproduction signal corresponding to data in a header portion (described later) supplied to the DVD data processing unit 6 is supplied to a CPU 25 described later. Thereby, the CPU 25 judges the sector number as the address of the header portion from the reproduction signal, and compares it with the sector number as the address to access (record data or reproduce recorded data). It is like that.
[0032]
A reproduction signal corresponding to data in a recording area (described later) supplied to the DVD data processing unit 6 stores necessary data in the RAM 20, and the reproduction signal is processed by the DVD data processing unit 6 to be a RAM 21 serving as a buffer. Is supplied to the SCSI interface control unit and the CD-ROM decoder 22, and a reproduction processing signal is supplied to another device such as a personal computer via the SCSI.
[0033]
In the CD mode, the focus signal, tracking signal and feed signal are sent from the CD servo seek control and CD data processing unit 16 to the focus and tracking actuator driver and feed motor driver 17, and the objective lens 3, 4 is brought into focus servo by this driver 17. Controlled and also
Tracking servo controlled.
[0034]
Further, an energizing signal is supplied from the driver 17 to the feed motor 11 in accordance with the access signal, and the optical pickup 2 is transported. The spindle motor driver 18 and the tray motor driver 19 are controlled by the CD servo seek control and the control signal from the CD data processing unit 16, the spindle motor 10 is energized, and the spindle motor 10 is rotated at a predetermined rotational speed. Become. The reproduction signal supplied to the CD data processing unit 16 is processed by the processing unit 16 and output through the CD data output amplifier 23.
[0035]
Each unit shown in FIG. 1 is controlled by the CPU 25 in accordance with the procedure stored in the ROM 24. The RAM 26 is used as a memory for the CPU 25.
[0036]
Next, the structure of the created DVD-RAM optical disk 1 will be described.
[0037]
The optical disk 1 is composed of a disk-shaped substrate made of a transparent resin such as polycarbonate or acrylic having a thickness of 0.6 mm, a phase change recording film, a reflective film, a protective film, and a sheet or adhesive for bonding. . Grooves and header information are recorded in a concavo-convex shape on a transparent substrate, a recording film is formed on the concavo-convex surface, the concavo-convex surfaces are bonded together, and recording / reproduction can be performed on both sides.
[0038]
As shown in FIG. 2, the optical disc 1 is composed of a header portion composed of a wobbled groove for tracking in advance and a prepit (embossed pit) row indicating a track address and the like.
[0039]
In other words, the tracking groove is wobbled at a constant period in order to obtain a reference signal for data recording. At this time, the phases of the signals for wobbling the header portion and the tracking groove at a constant cycle are set to roughly match.
[0040]
In the optical disc 1, data is recorded and reproduced in units of sectors.
[0041]
The format for each sector is shown in FIG.
[0042]
In FIG. 3, one sector includes a header area (corresponding to the header portion) 27, a mirror area 28, and a recording area 29.
[0043]
The channel bits recorded in the sector are in the form of 8-16 code modulation of 8 bits of data into 16 bits of channel bits.
[0044]
The header area 27 is an area where predetermined data is recorded when the optical disc 1 is manufactured. The header area 27 includes four header 1 areas, a header 2 area, a header 3 area, and a header 4 area.
[0045]
The header 1 area to the header 4 area include a synchronization code portion VFO (Variable Frequency Oscillator), an address mark AM (Address Mark), an address portion PID (Position Identifier), an error detection code IED (ID Error Detection Code), and a postamble PA ( Postambles).
[0046]
The mirror area 28 is used for offset correction of a tracking error signal, generation of a land / groove switching signal timing, and the like.
[0047]
The recording area 29 includes a gap area, a guard 1 area, a VFO 3 area, a pre-synchronous code (PS) area, a data area, a postamble 3 (PA 3) area, a guard 2 area, and a buffer area.
[0048]
The data area is an area composed of a data ID, a data ID error correction code IED (Data ID Error Detection Code), a synchronization code, an ECC (Error Correction Code), an EDC (Error Detection Code), user data, and the like.
[0049]
As shown in FIG. 4, each sector is composed of 26 frames from the 0th frame to the 25th frame, and the synchronization code (frame synchronization signal) assigned to each frame specifies the frame number. Specific code and a common code common to each frame.
[0050]
In the DVD data processing unit 6, as shown in FIG. 1, a data reproduction circuit 30 for reproducing data recorded on the optical disk 1 by a reproduction signal from the RF amplifier 13 is provided.
[0051]
As shown in FIG. 5, the data reproduction circuit 30 includes binarization circuits 31 and 32, a switching circuit 33, a PLL circuit 34, a shift register 35, a demodulation circuit 36, a synchronization code detection circuit 37, and a phase difference variation detection circuit. 38, a switching signal generation circuit 39.
[0052]
The binarization circuit 31 binarizes the reproduced RF signal obtained by waveform equalizing the waveform of the addition signal from the RF amplifier 13 by a waveform equalization circuit (not shown) to obtain an 8-16 signal. DSV (Digital Sum (Value) is 0, that is, the binarized slice level is changed so that the time of the high level and the low level of the binarized signal becomes equal in the integrated period, and binarized by following the fluctuation of the input signal It is.
[0053]
The binarization circuit 31 is reset by a reset signal (switching signal) from the switching signal generation circuit 39 (reset function), so that the slice level (binarization level) is set to an initial value. Is to prevent divergence. The reset signal from the switching signal generation circuit 39 is supplied at the time of detecting an abnormality in which the phase difference fluctuation amount of the PLL circuit 34 exceeds a predetermined value and at the timing when the next synchronization code is detected. The reset function works at the timing.
[0054]
The binarization circuit 32 is provided in parallel with the binarization circuit 31, and based on the phase difference of the PLL, a reproduced RF signal obtained by equalizing the waveform of the addition signal from the RF amplifier 13 by a waveform equalization circuit (not shown). In the state where the PLL loop is operating almost correctly, the imbalance between the charge signal and the discharge signal is fed back to the binarization level with respect to fluctuations in the data signal sufficiently slower than the PLL loop. Thus, correct binarized data is generated. Actually, binarization is started at the same slice level as that immediately before the binarization signal is cut by the binarization circuit 31, and the phase difference fluctuation amount is fed back (added) to this value (slice level). It has come to go.
[0055]
As a result, fluctuations in a wide range and low in frequency that cannot be followed by the PLL are followed.
[0056]
The binarization circuit 32 feeds back the phase difference fluctuation amount of the PLL circuit 34 to the binarized slice level. This method has several stable points and cannot always be used. However, it is effective when the PLL by the PLL circuit 34 is operating normally by binarization by DSV, which is almost stable in advance. It is.
[0057]
The binarization circuit 32 is used when retrying when reproduction cannot be performed even if the binarization circuit 31 is reset by the reset function. Regardless of the amount of the phase difference, the following binarization circuit 32 is used. The binarization is performed at the timing when the synchronization code at the beginning of the sector is detected, that is, at the beginning of the data.
[0058]
The binarized output from the binarizing circuit 31 and the binarized output from the binarizing circuit 32 are supplied to the PLL circuit 34 via the switching circuit 33.
[0059]
The switching circuit 33 outputs the binarized output from the binarizing circuit 31 to the PLL circuit 34 or the binarized output from the binarizing circuit 32 according to the switching signal from the switching signal generating circuit 39. Is output to the PLL circuit 34.
[0060]
The PLL circuit 34 generates a channel clock and channel data as a PLL clock synchronized with the binarized output from the binarizing circuit 31 or the binarizing circuit 32. The channel clock output from the PLL circuit 34 is supplied to the shift register 35, the demodulation circuit 36, and the synchronization code detection circuit 37, the channel data is supplied to the shift register 35, and a phase difference detection signal from a low-pass filter described later is output. This is supplied to the phase difference variation detection circuit 38.
[0061]
The shift register 35 converts the supplied channel data into 16-bit parallel data and outputs it. The 16-bit channel data from the shift register 35 is supplied to a demodulation circuit 36 and a synchronization code detection circuit 37.
[0062]
The demodulating circuit 36 outputs, as ROM output data, data stored at an address corresponding to 16-bit address data from the shift register 35 when a word boundary signal from a word boundary counter (not shown) is supplied. A ROM (not shown) and parallel-serial that converts the demodulated data as ROM output data from the demodulating ROM into serial data according to the data clock generated by dividing the channel clock from the PLL circuit 34 and outputs the data. It comprises a conversion unit (not shown).
[0063]
This ROM output data is data that is demodulated based on a predetermined (8, 16) code conversion rule corresponding to the address data, that is, 16 channel bits are demodulated to 8 bit data.
[0064]
The synchronization code detection circuit 37 includes a byte counter and a comparator. The synchronization code detection circuit 37 counts the number of bytes with reference to the header detection signal from the CPU 25, and from the PLL circuit 34 while corresponding to the data area according to the count value. Is compared with whether or not the 16-bit channel data from the shift register 35 matches the 16-bit synchronization code pattern (common code pattern). A code detection signal is output to the CPU 25.
[0065]
The phase difference variation detection circuit 38 detects a phase difference abnormality when the width of the phase difference detection signal exceeds a predetermined value based on a phase difference detection signal from a low pass filter (described later) in the PLL circuit 34. The signal is output to the switching signal generation circuit 39.
[0066]
The switching signal generation circuit 39 outputs a switching signal as a reset signal to the binarization circuit 31 and outputs a switching signal to the changeover switch 33 based on a control signal from the CPU 24.
[0067]
For example, the reset signal to the binarization circuit 31 is output at the time of detecting an abnormality in which the phase difference fluctuation amount of the PLL circuit 34 exceeds a predetermined value and at the timing when the next synchronization code is detected. In other words, a phase difference abnormality detection signal is supplied from the phase difference variation detection circuit 38, and is output at a timing at which a control signal corresponding to the synchronization code detection timing signal from the CPU 24 is supplied. The time for which the reset signal is output is a fixed time.
[0068]
The changeover signal to the changeover switch 33 is the same as the synchronization code at the beginning of the next sector from the CPU 24 when retrying when the binarization circuit 31 is reset by the reset function and reproduction cannot be performed. The control signal corresponding to the detected timing signal, that is, the control signal corresponding to the first timing signal of the data is output at the timing when it is supplied.
[0069]
The binarization circuit 31 binarizes the reproduction signal from the RF amplifier 13 with the slice level as a value obtained by adding a signal fed back from the comparator via a low-pass filter to the binarization initial level. The reset switch is provided between the low-pass filter and the adding unit.
[0070]
Actually, as shown in FIG. 1, it is composed of a comparator 41, a charge pump 42, changeover switches 43 and 44, an inverter 45, a capacitor 46 and a buffer 47.
[0071]
Thus, when the reset signal is at a low level, the changeover switch 43 is closed and the changeover switch 44 is open, and the binarized signal from the comparator 41 is passed through the charge pump 42 and the changeover switch 43 to the capacitor 46. , The value obtained by adding the binarized signal from the comparator 41 to the binarized initial level Vref is supplied to the inverting input terminal of the comparator 41 via the buffer 47 as a slice level.
[0072]
When the reset signal is at a high level (at the time of reset), the changeover switch 43 is open and the changeover switch 44 is closed, and the binarized initial level Vref is set as a slice level via the buffer 47. It is supplied to the inverting input terminal of the comparator 41.
[0073]
  When the phase difference abnormality detection signal is not supplied, the binarization circuit 32 feeds back the reproduction signal from the RF amplifier 13 to the initial binarization level from the comparator via a low-pass filter. The binarization is performed with the value obtained by adding the signals to be sliced as the slice level, and the phase difference abnormality detection signal is supplied.Not inIn this case, a value obtained by adding a signal obtained by passing the phase difference detection signal from the PLL circuit 34 through the low-pass filter to the initial level of binarization with respect to the reproduction signal from the RF amplifier 13 is set to 2 as a slice level. It is a valuation.
[0074]
Actually, as shown in FIG. 1, it is composed of a comparator 51, a changeover switch 52, a charge pump 53, a capacitor 54, and a buffer 46.
[0075]
Thereby, when the phase difference abnormality detection signal is not supplied, the changeover switch 52 is switched to the L side, and the binarized signal from the comparator 51 is passed through the changeover switch 52 and the charge pump 53 to the capacitor 54. The value obtained by adding the binarized signal from the comparator 51 to the binarized initial level Vref is supplied to the inverting input terminal of the comparator 51 via the buffer 55 as a slice level.
[0076]
When the phase difference abnormality detection signal is supplied, the changeover switch 52 is switched to the H side, and the phase difference detection signal from the low pass filter 63 of the PLL circuit 34 is changed to the changeover switch 52 and the charge pump 53. Is supplied to the capacitor 54 through the buffer 54, and a value obtained by adding the phase difference detection signal from the low-pass filter 63 to the binarized initial level Vref is supplied to the inverting input terminal of the comparator 51 through the buffer 55 as a slice level. Is done.
[0077]
As shown in FIG. 6, the charge pumps 42 and 53 include a switch that is turned on when the input signal is at a high level, a switch that is turned on when the input signal is at a low level, two current sources, and a capacitor. Has been.
[0078]
The PLL circuit 34 includes an edge detection circuit 61, a phase comparator 62, a low-pass filter 63, and a voltage controlled oscillator (VOC) 64.
[0079]
The edge detection circuit 61 is a circuit for detecting the edge of the signal waveform from the binarization circuit 31 or 32. The edge detection signal is output to the phase comparator 62 and also output to the shift register 35 as channel data. Is done.
[0080]
The phase comparator 62 is a lock-in type phase comparator, which compares the phase of the edge detection signal from the edge detection circuit 61 and the clock signal from the voltage controlled oscillator 64 and is proportional to the compared phase difference. A signal having a pulse width is output from the charge signal and discharge charge signal. The clock signal from the phase comparator 62 is output to the synchronous low-pass filter 63.
[0081]
The low-pass filter 63 subtracts the charge signal from the discharge signal from the phase comparator 62, outputs a signal obtained by integrating the subtraction result to the voltage controlled oscillator (VOC) 64, and the integrated signal detects the phase difference. The signal is output to the phase difference variation detection circuit 38 and the binarization circuit 32 as a signal.
[0082]
A voltage-controlled oscillator (VCO) 64 outputs a binary clock signal (channel clock) having a frequency proportional to the voltage value (analog value) of the signal supplied from the low-pass filter 63.
[0083]
The channel clock of the voltage controlled oscillator 64 is output to the phase comparator 62 and also output to the shift register 35, the demodulation circuit 36, and the synchronization code detection circuit 37.
[0084]
Next, in the configuration as described above, the PLL operation will be described using the signal waveforms shown in FIGS.
[0085]
That is, the reproduction signal shown in FIG. 7A is binarized by the binarization circuit 31, and then edge detection is performed by the edge detection circuit 61, whereby the channel data shown in FIG. The channel data signal shown in FIG. This signal indicates a change in channel data by changing the binarized signal of the reproduction signal to a high level for one clock.
[0086]
Then, as shown in FIGS. 7D, 7E and 7F, the phase comparator 62 generates, as a charge signal, a signal having a high level from the fall of the channel data signal to the next clock timing. A pulse of 0.5T (fixed) (T is the period of the channel clock) is generated as a discharge signal from the fall timing of the next channel clock after the fall of the channel data signal.
[0087]
The pulse width of the charge signal changes by 0.5T ± 0.5T (T is the period of the channel clock) due to the jitter of the reproduction signal.
[0088]
Here, the value obtained by integrating the pulse width of the charge signal generated by the phase comparator 62 and the discharge signal by the low-pass filter 63 is compared, and the output of the VCO 64 is changed so that the charge signal is always 0.5T. Yes.
[0089]
In such a state, processing when a reproduction signal for a data pattern of DSV ≠ 0 is supplied will be described with reference to signal waveforms shown in FIGS.
[0090]
That is, the slice level supplied to the inverting input terminal (−) of the comparator 41 gradually increases as shown by a solid line in FIG. 8A, that is, moves away from the original slice level shown by a broken line. Then, the binarized signal output from the comparator 41 is greatly deviated from the original timing indicated by the broken line, as indicated by the solid line in FIG. As a result, the width of the phase difference detection signal output from the low-pass filter 63 gradually increases as shown in FIG. When the width of the phase difference detection signal becomes equal to or greater than a specified value, the phase difference variation detection circuit 38 outputs a phase difference abnormality detection signal to the switching signal generation circuit 39.
[0091]
Thereafter, as shown in FIG. 8D, the switching signal generation circuit 39 binarizes the reset signal (high level) at the timing when the control signal corresponding to the synchronization code detection timing signal from the CPU 24 is supplied. To 31. By this reset signal, the changeover switch 43 is opened, the changeover switch 44 is closed, and the value of the binarized initial level Vref is supplied to the inverting input terminal of the comparator 41 via the buffer 47 as the slice level.
[0092]
As a result, the slice level supplied to the inverting input terminal (−) of the comparator 41 is quickly returned to the initial value by the reset as shown by the solid line in FIG. 8A, and this slice level does not diverge. Like that.
[0093]
Thereafter, after a fixed time elapses, the reset signal becomes a low level, and the state returns to the state where the normal binarization signal in which the changeover switch 43 is closed and the changeover switch 44 is open is fed back.
[0094]
Further, as described above, when performing the retry when the recorded data cannot be reproduced even if the binarization circuit 31 is reset by the reset function, the CPU 24 performs the first synchronization for the next sector. A control signal is output to the switching signal generation circuit 39 at the timing when the code is detected. Then, the switch signal generation circuit 39 switches the switch 33 to the binarization circuit 32 side by the switch signal. At this time, the changeover switch 52 is on the L side.
[0095]
In such a state, processing when a reproduction signal for a data pattern of DSV ≠ 0 is supplied will be described with reference to signal waveforms shown in FIGS.
[0096]
That is, the slice level supplied to the inverting input terminal (−) of the comparator 51 gradually increases as shown by the solid line in FIG. 9A, that is, moves away from the original slice level shown by the broken line. Then, the binarized signal output from the comparator 51 deviates significantly from the original timing indicated by the broken line, as indicated by the solid line in FIG. 9B. As a result, the width of the phase difference detection signal output from the low-pass filter 63 gradually increases as shown in FIG. When the width of the phase difference detection signal is equal to or greater than a specified value, as shown in FIG. 9D, a phase difference abnormality detection signal (high level) is output from the phase difference variation detection circuit 38, and the changeover switch 52 is switched to the H side.
[0097]
When the changeover switch 52 is switched to the H side, the phase difference detection signal output from the low-pass filter 63 via the charge pump 53 to the slice level before the changeover switch 52 held by the capacitor 54 is changed. Is added to the inverting input terminal of the comparator 51 through the buffer 55 as a slice level.
[0098]
As a result, the slice level supplied to the inverting input terminal (−) of the comparator 51 is made appropriate as shown by the solid line in FIG.
[0099]
After that, when the width of the phase difference detection signal is less than the specified value that is the reference for restoration,
Alternatively, after the fixed time has elapsed, the changeover switch 33 is switched to the binarization circuit 31 side by the changeover signal from the changeover signal generation circuit 39 to the changeover switch 33, whereby the binary from the normal binarization circuit 31 is obtained. Return to the processing state using the digitized signal. The specified value that serves as a reference for the return does not necessarily match the specified value when an abnormality in phase difference is detected. For example, the prescribed value t1 when detecting an abnormality in the phase difference is twice the prescribed value t2 that is a reference for restoration. (T1 = 2 · t2)
As described above, when the width of the phase difference between the charge signal and the discharge signal in the PLL circuit 34 exceeds a specified value, the feedback system of the binarization circuit 31 is reset to slice the binarization circuit 31. The level is set to an initial value, or the slice level of the binarization circuit 32 is corrected to an optimum value by the phase difference.
[0100]
As a result, even if the data pattern to be reproduced is a special pattern in which the DSV does not become zero, the data can be reproduced.
[0101]
In the above-described embodiment, the case where the phase difference detection signal becomes a low level when the width of the phase difference detection signal is equal to or less than a specified value as a reference for restoration or after a fixed time has elapsed has been described. However, the present invention is not limited to this, and as shown in FIG. 10D, the changeover switch 33 is switched to the binarization circuit 31 side by the changeover signal from the changeover signal generation circuit 39 to the changeover switch 33 at the end position of the sector. Accordingly, the binarization by the binarization circuit 32 may be continued until the end of the sector, and the next sector may return to the processing state using the binarization signal from the normal binarization circuit 31. In this case, the processes in FIGS. 10A to 10C are the same as those in FIGS. 9A to 9C.
[0102]
In the above embodiment, the case where the two binarization circuits 31 and 32 are used has been described. However, even when only the binarization circuit 31 excluding the binarization circuit 32 is provided, good. In this case, besides the binarization circuit 32, the changeover switch 33 is removed and the binarization signal from the binarization circuit 31 is output to the PLL circuit 34 as it is. Further, a signal line for supplying a reproduction signal to the comparator 51 of the binarization circuit 32, a signal line from the comparator 51 to the changeover switch 33, a signal line from the low pass filter 63 to the changeover switch 52, and a phase difference variation detection circuit 38. To the change-over switch 52 is removed. In this embodiment, the reset process for the binarization circuit 31 described with reference to FIGS. 8A to 8D is performed.
[0103]
In this case, when the width of the phase difference between the charge signal and the discharge signal in the PLL circuit 34 exceeds a specified value, the feedback system of the binarization circuit 31 is reset and the slice level of the binarization circuit 31 is set. This is an initial value.
[0104]
As a result, even if the data pattern to be reproduced is a special pattern in which the DSV does not become zero, the data can be reproduced.
[0105]
In the above embodiment, the case where the slice levels are corrected for each of the two binarization circuits 31 and 32 has been described.
Normally, the binarization signal from the binarization circuit 31 may be used, and the binarization circuit 32 may be used when the phase difference detection signal is detected. In this case, in FIG.
The changeover switches 43 and 44 and the inverter 45 are removed from the binarization circuit 31, the charge pump 42 and the buffer 47 are directly connected, and the signal line from the changeover signal generation circuit 39 to the changeover switch 43 and the inverter 45 is removed. .
[0106]
In this embodiment, as described with reference to FIGS. 9A to 9D, when the width of the phase difference between the charge signal and the discharge signal in the PLL circuit 34 exceeds a specified value, the selector switch 33 is switched. The binarization signal from the binarization circuit 32 is supplied to the PLL circuit 36, and the changeover switch 52 is further switched to change the slice level of the binarization circuit 32 from the low-pass filter 63 of the PLL circuit 34. The correction is made by the phase difference detection signal.
[0107]
As a result, even if the data pattern to be reproduced is a special pattern in which the DSV does not become zero, the data can be reproduced.
[0108]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to provide an optical disc apparatus capable of correctly reproducing data when a special data pattern is reproduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a schematic configuration of an optical disc apparatus according to an embodiment of the present invention.
FIG. 2 is a plan view showing a schematic configuration of an optical disc.
FIG. 3 is a diagram showing a sector format.
FIG. 4 is a diagram for explaining the configuration of each sector;
FIG. 5 is a block diagram showing a schematic configuration of a data reproduction circuit.
FIG. 6 is a block diagram illustrating a configuration of a charge pump.
FIG. 7 is a signal waveform diagram for explaining a PLL operation.
FIG. 8 is a signal waveform diagram for explaining processing when a reproduction signal for a data pattern of DSV ≠ 0 is supplied.
FIG. 9 is a signal waveform diagram for explaining processing when a reproduction signal for a data pattern of DSV ≠ 0 is supplied.
FIG. 10 is a signal waveform diagram for explaining processing when a reproduction signal for a data pattern of DSV ≠ 0 is supplied.
[Explanation of symbols]
30. Data reproduction circuit
31, 32... Binarization circuit
33 ... changeover switch
34 ... PLL circuit
36. Demodulator circuit
38 ... Phase difference variation detection circuit
39. Switching signal generation circuit

Claims (1)

In an optical disc apparatus for reproducing data recorded on an optical disc,
An optical head for outputting a reproduction signal from the optical disc;
The reproduction signal is compared with a first slice level and converted into a first rectangular wave signal and output. When not reset, the first slice level is generated using the first rectangular wave signal. A first binarization circuit,
The reproduction signal is compared with a second slice level and converted into a second rectangular wave signal and output. When not reset, the second slice level is generated using the second rectangular wave signal. A second binarization circuit,
Either the rectangular wave signal output from the first binarization circuit or the rectangular wave signal output from the second binarization circuit is selectively input, and edge detection of the rectangular wave signal is performed. Edge detection means for obtaining a signal;
A phase difference detection signal whose pulse width changes according to the phase difference between the edge detection signal from the edge detection means and the reproduction clock, and a generation means for generating the reproduction clock;
Demodulating means for demodulating an edge detection signal from the edge detection means into reproduction data based on the reproduction clock generated by the generation means;
A phase difference variation detection circuit for obtaining a phase difference abnormality detection signal when a pulse width of the phase difference detection signal from the generation unit is equal to or greater than a predetermined value;
Reset means for adding the phase difference detection signal to the second slice level of the second binarization circuit when the phase difference abnormality detection signal is obtained from the phase difference variation detection circuit; ,
Reset means for resetting the first slice level of the first binarization circuit for a fixed time at a predetermined synchronization signal timing when the phase difference abnormality detection signal is obtained from the phase difference variation detection circuit;
Means for selecting and supplying a second rectangular wave signal from the second binarization circuit to the edge detection means at the time of retry ;
An optical disc apparatus comprising:

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