JPH1011360A - Cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optmize access width regardless of an instruction when data including monotonous bit information is read and written and to save power consumption by setting the contents of the state flag of a flag possessing part to a new value at the time of refilling and also writing only a part of 0 and 1 mixing data within required data in a data storage part. SOLUTION: A tag possessing part 202 and the flag possessing part 1 are accessed concerning a selected tag and a state flag in order to designate an index and the contents of the state flag read from the flag possessing part 1 are transmitted to an encoder 6. Then, at the time of tag checking and hitting, the new state flag is written in an area which is designated by the applying index and writing is executed only to a cell which executes updating to data being 'whole are not 0 nor 1'. In the meantime, at the time of missing, an operation becomes the refilling one, refill data is stored in the latch of a latch circuit 20A with a 0-string/1-string restoring function and updating is processed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory mounted on a microprocessor or the like.

[0002]

2. Description of the Related Art A cache memory mounted on a microprocessor is located between a CPU and a main memory (main storage device). The cache memory transfers frequently accessed information from the main memory to the main memory. It is known as a high-speed buffer storage device for reading and writing data.

An example will be described in which such a cache memory is constituted by storage means having two complementary bit lines for each bit, for example, a static RAM (hereinafter simply referred to as SRAM).

FIG. 6 is a diagram showing a configuration example of one bit of the SRAM, and FIG. 7 is a waveform diagram showing an operation of one bit of the SRAM shown in FIG.

In this SRAM, in both reading and writing, first, the precharge and equalize enable PRE becomes "L" level,
The channel MOS transistors (hereinafter, referred to as P-MOS) 101, 102, and 103 are turned on, and the bit line B
It and Bit bars are precharged to the power supply potential Vcc. At this time, the word line WD is at the “L” level, and an N-channel MOS transistor (hereinafter referred to as an N-MOS
) 104 and 105 are off, and the potential of the bit lines Bit and Bit bar is not transmitted to the flip-flop 106.

Next, the enable PRE goes to "H" level, the P-MOSs 101, 102 and 103 are turned off, and the bit lines Bit and Bit bar are kept at the power supply potential Vcc. As described above, the precharge operation is inevitably performed in both read / write operations (see FIG. 7).

At the time of reading, thereafter, the word line WD goes to "H" level, the N-MOSs 104 and 105 are turned on, and the potential of the flip-flop 106 is set to the bit line Bit,
It is transmitted to the Bit bar. At this time, the bit lines Bit, B
The change in the potential of the it bar is accelerated by the reading means (sense amplifier) 107. Bit line Bit, Bit
Depending on the contents of the flip-flop 106, one of the bars is always at "H" level and the other is at "L" level.
Therefore, one of the bit lines Bit and Bit bar always transitions from the “H” level to the “L” level. Note that the example shown in FIG. 7 shows a case where the bit line Bit side is at “L” level and the bit line Bit bar side is at “H” level.

At the time of writing, bit lines Bit, Bit
After the bar is precharged (at this time, the P-MOS 101, 1
02 and 103 are off), writing means (write amplifier)
108 supplies data to be written to the bit lines Bit and Bit bar. In the write data, one of the bit lines Bit and Bit bar is always at "H" level and the other is at "L" level. Next, the word line WD goes to “H” level, and the N-MOSs 104 and 10
5 is turned on, and the data on the bit lines Bit and Bit bar is transmitted to the flip-flop 106.

At this time, write acceleration is performed by the write amplifier 107. Also at the time of writing, one of the bit lines always transitions from "H" level to "L" level. This is because the bit lines Bit and Bit bar are constituted by two complementary lines, and have no relation to the data contents.

As described above, in the case of the SRAM, in the storage means in which each bit has two complementary bit lines, one of the two bit lines of the accessed bit is used for both reading and writing. From “H” level to “L”
Since the transition to the level is made, the transition of the bit line of the corresponding bit cannot be stopped when the access is performed. In particular, since a configuration in which many flip-flops are usually connected to one bit line is used, the load capacity of the bit line becomes very large. Therefore, the transition of the bit line is accompanied by charging / discharging of a large load capacity, which is one of the causes for increasing the power of the cache memory including such storage means.

FIG. 8 is a block diagram showing a configuration example of a conventional cache memory (first conventional example).

In this cache memory, addresses are decomposed into a tag section 200a, an index section 200b, and an offset section 200c. The tag section 200a indicates a position in the main memory, the index section 200b indicates designation of a line, and the offset section 200c indicates a data position within the line. The index unit 200b is a decoder 2
01, and designates one line of the tag holding unit 202 and the memory cell array 203.

At the time of reading, generally, a line of the selected cell array 203 is accessed with a line size width, and the read data enters the latch 204. The offset is decoded by the decoder 205 and the multiplexer (m
ux) 206, reads out the data designated by the offset from the data in the latch 204,
Send to The tag is compared in the comparator 208 with the tag designated by the program and the tag held in the cache memory, and a hit / miss determination is made. If they match, data is output from the port 207 to the external bus 209 as a hit.

On the other hand, in the case of writing, the data input to the write port 207 is transferred to the decoder 2 with the offset.
05 through the demultiplexer (de
mux) 206, and enters the area of the latch 204 specified by the offset. In the case of a hit determination by the hit check by the comparator 208, the data of the latch 204 is written to the memory cell array 203. At this time, for a portion where data is not stored in the latch 204, control is performed to set the corresponding bit of the memory cell array 203 to a write-inhibited state, so that only data sent from the write port 207 to the latch 204 is stored in the memory cell array 20.
3 is written.

When the hit check by the comparator 208 determines a miss, refilling is started. At the time of refilling, data of a line size width is sequentially sent from the main memory to the latch 204 via the bus 209 and the write port 207. When the data is stored in the latch 204, writing to the memory cell array 203 is performed. Access is performed with a bus width at the time of writing and with a line size at the time of refilling.

As described above, in the configuration of the cache memory, the memory cell array 203 is accessed uniformly in the line size at the time of reading and refilling, and uniformly in the unit of the bus width at the time of writing.

On the other hand, FIG. 9 shows an example of a cache memory which is accessed with a bus width at the time of reading, writing and refilling (second conventional example). Note that the cache memory shown in FIG. 8 has a conventional configuration corresponding to an embodiment to be described later, whereas that shown in FIG. 9 is a cache memory having a generally known configuration.

300a, 300b, 300c in FIG.
Are the tag section 200a and the index section 200b in FIG.
And the offset unit 200c, respectively.
8, reference numeral 01 denotes the decoder 201, reference numeral 302 denotes the tag holding unit 202, reference numeral 303 denotes the memory cell array 203, reference numeral 304
Are components corresponding to the decoders 205 and 305 and the multiplexer / demultiplexer (mux / demux) 206, respectively.

However, unlike the decoder 205 of FIG. 8, the decoder 304 not only outputs the signal S300 corresponding to the offset select signal S200, but also supplies the decoded result of the offset to the memory cell array 203.
That is, the offset is decoded by the decoder 304 to indicate a designated position in the memory cell array 303.

The memory cell array 303 and the multiplexer / demultiplexer 305 are connected not by a line size but by a bus width, and elements corresponding to the latch 204 in FIG. 8 are removed. The multiplexer / demultiplexer 305 is connected to the bus 308 via the sense amplifier 307, and
9 is connected to the bus 310. This bus 31
To 0, a latch 311 for supplying data to the memory cell array 303 is connected.

At the time of reading, the decoder 304 outputs the result of offset decoding to the multiplexer 305.
Not only is supplied to the memory cell array 303 but also a read position (bus width) in a line is specified. As a result, only that position is activated and multiplexer 305
Is sent to the sense amplifier 307 and latched. Note that the sense amplifier 307 is configured by a flip-flop whose operation can be turned on / off, and the sense operation itself becomes a data latch.

On the other hand, at the time of writing, write data passes through the demultiplexer 305 and the memory cell array 30
3 and is written by the write operation of the write amplifier 309. At this time, the decoding result of the offset from the decoder 304 is
05 and the memory cell array 303, and the write position is activated by the bus width in the memory cell array 303. The operation itself in which the offset specifies the position of the memory cell array 303 gives the write enable.

The operation at the time of refilling is the same as the operation at the time of writing. However, since data is exchanged with the memory cell array 303 by the bus width, the writing operation is performed until the entire line is refilled, and the line width is gradually reduced by the bus width. This is repeated the number of times (line width / bus width).

[0024]

However, as the bus width of the microprocessor increases, data handled by the cache memory may include a monotonic "0" column or a monotonic "1" column. More. Although the data happens to have such a value, it is particularly remarkable when software does not need to use up the bus width of the processor.

In such a case, for example, a monotonous sequence of 1s or a monotone sequence of 0s is placed in the upper several bits. Bits that are not necessary for the data are subjected to sign extension or 0 extension, and are filled with "0" columns or "1" columns so that no inconsistency occurs in the operation of the processor.

This will be described more specifically. Assuming that the bus width of the microprocessor is, for example, 64 bits, there are many cases where all 64 bits are not actually used. That is, the data used for the convenience of the program is 8 bits,
This is because there are many cases such as 16 bits and 32 bits. In these cases, sign extension or 0
For example, "all 0s" or "all 1s" are stored in portions of the 64-bit data width prepared by the processor that are not used by the program. Also, even if the software uses all 64 bits,
Data in which all parts of the bit string are “0” or “1” should appear.

In the conventional cache memory, all bits are accessed for such data. That is, in the first conventional example (FIG. 8), all the bits of the line size are accessed at the time of reading or refilling, and all the bits of the bus width are accessed at the time of writing. In the second conventional example (FIG. 9), At the time of reading, writing and refilling, all bits of the bus width are accessed. As a result, there is a problem that power consumption cannot be reduced even when reading / writing data including monotonous bit information such as a monotonic “0” column and a monotonic “1” column.

From the viewpoint of reducing power consumption at the time of accessing the cache memory, for example, a method of accessing the memory cell array in byte units at the time of reading (the configuration is the same as that shown in FIG. 9), a specific byte of the memory cell array, Conventionally, a method of writing data only to a memory cell, a method of writing data to a memory cell array in byte units, and the like have been known.

The above method is performed only when the access width is specified to be smaller than the bus width in an instruction issued to the processor such as “load byte” or “load half word”. Bits can be reduced. Further, in the above method, for example, when a cache line is 32 bytes in a 64-bit processor, "store"
One byte is rewritten by the "byte" instruction, and the remaining 31 bytes remain unchanged. As an example of the cache operation of this method, there is a “read modify write” in which data is read once with a bus width, a desired one byte is replaced with new data, and the data is written into a cache memory with a bus width. However, this is an operation when the address specification to be sent to the cache memory is in the unit of the bus width. In the above method, the power consumption is lower than the bus width access, which is performed at the time of an instruction such as “store byte”.

However, in each of these methods,
The power consumption cannot be reduced by optimizing the access width based on the content of the data regardless of the instruction.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An object of the present invention is to optimize an access width independently of an instruction when reading and writing data including monotonous bit information. It is an object of the present invention to provide a cache memory which can be reduced in power consumption. Another object is to provide a cache memory capable of reducing the above power consumption while suppressing an increase in circuit scale. Still another object is to provide a cache memory capable of reducing the power consumption while increasing the speed.

[0032]

In order to achieve the above object, a first aspect of the present invention is characterized in that the memory cell comprises a plurality of lines each having a memory cell for each bit, and each of the memory cells has two lines for each bit. A data storage unit connected to a complementary bit line for selectively reading / writing data from / to the memory cell through the bit line, and a tag holding a tag indicating a position in an external main storage device And a hit judging unit for judging hit / hit / miss by comparing the match / mismatch between the tag in the tag holding unit and the tag specified by the program, and when the hit is judged by the judging unit, At the time of data reading, read out predetermined data from the data storage unit to the outside, and at the time of data writing, write externally written data to the data storage unit,
When a hit / miss determination is made by the determination unit, in the cache memory that performs refilling for writing required data from the main storage device to the data storage unit, each line in the data storage unit is set to N (a positive integer). And the memory cell data of each block is all 0 data, all 1 data, or other 0 data.
And a flag holding unit for holding a state flag representing the content of 1 mixed data for each line, and when reading the data, refer to the contents of the state flag in the flag holding unit corresponding to the read line, Only the block storing the mixed data of 0 and 1 among the blocks in the read line is accessed, and a 0 data string or 1 data string corresponding to the all 0 data or the all 1 data is read from the read data. In addition, at the time of data writing, the content of the status flag of the flag holding unit is set to a new value based on the content of the status flag in the flag holding unit corresponding to the write destination line and the content of the write data. At the same time, the portion of the write data which is a mixture of 0 and 1 data is At the time of the refill, the content of the status flag of the flag holding unit is set to a new value based on the content of the required data to be written, and a portion of only the mixed data of 0 and 1 of the required data is written. Is written in the data storage unit.

According to the first aspect, of the N blocks on each line, a block composed of all 0 data and a block composed of all 1 data are not accessed. That is, the access itself is stopped for the monotonic 0 data column and the monotonic 1 data column,
Reduce power consumption without swinging bit lines. At the time of data reading, the block to be accessed is limited by the contents of the status flag. At the time of data writing and refilling, only the "0 and 1 mixed data" portion of the write data is written, and the contents of the state flag are rewritten by the contents of the write data and the contents of the original state flag.

A second aspect of the present invention is characterized in that the memory cell is constituted by a plurality of lines each having a memory cell for each bit, and each of the memory cells is connected to two complementary bit lines for each bit. A data storage unit for selectively reading / writing data to / from the memory cell, a tag holding unit holding a tag indicating a position in an external main storage device, a tag in the tag holding unit and a program designation A hit judging unit for judging hit / hit / miss by comparing match / mismatch with the tag, and when a hit is judged by the judging unit, predetermined data is sent from the data storage unit to the outside at the time of data reading. In addition to reading, when writing data, external write data is written to the data storage unit, and when a hit / miss determination is made by the determination unit, the data is read from the main storage device. In the cache memory to perform the refill writing the required data to the data storage unit, the respective lines in the data storage unit N (a positive integer)
And a status flag indicating that the memory cell data in less than N of the predetermined blocks is all 0 data, all 1 data, or other mixed data of 0 and 1 is provided for each line. A flag holding unit is provided, and at the time of reading the data,
Referring to the contents of the status flag in the flag holding unit corresponding to the read line, access is made to only the block storing the 0 and 1 mixed data among the predetermined blocks in the read line, and the read data of the predetermined block is read. In response to the above, all the 0 data or all the 1 data are supplemented with the 0 data string or the 1 data string and read out to the outside, and at the time of writing the data, the contents of the status flag in the flag holding unit corresponding to the write destination line And setting the content of the status flag of the flag holding unit to a new value based on and the content of the write data for the predetermined block of the write destination line,
A portion of only the mixed data of 0 and 1 in the write data for the predetermined block of the write destination line is written to the predetermined block, and at the time of the refill, the flag holding unit is set based on the content of the required data to be written to the predetermined block. Is set to a new value, and a portion of only the mixed data of 0 and 1 of the required data is written to the predetermined block.

According to the second aspect, the same operation and effect as those of the first aspect can be obtained only for a predetermined block out of N blocks formed by dividing each line.

According to a third aspect of the present invention, in the first and second aspects, a line size of the plurality of lines is equal to a bus width of an external bus.
The content of the status flag of the flag holding unit is set to a new value based on the content of the write data without decoding the content of the status flag of the write destination line.

According to the third aspect, at the time of writing data, it is not necessary to decode the contents of the status flag of the write destination line, so that the configuration is simplified and high-speed operation is possible.

According to a fourth aspect of the present invention, in the first to third aspects, the content represented by the status flag is set such that all data in the memory cells in each block is 0 data or other data, or All data is one data or other data.

According to the fourth aspect, the number of bits of the status flag can be reduced. Furthermore, the status flag is 1
Since the number of bits is the same as the number of divisions of the block per line, not only the configuration is simplified, but also at the time of writing, the access width to the status flag can be limited to the flag width corresponding to the write data width.

According to a fifth aspect of the present invention, in the first to fourth aspects, the status flag provided for each block or each predetermined block of each line is flag data composed of 2 bits. It is in.

According to the fifth aspect of the invention, the configuration is simplified, and at the time of writing, the access width to the status flag can be limited to the flag width corresponding to the write data width.

[0042]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a first embodiment of the cache memory of the present invention.
The same reference numerals are given to the common elements.

It is assumed that the cache memory of this embodiment is mounted on a microprocessor having a bus width of 64 bits. The line size of the cache memory is, for example, 128 bits, and each line is divided into four 32-bit blocks (hereinafter referred to as cells). FIG. 2 shows an image obtained by dividing the data width.

As shown in FIG. 1, this cache memory is different from the configuration of the conventional cache memory (FIG. 8).
A flag holding unit 1, a flag content decoder 2, multiplexers (muxes) 3, 4, a data decoder 5, and an encoder 6 are added. Further, the latch circuit 204A for exchanging data with the memory cell array 203A of the present embodiment includes a mechanism (0 column / 1 column restoration mechanism) for restoring the data of “all 0s” and “all 1s”. ing. In addition, the memory cell array 203A has a mechanism that does not access a cell specified at the time of line access.

Specifically, the flag holding unit 1 determines that the data inside each cell is “all 0”, “all 1”, or “all 0”.
However, each line has a status flag representing the content of "but not all 1 (mixed data of 0 and 1)". Then, the decoder 2 decodes the state flag in the flag holding unit 1 and generates control signals S1 and S2. The multiplexer (mux) 3 temporarily stores the control signal S2 and the control signal S3 output from the decoder 5, and temporarily stores one of the control signal S2 and the control signal S3.
One is selected and output as a 4-bit control signal S5. Similarly, the multiplexer (mux) 4 outputs one of the control signal S 1 and the control signal S 4 output from the decoder 5.
One is selected and output as a 4-bit control signal S6.

The decoder 5 further includes a latch circuit 204
The write data in A is decoded, and the control signals S3 and S
4, the encoder 6 generates a new state flag from the contents of the flag holding unit 1 and the contents of the write data, and updates the contents of the flag holding unit 1. The memory cell array 203A has two complementary bit lines for each bit, and for example, each bit has an SRAM having a configuration shown in FIG.
It is composed of

FIG. 3 shows the memory cell array 203 shown in FIG.
9A is a diagram showing a specific configuration of a latch circuit 204A with a 0-column / 1-column restoration function. FIG.

The memory cell array 203A of the present embodiment
, Rn are divided into 32-bit cells 21, 22, 23, and 24, and two-input NAND gates 31 corresponding to the cells 21 to 24, respectively. , 32, 33, 34 are provided.

The NAND gates 31 to 34 function as a mechanism that does not access the designated cell at the time of line access. A clock CLK is commonly supplied to one input terminal, and a 4-bit signal is supplied to the other input terminal. One bit of the control signal S6 is allocated and supplied. As a result, each bit of the control signal S6 has four cells 21 to 2
4 is an enable signal for supplying the clock CLK to the control signal No. 4.

On the other hand, the latch circuit 204A with the 0 column / 1 column restoring function includes the multiplexer / demultiplexer 13,
14, 15 and 16 and latches 11 and 12. Multiplexer / Demultiplexer 13, 14
Are respectively connected to the upper bit side and the lower bit side of the latch 11 via a 32-bit bus. Similarly, the multiplexer / demultiplexers 15 and 16
The latch 12 is connected to the upper bit side and the lower bit side of the latch 12 via a bit bus. Further, these 32-bit buses are connected to the decoder 5 and the encoder 6 as a 128-bit write data bus.

Multiplexer / Demultiplexer 13-
Numeral 16 is controlled by a control signal S5, and is connected to a 32-bit “0” column (configured with a power supply), a 32-bit “1” column (configured with a ground), and cells 21 to 24, respectively. One of the 32-bit buses. And latches 11 and 12
Are connected to a multiplexer / demultiplexer 206 external to the latch circuit 204A.

Next, the operations (A) and (B) of the present embodiment configured as described above will be described. (A) Read operation First, in order to specify an index, the index part 200b of the address is decoded by the decoder 201.
Select tags, status flags, and data (all cells).
Next, only the selected tag and the status flag are accessed, and the selected data is not yet accessed.

The content of the status flag read by accessing the flag holding unit 1 is decoded by the decoder 2 and converted into control signals S1 and S2. The control signal S1 passes through the multiplexer 4 to become a control signal S6, and the control signal S6
2 passes through the multiplexer 3 and becomes the control signal S5. Further, the control signal S6 composed of 4 bits, each bit of which serves as an enable signal for supplying the clock CLK to the four cells 21 to 24.

According to the contents of the selected state flag, a cell which is found to be "all 0s" or "all 1s" among the four cells 21 to 24 corresponds to the cell among the four bits of the control signal S6. The bit becomes "L" level, and clock CLK is not supplied. Since the control signal for controlling the access operation to the cell array 203A of the cache memory, that is, the series of operations starting from precharge and equalization, is generated from the clock CLK, it does not operate at all unless the clock CLK is supplied.

Further, to the cell which is determined by the contents of the selected status flag to be "not all 0 or all 1", the corresponding bit of the control signal S6 becomes "H" level and the clock CLK is supplied. You.

As a result, of the four cells 21 to 24, only the cell “all 0 or not all 1” is accessed, and the “all 0” or “all 1” part is accessed. Absent. In addition, since the clock CLK is stopped in the “all 0s” and the “all 1s”, power consumption is reduced.

The control signal S5 is supplied to the latch circuit 204A.
Among the four cells 21 to 24, a “0” column of 32 bits for “all 0” cells, and 3 bits for “all 1” cells among the four cells 21 to 24.
In the case of a cell of "1" of 2 bits and "all 0 or neither 1", the output from the memory cell array 203A is selected and stored in the latches 11 and 12, respectively.

The read tag is sent to the comparator 208 for hit determination. In the case of a hit, the decoder 205
, One of the 64-bit data in each of the latches 11 and 12 in the latch circuit 204A is selected, and the read port 207 is selected.
to go into.

(B) Write Operation First, in order to designate an index, the index part 200b of the address is decoded by the decoder 201.
Select tags, status flags, and data (all cells).
Next, the tag holding unit 202 and the flag holding unit 1 are accessed for the selected tag and status flag, and the selected data is not yet accessed in the memory cell array 203A. The content of the status flag read from the flag holding unit 1 is sent to the encoder 6.

On the other hand, the write data passes through the demultiplexer 206 from the write port 207 and enters the latches 11 and 12 in the latch circuit 204A.
Is sent to the decoder 5. The encoder 6 generates a new status flag from the content of the status flag and the content of the data. In the decoder 5, the memory cell array 203A
, And supplies the control signal S6 to the memory cell array 203A as the control signal S6 through the multiplexer 4.

The clock CLK is not supplied to the cells to be updated to "all 0s" or "all 1s", but is supplied to the cells to be updated to "neither all 0s nor all 1s" data. At the same time, the control signal S3
Is generated as a control signal S5 through the multiplexer 3 and the demultiplexers 13 to 1 in the latch circuit 204A.
Supply to 6.

Of the demultiplexers 13 to 16,
The demultiplexer corresponding to the update data “not all 0s or all 1s” is connected to the memory cell array 203A under the control of the control signal S5.

As described above, if the tag check results in a hit, a new state flag is written in the area specified by the corresponding index, and writing is performed only on cells that are updated to “all 0s and all 1s” data. This allows
No access is made to the “all 0s” and “all 1s” parts, and the clock is stopped, so that power consumption is reduced.

On the other hand, if a mistake is found in the tag check, the refill operation is started. At the time of refill, the refill data is stored in the latches 11 and 12 of the latch circuit 204A having the 0-column / 1-column restoration function. 6 generates a state flag, and the decoder 5 generates a control signal S3. The rest is the same operation as writing.

When it is desired to rewrite only the data of one data bus width in one line, the bit line control is inactivated for the remaining non-rewritten area, and the access itself is not performed. It is common to control as follows. With such control,
Since a portion of one line that is not to be rewritten is not accessed in the first place, the cells constituting the portion that is not to be rewritten correspond to any of "all 0", "all 1", "all 0 and neither all 1". There is no need to find out. That is, only the part to be updated is "all 0s",
Since the classification of "all 1s" and "all 0s and neither 1s" may be performed, the control signal S3 can be created only from the data to be written, and does not need to be combined with the contents of the status flag. .

FIG. 4 shows a second example of the cache memory of the present invention.
FIG. 2 is a configuration block diagram showing the embodiment, and the same reference numerals are given to the same elements as those in FIG.

In this embodiment, the line size of the memory cell array is the same as the bus width in the configuration of the first embodiment. In this case, even at the time of writing, all the information necessary to set the status flag can be obtained only from the data content of the latch circuit with the 0 column / 1 column restoring function.
It is not necessary to decode the status flag of the write destination line when writing data, and the encoder is simplified.

More specifically, in the first embodiment, the line size is larger than the bus width, and the number of bits of the status flag is reduced by using the advanced encoder 6. In this case, when writing data, It is necessary to update the contents of the status flag. That is, while the status flag must be set to data representing the status of all the bits of the line including the status of the bits other than the portion to be written in the line, the write data is stored in the latch circuit with restoration function 204A. Because there is only. That is, the state flag is read first to know the state of the bit on the line, and from the contents of the latch circuit with restoration function 204A, the state of the bit after data writing is calculated to generate the contents of the state flag. Therefore, the encoder 6 needs a signal line from the flag holding unit 1 and a signal line from the latch circuit with restoration function 204A.

On the other hand, when the line size is the same as the bus width as in the present embodiment, the state of the bits after data writing is the same as the data content of the latch circuit with the 0 column / 1 column restoring function. Therefore, there is no need to read the status flag, and therefore, the input from the flag holding unit 1 is omitted in the encoder 6A of the present embodiment.

As described above, the encoder 6A of the present embodiment
Has a simplified configuration as compared with the above-described embodiment, and furthermore, in this embodiment, the configuration is simplified corresponding to the memory cell array 203B whose line size is equal to the bus width.
In addition to a latch circuit 204B with a column / single column restoration function,
Since the address offset unit 200c, the decoder 205, and the multiplexer / demultiplexer 206 are not required, high-speed operation is possible.

FIG. 5 shows a third example of the cache memory of the present invention.
FIG. 4 is a block diagram of a main part configuration showing the embodiment, and the same reference numerals are given to the same elements as those in FIG.

In the present embodiment, the configuration of the present invention is applied to only some of the N cells formed by dividing each line in the first embodiment. As is clear from the first embodiment, the present invention increases the circuit scale. Therefore, the present invention is applied only to cells that are effective due to the nature of the program, and if the conventional configuration is used for cells that are not effective, the circuit scale is increased. The increase can be suppressed.

As shown in FIG. 5, the specific configuration of this embodiment is such that the bus width is 64 bits and the line size is 128 bits.
The data compression method of the present invention is not applied to the lower 32 bits of each double word, but is applied to only the upper 32 bits. That is, the lower 32 bits of each double word are the same as the conventional configuration,
Two bits are configured to perform data compression according to the present invention.

As a result, the latch circuit 204C with the 0-column / 1-column restoring function of the present embodiment uses the multiplexer / demultiplexer 1 corresponding to the lower 32 bits shown in FIG.
4 and 16 are omitted, and the memory cell array 203C of the present embodiment has the clock CLK shown in FIG.
The stop NAND gates 32 and 34 are omitted.

Even with such a configuration, there is no change in the connection configuration shown in FIG.
Can be reduced from 4 bits to 2 bits, the bit width of the input signal to the decoder 5 and the encoder 6 can be reduced from 128 bits to 64 bits, and the bit width of the flag holding unit 1 and the control signals S1, S2, S3, S4 Can also be reduced. Further, the logic gate amounts of the decoders 2 and 5 and the encoder 6 are also reduced.

Further, the contents and configuration of the tag of the present invention are irrelevant to the cell division of the memory cell array 203C, and the flag holding unit 1 only needs to connect the cells to be subjected to the data compression of the present invention (of course, the same as in the conventional case). The bit information of the cell having the configuration is not stored in the flag holding unit 1).

The operation of the present embodiment thus configured is the same as that described in the first embodiment for the upper 32 bits and that described in the conventional example of FIG. Do it. At the time of reading, it is only necessary to concatenate the values read independently of each other at the end, and at the time of writing, since the memory cell array 203C is separated, it is apparent that each can be independently accessed in parallel. .

The present invention is not limited to the above-described first to third embodiments, and various modifications are possible. For example, there are the following modifications.

(1) The information of the status flag is set to “all 0s”
Or "Other" or "All 1" or "Other"
In either case, the number of bits of the status flag can be small. Further, since the state flag has the same number of bits as the number of cell divisions per line, not only can encoding and decoding be simplified, but also the access width to the state flag at the time of writing can be limited to a flag width corresponding to the writing data width.

(2) When classifying the state of cells into "all 0s", "all 1s", and "all 0s and not all 1s", a state flag is set so that each cell in each line has 2 bits. Not only makes encoding and decoding easier, but also increases the access width to the status flag during writing.
It can be limited to the flag width corresponding to the write data width.

(3) It goes without saying that the number of divisions of the memory array and the number of bits of the status flag can be increased as compared with the above embodiment.

(4) In the above embodiment, the replenishment function of the “0” column or the “1” column corresponding to the “all 0” or “all 1” cell that has not been accessed is restored to 0 column / 1 column. Although the function is realized by the latch circuit with the function, this function may be used also as the function of the sign extender already provided in the microprocessor.

(5) In the above embodiment, the bus 209
May be separated for reading, writing, and refilling.

(6) In the above embodiment, the output destination of the read data may not be a bus. However,
The bus has a narrow meaning that signal lines are used for a plurality of purposes.

[0085]

As described above in detail, according to the first aspect, when reading / writing data including monotonous bit information such as a monotonic sequence of 0 data and a monotonous sequence of 1 data, the instruction Irrespective of this, the access width can be optimized based on the contents of the data, and the power consumption can be reduced. In particular, for example, when the cache memory of the present invention is mounted on a microprocessor, when a program in which data smaller than the bus width of the microprocessor is frequently used is executed, or a sequence of monotonous 0 data that accidentally enters data, When a program having many monotonous data strings is executed, the effect of reducing power consumption becomes remarkable.

According to the second aspect, the same effect as that of the first aspect can be obtained only for a predetermined block out of N blocks formed by dividing each line. This makes it possible to suppress an increase in circuit scale.

According to the third invention, in the first and second inventions, the line size of the plurality of lines and the bus width of the external bus are equalized, and when writing data, the contents of the status flag of the write destination line are changed. Since the content of the status flag of the flag holding unit is set to a new value based on the content of the write data without decoding, the content of the status flag of the write destination line is not required at the time of data writing, so the configuration Is simplified, and high-speed operation becomes possible.

According to the fourth invention, in the first to third inventions, the contents represented by the status flag are set such that the data in the memory cells in each block is all 0 data, other data, or all 1 data. Since the data is data or other data, the number of bits of the status flag can be reduced. Further, since the status flag has the same number of bits as the number of block divisions per line, not only the configuration is simplified, but also at the time of writing, the access width to the status flag is limited to a flag width corresponding to the write data width. Can be.

According to the fifth aspect, in the first to fourth aspects, the status flag provided for each block of each line or for each predetermined block is flag data composed of 2 bits. Can be simplified, and the access width to the status flag at the time of writing can be limited to the flag width corresponding to the writing data width.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing a first embodiment of a cache memory of the present invention.

FIG. 2 is a diagram illustrating a divided image of a data width according to the first embodiment.

FIG. 3 shows a memory cell array 203A in FIG.
FIG. 9 is a diagram showing a specific configuration of a latch circuit with one-column restoration function 204A.

FIG. 4 is a configuration block diagram showing a second embodiment of the cache memory of the present invention.

FIG. 5 is a block diagram showing a main part of a cache memory according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration example of one bit of an SRAM.

7 is a waveform chart showing an operation for one bit of the SRAM shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a conventional cache memory (first conventional example).

FIG. 9 is a block diagram showing a configuration of a conventional cache memory (second conventional example).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Flag holding | maintenance part 2,5 decoder 3,4 Multiplexer (mux) 6 Encoder 201,205 Decoder 202 Tag holding | maintenance part 203A, 203B, 203C Memory cell array 204A, 204B, 204C Latch circuit 206 with 0 column / 1 column restoration function 206 multiplexer / Demultiplexer 207 Read / write port 208 Comparator 209 External bus

Claims (5)

[Claims] 1. A memory system comprising: a plurality of lines each having a memory cell for each bit; each of said memory cells being connected to two complementary bit lines for each bit; A data storage unit for reading / writing data from / to a tag, a tag holding unit holding a tag indicating a position in an external main storage device, and matching / mismatch between a tag in the tag holding unit and a tag specified by a program And a hit judging unit for judging hit / hit / miss by comparing the data. When a hit is judged by the judging unit, predetermined data is read out from the data storage unit to the outside at the time of data reading, and at the time of data writing. When write data from the outside is written to the data storage unit and the hit / miss determination is made by the determination unit, the required data from the main storage device is written to the data storage unit. In a cache memory for refilling data to be written into a data storage unit, each line in the data storage unit is divided into N (positive integer) blocks, and memory cell data in each block is all 0 data and all 1 data Alternatively, a flag holding unit for holding a state flag representing the content of mixed 0 and 1 data for each line is provided, and at the time of reading the data, the content of the state flag in the flag holding unit corresponding to the read line , The above-mentioned 0 and 1 of each block in the read line
Only the block storing the mixed data is accessed, and the read data is read out to the outside by supplementing the 0 data string or the 1 data string corresponding to the all 0 data or the all 1 data. Based on the content of the status flag in the flag holding unit corresponding to the previous line and the content of the write data, the content of the status flag of the flag holding unit is set to a new value, and 0 and 1 of the write data are set. The mixed data only portion is written to the write destination line. At the time of the refill, the content of the status flag of the flag holding unit is set to a new value based on the content of the required data to be written, and 0 of the required data is set. And 1
A cache memory in which a portion including only mixed data is written to the data storage unit. 2. A memory system comprising: a plurality of lines each having a memory cell for each bit, wherein each memory cell is connected to two complementary bit lines for each bit, and selectively connected to the memory cell through the bit line. A data storage unit for reading / writing data from / to a tag, a tag holding unit holding a tag indicating a position in an external main storage device, and matching / mismatch between a tag in the tag holding unit and a tag specified by a program And a hit judging unit for judging hit / hit / miss by comparing the data. When a hit is judged by the judging unit, predetermined data is read out from the data storage unit to the outside at the time of data reading, and at the time of data writing. When write data from the outside is written to the data storage unit and the hit / miss determination is made by the determination unit, the required data from the main storage device is written to the data storage unit. In a cache memory for performing a refill to be written to a data storage unit, each of the lines in the data storage unit is divided into N (positive integer) blocks, and all the memory cell data in a predetermined block less than N is 0. A flag holding unit for holding, for each line, a status flag indicating that the data is all 1 data or other mixed 0 and 1 data; and when reading the data, the flag holding unit corresponding to the read line is provided. With reference to the contents of the status flag, only the block storing the mixed data of 0 and 1 among the predetermined blocks on the read line is accessed, and the all 0 data or the all Complement 0 data string or 1 data string corresponding to 1 data When the data is written, the state of the flag holding unit is determined based on the contents of the status flag in the flag holding unit corresponding to the writing destination line and the contents of the write data for the predetermined block of the writing destination line. The content of the flag is set to a new value, and a portion of only the mixed data of 0 and 1 among the write data for the predetermined block of the write destination line is written to the predetermined block. At the time of the refill, the data should be written to the predetermined block. A cache, wherein the content of the status flag of the flag holding unit is set to a new value based on the content of the required data, and a portion of only the mixed data of 0 and 1 of the required data is written to the predetermined block. memory. 3. The method according to claim 1, wherein the line size of the plurality of lines is equal to the bus width of an external bus, and at the time of data writing, the content of the status flag of the write destination line is not decoded, 3. The cache memory according to claim 1, wherein the content of the status flag of the flag holding unit is set to a new value. 4. The method according to claim 1, wherein the contents represented by the status flags are all 0 data or other data, or all 1 data or other data in the memory cells in each of the blocks. The cache memory according to any one of claims 1 to 3. 5. The cache memory according to claim 1, wherein the status flag provided for each block or each predetermined block of each line is flag data composed of two bits.