JPH10107861A - Frequency offset compensation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency offset compensation device in which highly accurate compensation is applied to a reference oscillator and initial locking is attained at a high speed. SOLUTION: This device is provided with a phase error estimation means 6 that estimates a phase error resulting from a frequency offset to provide an output of a phase error compensation value and a conversion means 7 that converts the phase error compensation value into frequency control data to control the reference oscillator based on the phase error compensation value. In this case, the device is provided with a compensation elimination means 5 that excludes the effect of the frequency offset compensation conducted at present from reception data after the detection, and the phase error estimation means uses the averaging method to calculate the phase error compensation value with respect to an initial frequency offset based on the correlation between the output of the compensation elimination means and the discrimination result of the reception data. Even after the frequency control of the reference oscillator 8, the phase error compensation value is calculated by using previous data and the compensation with high accuracy and high speed initial locking are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency offset compensator used for a data receiving device of digital mobile communication, and more particularly to a device capable of correcting an oscillation frequency of a reference oscillator at high speed.

[0002]

2. Description of the Related Art A data receiving apparatus for digital mobile communication or the like detects a received signal to decode data. At this time, a carrier frequency used for modulation on a transmitting side and an oscillation frequency of a reference oscillator used for demodulation on a receiving side are used. If there is a frequency error (offset) between the two, correct decoding cannot be performed. Therefore, the data receiving device includes a frequency offset compensating device, compensates for the frequency offset, and corrects the oscillation frequency of the reference oscillator.

[0003] When a received signal is, for example, a π / 4-shifted QPSK modulated wave signal, a conventional frequency offset compensator, as shown in FIG. Component X
An input terminal 61 to which (nT) is applied, an input terminal 62 to which an orthogonal component Y (nT) at the time of symbol identification of waveform-shaped baseband waveform data is applied, and an input terminal
Waveform data X (nT), Y (nT) applied to 61 and 62
And the cosine and the sine of the modulation phase difference of the received π / 4 shift QPSK modulated wave signal are in-phase components I (n
T), a baseband delay detection circuit 63 that outputs a signal S (nT) having quadrature components Q (nT), an output signal S (nT) of the baseband delay detection circuit 63, and an output signal D of a determination circuit 68 described later. (NT), a phase error estimating circuit 64 for estimating the phase error and updating the data of the phase compensation value for each symbol and outputting the same, and a baseband delay using the phase compensation value supplied from the phase error estimating circuit 64. A phase compensation circuit 67 for compensating for a phase error caused by a frequency offset included in the output signal S (nT) of the detection circuit 63, and a phase compensation circuit
A determination circuit 68 for performing a quadrant determination on the received data output from the 67, and a conversion circuit 69 for converting the phase compensation value supplied from the phase error estimation circuit 64 into a control signal (frequency control data) for a reference oscillator 71 described later. An averaging circuit 70 for averaging the frequency control data of the reference oscillator output from the conversion circuit 69, a reference oscillator 71 for supplying an oscillation frequency serving as an operation reference of the data receiving device, and an output of the determination circuit 68 A decoder 72 for converting the data into binary serial data, and a reception data output terminal 73 for outputting the output of the decoder 72 as reception data.

When the frequency of the reference oscillator 71 is controlled, the conversion circuit 69 outputs a reset signal for resetting the data of the past phase compensation value of the phase error estimation circuit 64.

The phase error estimating circuit 64 includes a conjugate complex signal S * (nT) (* indicates a conjugate complex number) of the output signal S (nT) of the baseband differential detection circuit 63 and an output signal D of the judgment circuit 68. A correlation operation circuit 65 for calculating a complex correlation value with (nT) and an average value Ψ * of the complex correlation value using an adaptive algorithm, and the average value Ψ * is updated as a phase compensation value for each symbol. And an adaptive operation circuit 66 for outputting the result. This phase compensation value Ψ * is a conjugate complex number of the phase error estimation value Ψ.

The operation of this device will be described. At the symbol identification time point nT (n: positive integer, T: symbol period), the input terminal 61 receives the in-phase component X (nT) of the waveform-shaped baseband waveform data, and the input terminal 62 receives the waveform. The orthogonal component Y (nT) of the shaped baseband waveform data is applied and supplied to the baseband differential detection circuit 63, respectively. The baseband delay detection circuit 63
Delay detection is performed on the waveform data X (nT) and Y (nT) to determine the phase difference between one symbol, and the π / 4 shift QP
The cosine and sine of the modulation phase difference of the SK modulated wave signal are output as an in-phase component I (nT) and a quadrature component Q (nT), respectively.

Here, when the output of the baseband differential detection circuit 63 is represented by a complex signal S (nT) having a real part of an in-phase component and an imaginary part of a quadrature component, the output becomes as shown in Equation 1.

S (nT) = I (nT) + jQ (nT) (Equation 1) Similarly, the complex expressions of the output of the phase error estimating circuit 64 and the output of the judging circuit 68 are represented by Ψ * ((n−1 ) T), D (nT)
And

Therefore, an estimated value Ψ (nT) of the phase error caused by the frequency offset is selected as follows. That is, with respect to the output S (nT) of the baseband differential detection circuit 63, the estimated value of the phase error 出力 ((n-1)
The result of phase compensation performed by the phase compensation circuit 67 using the complex conjugate Ψ * ((n−1) T) of T) results in S (nT) · Ψ * ((n−1)
T), and the judgment circuit 68 sets the output of the phase compensation circuit 67 to 4
Error e (n) = D from result of value determination D (nT)
(NT) −S (nT) · Ψ * ((n−1) T) is selected so as to minimize the sum of squares.

When the estimated value of the phase error is selected in this manner, the conjugate complex number of the estimated value of the phase error, that is, the phase compensation value Ψ
* (NT) is obtained by performing the correlation operation shown in (Equation 2) in the phase error estimating circuit 64.

Ψ * (nT) = Σλ ^nk · S * (kT) · D (kT) / Σλ ^nk · | S (kT) | ² (Σ is added from k = 1 to n) (Equation 2) , Λ are forgetting factors, and values are determined within a range of 0 <λ ≦ 1.

At this time, the correlation operation circuit 65 of the phase error estimating circuit 64 calculates S * (n) shown in (Equation 2) for each symbol.
T) · D (nT) correlation operation is performed. Further, the adaptive operation circuit 66 uses the output of the correlation operation circuit 65 and the output signal S (nT) of the baseband delay detection circuit 63 to obtain (Equation 2)
適 応 * (n
T) is output.

The phase compensation circuit 67 uses the phase compensation value Ψ * (nT) obtained in this way to add a frequency offset to the data S ((n + 1) T) at the symbol identification time point (n + 1) T after one symbol. And the decision circuit 68 makes a quaternary decision on the data with the compensated phase error. The output of the determination circuit 68 is converted into binary serial data by the decoder 72 and output from the output terminal 73 as received data.

The phase compensation value Ψ * (nT) output from the phase error estimation circuit 64 is sent to the conversion circuit 69,
69 converts this Ψ * (nT) into a control signal for correcting the frequency shift of the reference oscillator 71. The control signal for the reference oscillator 71, which is the output of the conversion circuit 69, is averaged by the averaging circuit 70, and the oscillation frequency of the reference oscillator 71 is controlled by the averaged control signal, thereby correcting the frequency shift.

When the frequency control of the reference oscillator 71 is performed, the past data used for calculating the phase compensation value cannot be referred to, so that the reset signal is output from the conversion circuit 69 to the phase error estimation circuit 64. And the phase error estimating circuit 64
Is reset.

In the averaging circuit 70, the reference oscillator
The control signal for 71 is not reset even when the frequency control of the reference oscillator 71 is performed, and is subsequently averaged with the past control signal.

As described above, the conventional frequency offset compensating apparatus executes the operation shown in (Equation 2) for each symbol and updates the compensation value of the phase error for each symbol. Therefore, highly accurate phase error compensation can be performed.

[0018]

However, the conventional frequency offset compensator can compensate for the phase error caused by the frequency offset of the baseband signal with high accuracy.
There are the following problems.

The phase error estimating circuit 64 obtains a phase compensation value by averaging the data during the time nT by an adaptive algorithm, and the frequency control of the reference oscillator is performed using the result. When the compensation value is updated, the past data in the phase error estimating circuit 64 is reset, and the phase error estimating circuit 64 recalculates the phase compensation value using newly obtained data.

At this time, if the phase compensation value calculated from the small number of data calculated by the phase error estimating circuit 64 is used for the frequency control of the reference oscillator, high-precision control cannot be performed. If the circuit 64 attempts to control the frequency of the reference oscillator using the phase compensation value calculated by averaging a predetermined number or more of data, much time is required for the initial pull-in.

The present invention solves such a conventional problem, and provides a frequency offset compensator capable of performing high-accuracy frequency control on a reference oscillator and performing high-speed initial pull-in. It is intended to be.

[0022]

Therefore, in the frequency offset compensating apparatus of the present invention, there is provided a compensation removing means for removing the effect of the currently performed frequency offset compensation from the received data after detection, and the phase error estimating means is provided. The phase error compensation value for the initial frequency offset is calculated based on the correlation value between the output of the compensation removing means and the result of the judgment of the received data.

In this apparatus, a phase error compensation value for an initial frequency offset from which the influence of frequency offset compensation has been removed is obtained, and the frequency of the reference oscillator is controlled based on the phase error compensation value. Therefore, even when the frequency of the reference oscillator is controlled, the past data used for calculating the phase error compensation value can be used as data to be averaged without resetting, and the phase error compensation value can be continuously maintained. The calculation can be continued. Therefore, high-precision control of the reference oscillator and high-speed initial pull-in can be realized.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a phase error estimating means for estimating a phase error due to a frequency offset and outputting a phase error compensation value, and a reference oscillator for outputting the phase error compensation value. A frequency offset compensator for controlling the frequency of the reference oscillator based on the phase error compensation value. A phase error estimating means for averaging the phase error compensation value for the initial frequency offset based on a correlation value between the output of the compensation removing means and the result of the determination of the received data. Is calculated, and even if the frequency control of the reference oscillator is performed, there is no need to reset the past data. Can be performed to continue the calculation of the error compensation values, it is possible to realize a high-speed offset compensation and initial pull precision.

According to a second aspect of the present invention, the phase error estimating means includes a correlation value between the conjugate complex data output from the compensation value removing means and the data of the determination result and a complex multiplication value output from the compensation value removing means. Calculating means for calculating a moving average with respect to the output of the correlation calculating means, and an estimation error for calculating a phase error compensation value from the output of the moving average means and outputting the compensation value for each symbol And a compensating means, so that a highly accurate phase error compensation value can be calculated.

According to a third aspect of the present invention, the phase error estimating means includes a correlation value between the conjugate complex data output from the compensation value removing means and the data of the determination result and a complex multiplication value output from the compensation value removing means. Is output for each symbol, an adaptive operation means for averaging the output of the correlation operation means using an adaptive algorithm, and a phase error compensation value is calculated from the output of the adaptive operation means for one symbol. And an estimation error correction means for outputting each time.
A highly accurate phase error compensation value can be calculated by an adaptive algorithm.

According to a fourth aspect of the present invention, the phase error estimating means includes a correlation value between the conjugate complex data output from the compensation value removing means and the data of the determination result and a complex multiplication value output from the compensation value removing means. Is output for each symbol, and N is used to accumulate the output of the correlation operation means for N symbols.
It comprises a symbol adding means, a moving average means for calculating a moving average for the output of the N symbol adding means, and an estimation error correcting means for calculating a phase error compensation value from the output of the moving average means and outputting the compensation value every N symbols. The power consumption required for calculating the phase error compensation value can be reduced by performing the calculation of the phase error compensation value at intervals.

According to a fifth aspect of the present invention, the phase error estimating means includes a correlation value between the conjugate complex data output from the compensation value removing means and the data of the determination result and a complex multiplication value output from the compensation value removing means. Is output for each symbol, and N is used to accumulate the output of the correlation operation means for N symbols.
Symbol adding means, adaptive calculating means for performing an average calculation using an adaptive algorithm on the output of the N symbol adding means, and an estimation error for calculating a phase error compensation value from the output of the adaptive calculating means and outputting the compensation value every N symbols And a compensator, which can reduce power consumption when calculating a phase error compensation value using an adaptive algorithm.

According to a sixth aspect of the present invention, when the calculated phase error compensation value exceeds the compensable range, the estimation error correcting means corrects the phase error compensation value to a phase error compensation value within the compensable range. Therefore, an appropriate phase error compensation value can be output.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(First Embodiment) The frequency offset compensator of the first embodiment is a TDMA π / 4 shift Q
The configuration will be described assuming that a PSK modulated wave signal is received.

As shown in FIG. 1, this apparatus has an input terminal 1 to which an in-phase component X (nT) at the time of symbol identification of waveform-shaped baseband waveform data is applied;
The input terminal 2 to which the orthogonal component Y (nT) is applied at the time of symbol identification of the waveform-shaped baseband waveform data, and the waveform data X (n) applied to the input terminals 1 and 2
T), Y (nT) is taken, and the received π / 4 shift Q
A baseband differential detection circuit 3 that outputs a signal S (nT) having a cosine and a sine of a modulation phase difference of a PSK modulation wave signal as an in-phase component I (nT) and a quadrature component Q (nT), respectively.
And the output signal S (nT) of the baseband differential detection circuit 3
, A compensation removal circuit 5 that removes the influence of the frequency offset compensation currently performed from the output signal S (nT) of the baseband differential detection circuit 3, and an output signal D of the decision circuit 4. A phase error estimating circuit 6 for estimating a phase error caused by a frequency offset from the correlation value between (nT) and the output signal U (nT) of the compensation removing circuit 5 using an averaging method; A conversion circuit 7 for converting the compensation value of the phase error, which is a signal, into data for controlling the frequency of the reference oscillator, a reference oscillator 8 for supplying an oscillation frequency serving as an operation reference of the data receiving device, Decoder 9 for converting to serial data
And a reception data output terminal 10 for outputting the output of the decoder 9 as reception data.

Further, as shown in FIG. 2, the phase error estimating circuit 6 outputs the conjugate complex signal U * (nT) of the output signal U (nT) of the compensation removing circuit 5 and the output signal D (nT) of the judging circuit 4. U * (nT) .D (nT) and the complex multiplication result | U of the output signal U (nT) of the compensation elimination circuit 5 and the conjugate complex signal U * (nT) of U (nT) * (nT) | ^2, and 1 for the correlation values U * (nT) .D (nT) and | U * (nT) | ² output from the correlation operation circuit 21. performs a moving average calculation of the L symbols for each symbol, the average value of the correlation values U * (nT) · D ( nT) for each symbol AZ (nT), and, | U * (nT) | 2 of the mean value AR
a moving average circuit 22 for updating (nT), and a phase error compensation value Ψ * (nT) for each symbol from the output of the moving average circuit 22
Is calculated, and when this compensation value exceeds the compensable range,
An estimation error correction circuit 23 that outputs a phase compensation value Ψ * (nT) after the compensation is performed within the compensable range.

The operation of the frequency offset compensator will be described.

Symbol identification time point nT (n: positive integer, T:
In the symbol period), the in-phase component X (nT) of the baseband waveform data whose waveform has been shaped is input to the input terminal 1.
Further, the orthogonal component Y (nT) of the baseband waveform data whose waveform has been shaped is applied to the input terminal 2, and is supplied to the baseband differential detection circuit 3. The baseband delay detection circuit 3 outputs the waveform data X (nT), Y (nT)
, And outputs the cosine and sine of the modulation phase difference of the π / 4 shift QPSK modulated wave signal as an in-phase component I (nT) and a quadrature component Q (nT), respectively. The output of the baseband differential detection circuit 3 is represented by the following (Equation 1): S (nT) = I (Nt) + jQ (nT) (Equation 1) Similarly, the complex expression of the compensation value output from the phase error estimating circuit 6 is represented as Ψ * (nT), and the complex value is output from the determination circuit 4.
The complex expression of the result of the quaternary determination for S (nT) is expressed as
T).

At this time, the conversion circuit 7 converts the compensation value Ψ * ((n−1) T) of the phase error due to the frequency offset into data for controlling the frequency of the reference oscillator 8, Assuming that the control is being performed, the output S (nT) of the baseband differential detection circuit 3 can be expressed as (Equation 3).

S (nT) = U (nT) · Ψ * ((n−1) T) (Equation 3) where U (nT) is a signal after baseband differential detection without frequency offset compensation. . Therefore, U (nT) can be obtained by performing the operation shown in (Equation 4) for each symbol in the compensation removing circuit 5.

U (nT) = S (nT) / Ψ * ((n−1) T) (Equation 4) Therefore, the estimated value 位相 (n) of the phase error caused by the frequency offset is calculated by the compensation removal circuit 5 The output U (nT) and the output S (nT) of the baseband differential detection circuit 3 in the determination circuit 4
Error e with respect to D (nT) as a result of quaternary judgment
(n) = D (nT) -U (nT) so that the root mean square is minimized. At this time, the conjugate complex number of the estimated value of the phase error, that is, the phase compensation value Ψ * (nT) is obtained as an output of the phase error estimating circuit 6 by performing the correlation operation shown in (Equation 5) by the phase error estimating circuit 6. can get.

Ψ * (nT) = E [U * (nT) · D (nT)] / E [| U (nT) | ² ] = AZ (nT) / AR (nT) (Equation 5) [·] Is an averaging operation, in which an operation for obtaining a moving average of L symbols (L: positive integer) is performed.

The correlation operation circuit 21 of the phase error estimation circuit 6
The correlation calculation of U * (nT) · D (nT) shown in (Equation 5) and the multiplication of | U (nT) | ² are performed for each symbol, and the calculation result is output to the moving average circuit 22. Using this output, the moving average circuit 22 performs the moving average operation shown in (Equation 5) for each symbol, and as a result, AZ (nT) and AR (n
T) is output. The estimation error correction circuit 23 is a moving average circuit 2
Using the two outputs AZ (nT) and AR (nT), a compensation value Ψ * (nT) of the phase error is calculated and output for each symbol. If the compensation value exceeds the compensable range, the compensation value is corrected to be within the compensable range, and then the compensated compensation value Ψ *
(nT) is output (this correction corresponds to, for example, setting the compensation value to (90 ° −θ) when the phase error θ exceeds the compensable range of 45 °).

The phase compensation value Ψ * (nT) obtained in this manner is output to the conversion circuit 7, which converts the 補償 * (nT)
Is converted to a control signal of the reference oscillator 8 at the symbol identification time (n + 1) T, and the control signal controls the oscillation frequency of the reference oscillator 8 to correct the frequency shift.

Since the phase compensation value Ψ * (nT) obtained by the phase error estimating circuit 6 is a phase compensation value for the initial frequency offset, even when the frequency of the reference oscillator 8 is controlled, the phase error estimating circuit 6 In, the phase compensation value can be calculated by continuously using the data used for calculating the past phase compensation value without resetting the data.

The output of the decision circuit 4 is converted into binary serial data by a decoder 9 and output from an output terminal 10 as received data.

As described above, the frequency offset compensator of the first embodiment continuously controls the frequency of the reference oscillator by using the compensation value of the initial frequency offset calculated in the baseband band, while performing the current control. The influence of the frequency offset compensation is removed, and the compensation value for the initial frequency offset is continuously calculated by an averaging method that takes a moving average for each symbol. In this device, even when the frequency control of the reference oscillator is performed, it is not necessary to reset the data used for calculating the phase compensation value, so that a highly accurate compensation value can be obtained continuously, and a high frequency offset can be obtained. Accurate compensation and high-speed initial pull-in can be realized together.

(Second Embodiment) The frequency offset compensator of the second embodiment uses an averaging method by an adaptive algorithm when estimating a phase error.

The phase error estimating circuit 6 in this device
As shown in FIG. 3, the output signal U (n
T), the complex correlation value U * (nT) · D (nT) between the conjugate complex signal U * (nT) and the output signal D (nT) of the decision circuit 4 and the output signal U (nT) of the compensation removal circuit 5 A correlation operation circuit 31 that outputs a result of complex multiplication of U (nT) with a conjugate complex signal U * (nT) | U * (nT) | ^2, and a correlation value U * (nT) output from the correlation operation circuit 31 D (nT) and | U * (nT) | ²
, An averaging operation using an adaptive algorithm is performed for each symbol, and a correlation value U * (nT) · D is calculated for each symbol.
an adaptive operation circuit 32 for updating the average value AZ (nT) of (nT) and the average value AR (nT) of | U * (nT) | ² , and compensating for a phase error for each symbol from the output of the adaptive operation circuit 32 Value Ψ *
(nT) is calculated, and when the compensation value exceeds the compensable range, the compensation value is corrected to be within the compensable range, and then the phase compensation value Ψ *
and an estimation error correction circuit 33 for outputting (nT). The overall configuration of this device is the same as in the first embodiment (FIG. 1).

In this frequency offset compensator, the first
Similarly to the embodiment, the compensation elimination circuit 5 calculates U (nT) = S (nT) / (* ((n−1) T) (Equation 4), and calculates U (nT) for each symbol. And the phase error estimating circuit 6 calculates the sum of squares of the error e (n) = D (nT) -U (nT) between U (nT) and D (nT) which is the output of the determining circuit 4. Is minimized, and the correlation operation shown in (Equation 6) is performed, and a phase compensation value Ψ * (nT) is output for each symbol.

Ψ * (nT) = Σλ ^nk · U * (kT) · D (kT) / Σλ ^nk · | U (kT) | ² = AZ (nT) / AR (nT) (Σ is from k = 1 (up to n) (Equation 6) Here, λ is a forgetting coefficient, and a value is determined within a range of 0 <λ ≦ 1.

The correlation operation circuit 31 of the phase error estimation circuit 6
The correlation operation of U * (nT) · D (nT) shown in (Equation 6) and
Multiplication of | U (nT) | ² is performed for each symbol, and the calculation result is output to the adaptive operation circuit 32. Using this output, the adaptive operation circuit 32 performs an operation according to the adaptive algorithm shown in (Equation 6) for each symbol, and as a result, AZ (n
T) and AR (nT). The estimation error correction circuit 33
Using the outputs AZ (nT) and AR (nT) of the adaptive arithmetic circuit 32, a phase error compensation value Ψ * (nT) is calculated and output for each symbol. If the compensation value is outside the compensable range, the compensation value is corrected to be within the compensable range, and the compensated compensation value Ψ * (nT) is output.

The phase compensation value Ψ * (nT) thus obtained is output to the conversion circuit 7, and the conversion circuit 7 outputs the 補償 * (nT)
Is converted to a control signal of the reference oscillator 8 at the symbol identification time (n + 1) T, and the control signal controls the oscillation frequency of the reference oscillator 8 to correct the frequency shift.

Since the phase compensation value Ψ * (nT) obtained by the phase error estimating circuit 6 is a phase compensation value for the initial frequency offset, the frequency control of the reference oscillator 8 was performed as in the first embodiment. Even in this case, the phase error estimating circuit 6 can continuously calculate the phase compensation value by using the data used for the calculation of the past phase compensation value without resetting the data.

As described above, the frequency offset compensator of the second embodiment continuously controls the frequency of the reference oscillator using the compensation value of the initial frequency offset calculated in the baseband band, while performing the current control. The effect of the frequency offset compensation is removed, and the compensation value for the initial frequency offset is continuously calculated using an averaging method using an adaptive algorithm. The use of the adaptive algorithm enables highly accurate compensation, and the use of the compensation value for the initial frequency offset can realize faster initial pull-in.

(Third Embodiment) The frequency offset compensator of the third embodiment aims to reduce power consumption by providing an interval for calculating a compensation value.

The phase error estimating circuit 6 in this device
As shown in FIG. 4, the output signal U (n
T), the complex correlation value U * (nT) · D (nT) between the conjugate complex signal U * (nT) and the output signal D (nT) of the decision circuit 4 and the output signal U (nT) of the compensation removal circuit 5 A correlation operation circuit 41 for outputting a result of complex multiplication of U (nT) with a conjugate complex signal U * (nT) | U * (nT) | ^2, and a correlation value U * (nT) output from the correlation operation circuit 41 D (nT) and | U * (nT) | ²
Are accumulated for N symbols, and the correlation value U *
(nT) · D (nT) addition result Z (m) and | U * (nT)
| N intersymbol addition circuit 42 for updating the addition result R (m) of ² and Z output from N intersymbol addition circuit 42
(M) and R (m) are subjected to a moving average calculation of M × N symbols for every N symbols, and Z
Average value AZ (m) of (m) and average value A of R (m)
A moving average circuit 43 for updating R (m);
誤差 * (m) phase error compensation value every N symbols from output
Is calculated, and when this compensation value exceeds the compensable range,
An estimation error correction circuit 44 that outputs a phase compensation value Ψ * (m) after the compensation is performed within the compensable range is provided. The overall configuration of this device is the same as in the first embodiment (FIG. 1).

In this frequency offset compensator, the first
Similarly to the embodiment, the compensation elimination circuit 5 calculates U (nT) = S (nT) / (* ((n−1) T) (Equation 4), and calculates U (nT) for each symbol. Is output. The phase error estimating circuit 6 calculates the error e (n) = D (nT) -U (nT) between U (nT) and D (nT) which is the output of the determining circuit 4.
Is performed so as to minimize the root-mean-square of, and a phase compensation value Ψ * (m) is output for every N symbols. Here, n, N, and m are N × m ≦ nT <N
× (m + 1), (n: positive integer, T: symbol period, m:
(Positive integer, N: average number of symbols).

Ψ * (m) = E [ΣU * (kT) · D (kT)] / E [Σ | U (kT) | ² ] = AZ (m) / AR (m) (Equation 7) Z (m) = ΣU * (kT) · D (kT) R (m) = Σ | U (kT) | ² AZ (m) = E [ΣU * (kT) · D (kT)] = E [Z (m)] AR (m) = E [Σ | U (kT) | ² ] = E [R (m)] (Each Σ is added from k = 1 to N) Note that E [•] is an average operation Yes, an operation for obtaining a moving average of M × N symbols (M, N: positive integers) is performed.

The correlation operation circuit 41 calculates the U * shown in (Equation 7).
The correlation operation of (nT) · D (nT) and the multiplication of | U (nT) | ² are performed for each symbol, and these U * (nT) · D (n
T) and | U (nT) | ² are output to the N-symbol addition circuit 42. The N-symbol addition circuit 42 performs the addition shown in (Equation 7) on the output of the correlation operation circuit 41, and outputs Z (m) and R (m) once for N symbols as a result.
The moving average circuit 43 performs a moving average operation of Z (m) and R (m) output every N symbols according to (Equation 7).
As a result, AZ (m) and AR (m) are output. The estimation error correction circuit 44 outputs the outputs AZ (m) and AR (m) of the moving average circuit 43.
Is used once every N symbols to compensate for the phase error Ｎ *
(m) is calculated and output. If the compensation value exceeds the compensable range, the compensation value is corrected within the compensable range and the compensated compensation value 補償 * (m) is output.

The thus obtained phase compensation value 得 *
(m) is converted by the conversion circuit 7 into a control signal for correcting the frequency shift of the reference oscillator 8, and the control signal is used to determine the symbol identification time point nT (N × (m + 1) ≦ nT <
The oscillation frequency of the reference oscillator 8 in (N × (m + 2)) is controlled, and the frequency deviation is corrected.

As described above, the frequency offset compensator of the third embodiment continuously controls the frequency of the reference oscillator using the compensation value of the initial frequency offset calculated in the baseband band, while performing the current control. The effect of the frequency offset compensation is removed, and the compensation value for the initial frequency offset is continuously calculated for every N symbols by using an averaging method using a moving average. With this device, high-precision compensation is possible, and the speed of the initial pull-in can be increased. In addition, by calculating the compensation value at intervals of N symbols, the power consumed for the calculation can be reduced. Can be.

(Fourth Embodiment) The frequency offset compensator of the fourth embodiment reduces the power consumption by increasing the calculation interval when calculating the compensation value using an averaging method using an adaptive algorithm. I'm trying.

The phase error estimating circuit 6 in this device
As shown in FIG. 5, the output signal U (n
T), the complex correlation value U * (nT) · D (nT) between the conjugate complex signal U * (nT) and the output signal D (nT) of the decision circuit 4 and the output signal U (nT) of the compensation removal circuit 5 A correlation operation circuit 51 that outputs a result of complex multiplication | U * (nT) | ² of U (nT) with a conjugate complex signal U * (nT), and a correlation value U * (nT) output from the correlation operation circuit 51 D (nT) and | U * (nT) | ²
Are accumulated for N symbols, and the correlation value U *
(nT) · D (nT) addition result Z (m) and | U * (nT)
| The N intersymbol addition circuit 52 for updating the addition result R (m) of ^{2 and} the Z output from the N intersymbol addition circuit 52
An average operation using an adaptive algorithm is performed on (m) and R (m) every N symbols, and an average value AZ (m) of Z (m) and an average value of R (m) for every N symbols Adaptive arithmetic circuit 53 for updating AR (m) and adaptive arithmetic circuit
Compensation value of phase error for every N symbols from 53 outputs Ψ *
(m) is calculated, and when this compensation value exceeds the compensable range, the compensation value is corrected within the compensable range, and then the phase compensation value Ψ *
(m) is output. The overall configuration of this device is the same as in the first embodiment (FIG. 1).

In this frequency offset compensator, the first
Similarly to the embodiment, the compensation elimination circuit 5 calculates U (nT) = S (nT) / (* ((n−1) T) (Equation 4), and calculates U (nT) for each symbol. Is output. The phase error estimating circuit 6 calculates the error e (n) = D (nT) -U (nT) between U (nT) and D (nT) which is the output of the determining circuit 4.
The correlation operation shown in (Equation 8) is performed so as to minimize the sum of squares, and a phase compensation value Ψ * (m) is output for every N symbols. Here, n, N, and m are N × m ≦ nT <N ×
(M + 1), (n: positive integer, T: symbol period, m: positive integer, N: average number of symbols).

Ψ * (m) = Σ′λ ^mi · {ΣU * (kT) · D (kT)} / Σ′λ ^mi · {Σ | U (kT) | ² } = AZ (m) / AR ( m) (Equation 8) where Z (m) = ΣU * (kT) · D (kT) R (m) = Σ | U (kT) | ² AZ (m) = Σ′λ ^mi · {ΣU * ( kT) · D (kT)} = Σ'λ ^mi · Z
(m) AR (m) = Σ′λ ^mi · {Σ | U (kT) | ² } = Σ′λ ^mi · R (m) (Σ is added from i = 1 to m, Σ is k = 1 Here, λ is a forgetting coefficient, and a value is determined within a range of 0 <λ ≦ 1.

The correlation operation circuit 51 calculates the U * shown in (Equation 8).
The correlation operation of (nT) · D (nT) and the multiplication of | U (nT) | ² are performed for each symbol, and these U * (nT) · D (n
T) and | U (nT) | ² are output to the N-symbol addition circuit 52. The N-symbol addition circuit 52 performs the addition shown in (Equation 8) on the output of the correlation operation circuit 51, and as a result, outputs Z (m) and R (m) once for N symbols.
The adaptive operation circuit 53 calculates Z (m) and R (N) output from the N-symbol addition circuit 52 for each N symbols according to (Equation 8).
An average operation using an adaptive algorithm is performed on (m), and AZ (m) and AR (m) are output as a result. The estimation error correction circuit 54 outputs the output AZ (m), AR
Using (m), once every N symbols, the compensation value of the phase error Ψ
* Calculate and output (m). If the compensation value exceeds the compensable range, the compensation value is corrected within the compensable range and the compensated compensation value 補償 * (m) is output.

The phase compensation value Ψ * thus obtained
(m) is converted by the conversion circuit 7 into a control signal for correcting the frequency shift of the reference oscillator 8, and the control signal is used to determine the symbol identification time point nT (N × (m + 1) ≦ nT <
The oscillation frequency of the reference oscillator 8 in (N × (m + 2)) is controlled, and the frequency deviation is corrected.

As described above, the frequency offset compensator of the fourth embodiment continuously performs the frequency control of the reference oscillator using the compensation value of the initial frequency offset calculated in the baseband band, while performing the current control. The effect of the frequency offset compensation is removed, and the compensation value for the initial frequency offset is continuously calculated for every N symbols by using an averaging method using an adaptive algorithm. In this device, high-precision compensation is possible, and the speed of the initial pull-in can be increased, and the compensation value is calculated at intervals of N symbols to reduce the power consumed for the calculation. Can be.

[0067]

As is apparent from the above description, the frequency offset compensator of the present invention can control the frequency of the reference oscillator with high accuracy to compensate for the frequency offset, and can perform the initial pull-in at a high speed. Can do it.

Further, in the devices according to the third and fourth embodiments which output the phase error compensation value every N symbols, the power consumed for the calculation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a frequency offset compensator according to first to fourth embodiments of the present invention;

FIG. 2 is a block diagram of a phase error estimating circuit in the frequency offset compensator according to the first embodiment;

FIG. 3 is a block diagram of a phase error estimating circuit in the frequency offset compensator according to the second embodiment;

FIG. 4 is a block diagram of a phase error estimating circuit in a frequency offset compensating apparatus according to a third embodiment;

FIG. 5 is a block diagram of a phase error estimating circuit in the frequency offset compensator of the fourth embodiment;

FIG. 6 is a block diagram illustrating a configuration of a conventional frequency offset compensator.

[Explanation of symbols]

 1, 2, 61, 62 input terminal 3, 63 baseband delay detection circuit 4, 68 decision circuit 5, compensation removal circuit 6, 64 phase error estimation circuit 7, 69 conversion circuit 8, 71 reference oscillator 9, 72 decoder 10, 73 Output terminals 21, 31, 41, 51, 65 Correlation calculation circuit 22, 43 Moving average circuit 23, 33, 44, 54 Estimation error correction circuit 32, 53, 66 Adaptive calculation circuit 42, 52 N-symbol addition circuit 67 Phase compensation Circuit 70 Average circuit

Claims (6)

[Claims] 1. A phase error estimating means for estimating a phase error due to a frequency offset and outputting a phase error compensation value, and a converting means for converting the phase error compensation value into frequency control data of a reference oscillator. A frequency offset compensator for controlling the frequency of the reference oscillator based on the phase error compensation value, comprising: a compensation removing means for removing the effect of the currently performed frequency offset compensation from the received data after detection; The error estimating means calculates the phase error compensation value for the initial frequency offset by using an averaging method based on a correlation value between the output of the compensation removing means and the result of the judgment of the received data. Frequency offset compensator. 2. The method according to claim 1, wherein the phase error estimating means calculates, for each symbol, a correlation value between conjugate complex data output from the compensation value removing means and data of a determination result and a complex multiplication value output from the compensation value removing means. , A moving average means for calculating a moving average with respect to the output of the correlation calculating means, and an estimation error correction for calculating the phase error compensation value from the output of the moving average means and outputting the compensation value for each symbol. The frequency offset compensating apparatus according to claim 1, further comprising means. 3. The method according to claim 1, wherein the phase error estimating means calculates, for each symbol, a correlation value between the conjugate complex data output from the compensation value removing means and the data of the determination result and a complex multiplication value output from the compensation value removing means. , An adaptive operation means for performing an averaging operation using an adaptive algorithm on the output of the correlation operation means, and calculating the phase error compensation value from the output of the adaptive operation means for each symbol. 2. The frequency offset compensator according to claim 1, further comprising: an estimation error correction unit that outputs the error to the frequency offset compensator. 4. The apparatus according to claim 1, wherein the phase error estimating means calculates, for each symbol, a correlation value between conjugate complex data output from the compensation value removing means and data of a determination result and a complex multiplication value output from the compensation value removing means. , An N symbol adding means for accumulating the output of the correlation calculating means for N symbols, a moving average means for calculating a moving average with respect to the output of the N symbol adding means, and an output of the moving average means. 2. The frequency offset compensating apparatus according to claim 1, further comprising: an estimation error correcting unit that calculates the phase error compensation value from and outputs the compensation value every N symbols. 5. The phase error estimating means calculates, for each symbol, a correlation value between conjugate complex data output from the compensation value removing means and data of a determination result and a complex multiplication value output from the compensation value removing means. , An N-symbol adding means for accumulating the output of the correlation calculating means for N symbols, an adaptive calculating means for performing an average calculation using an adaptive algorithm on the output of the N-symbol adding means, 2. The frequency offset compensator according to claim 1, further comprising: an estimation error correction unit that calculates the phase error compensation value from an output of the adaptive operation unit and outputs the calculated value for every N symbols. 6. The apparatus according to claim 2, wherein said estimation error correction means corrects the calculated phase error compensation value to a phase error compensation value in a compensable range when the calculated phase error compensation value exceeds a compensable range. 5. The frequency offset compensator according to item 1.