JPH10107398A - Structure of implementation on wiring board - Google Patents

Structure of implementation on wiring board

Info

Publication number
JPH10107398A
JPH10107398A JP25882296A JP25882296A JPH10107398A JP H10107398 A JPH10107398 A JP H10107398A JP 25882296 A JP25882296 A JP 25882296A JP 25882296 A JP25882296 A JP 25882296A JP H10107398 A JPH10107398 A JP H10107398A
Authority
JP
Japan
Prior art keywords
wiring
wiring board
electric circuit
board
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25882296A
Other languages
Japanese (ja)
Other versions
JP3740225B2 (en
Inventor
Masahiko Azuma
昌彦 東
Koichi Yamaguchi
浩一 山口
Masaya Kokubu
正也 國分
Hitoshi Kumadahara
均 隈田原
Kenichi Nagae
謙一 永江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP25882296A priority Critical patent/JP3740225B2/en
Priority to US08/939,563 priority patent/US6027791A/en
Publication of JPH10107398A publication Critical patent/JPH10107398A/en
Application granted granted Critical
Publication of JP3740225B2 publication Critical patent/JP3740225B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a structure of implementation on a wiring board of a high degree of reliability by which a firm and stable connection by soldering can be maintained for a long term between the wiring board and an outer electric circuit board, such as printed board. SOLUTION: A ceramic wiring board A is provided with multiple connecting terminals 4. An outer electric circuit board B is made of wiring conductor, formed and adhered to the surface of an insulator-containing organic resin. The ceramic wiring board A is placed on the outer electric circuit board B and wiring terminals 4 of the wiring board A and wiring conductor 11 are soldered to form a mounting structure for a wiring board. In this structure, the value of F=L×Δα/H<2> is 2000 or less. In the formula, L is the maximum spacing distance between two of multiple-connecting terminals mounted on the insulating board (mm). Δα is the difference in coefficient of thermal expansion at 40-400 deg.C between the insulating board and the outer electric circuit board in the wiring board (ppm/ deg.C). H is the height of solder between the wiring board and the outer electric circuit board (mm).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、有機樹脂を含む絶
縁体を備えた外部電気回路基板の表面に、配線基板、特
に大型の表面実装型の配線基板をロウ付けして実装する
のに適した実装構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for mounting a wiring board, particularly a large surface-mounting wiring board, on the surface of an external electric circuit board provided with an insulator containing an organic resin by brazing. The mounting structure.

【0002】[0002]

【従来技術】従来、配線基板は、絶縁基板の表面あるい
は内部にメタライズ配線層が配設された構造からなる。
また、この配線基板の代表的な例として、半導体素子、
特にLSI(大規模集積回路素子)等の半導体集積回路
素子を収容するための半導体素子収納用パッケージは、
一般にアルミナセラミックスからなる絶縁基板の表面に
半導体素子を収容するための凹部が形成され、また絶縁
基板の表面および内部には、タングステン、モリブデン
等の高融点金属粉末から成る複数個のメタライズ配線層
が配設され、凹部内に収納される半導体素子と電気的に
接続される。また、絶縁基板の下面または側面には、外
部電気回路基板と電気的に接続するための接続端子が備
えられ、この接続端子は、メタライズ配線層と電気的に
接続されている。
2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is disposed on the surface or inside of an insulating substrate.
Also, typical examples of the wiring board include a semiconductor element,
In particular, a semiconductor device housing package for housing a semiconductor integrated circuit device such as an LSI (Large Scale Integrated Circuit Device)
A concave portion for accommodating semiconductor elements is formed on the surface of an insulating substrate generally made of alumina ceramics, and a plurality of metallized wiring layers made of a refractory metal powder such as tungsten and molybdenum are formed on the surface and inside of the insulating substrate. It is provided and is electrically connected to the semiconductor element housed in the recess. In addition, a connection terminal for electrically connecting to an external electric circuit board is provided on a lower surface or a side surface of the insulating substrate, and the connection terminal is electrically connected to the metallized wiring layer.

【0003】そして、かかる半導体素子収納用パッケー
ジは、絶縁基板下面または側面に設けられた接続端子と
外部電気回路基板表面に形成された配線導体とを半田等
によりロウ付けして電気的に接続することにより実装さ
れる。
In such a package for housing a semiconductor element, connection terminals provided on the lower surface or side surfaces of the insulating substrate and wiring conductors formed on the surface of the external electric circuit board are electrically connected by soldering or the like. It is implemented by

【0004】一般に、半導体素子の集積度が高まるほ
ど、半導体素子に形成される電極数も増大するが、これ
に伴いこれを収納する半導体収納用パッケージにおける
端子数も増大することになる。ところが、電極数が増大
するに伴いパッケージ自体の寸法を大きくする必要があ
るが、それと同時に小型化も要求されるためパッケージ
における接続端子の密度を高くすることが必要となる。
In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases. As a result, the number of terminals in a semiconductor housing package for housing the same increases. However, as the number of electrodes increases, it is necessary to increase the dimensions of the package itself. At the same time, it is also required to reduce the size, so that the density of connection terminals in the package needs to be increased.

【0005】これまでのパッケージにおける接続端子の
構造としては、パッケージの下面にコバールなどの金属
ピンを接続したピングリッドアレイ(PGA)が最も一
般的であるが、表面実装型のパッケージとして、パッケ
ージの側面に導出されたメタライズ配線層にL字状の金
属部材がロウ付けされたクワッドフラットパッケージ
(QFP)、パッケージの4つの側面に電極パッドを備
えたリードピンのないリードレスチップキャリア(LC
C)、さらに絶縁基板の下面に半田からなる球状端子に
より構成したボールグリッドアレイ(BGA)等があ
り、これらの中でもBGAが最も高密度化が可能である
と言われている。
The structure of connection terminals in a conventional package is most commonly a pin grid array (PGA) in which metal pins such as Kovar are connected to the lower surface of the package. A quad flat package (QFP) in which an L-shaped metal member is brazed to a metallized wiring layer led out to the side, a leadless chip carrier (LC) without lead pins having electrode pads on four sides of the package
C) Further, there is a ball grid array (BGA) constituted by spherical terminals made of solder on the lower surface of the insulating substrate. Among them, it is said that the BGA can achieve the highest density.

【0006】このボールグリッドアレイ(BGA)は接
続端子を接続パッドに半田などのロウ材からなる球状端
子をロウ付けした端子により構成し、この球状端子を外
部電気回路基板の配線導体上に載置当接させ、しかる
後、前記端子を約250〜400℃の温度で加熱溶融
し、球状端子を配線導体に接合させることによって外部
電気回路基板上に実装することが行われている。このよ
うな実装構造により、半導体素子収納用パッケージの内
部に収容されている半導体素子はその各電極がメタライ
ズ配線層及び接続端子を介して外部電気回路に電気的に
接続される。
In this ball grid array (BGA), connection terminals are constituted by terminals in which spherical terminals made of a brazing material such as solder are soldered to connection pads, and the spherical terminals are mounted on wiring conductors of an external electric circuit board. After that, the terminals are heated and melted at a temperature of about 250 to 400 ° C., and the spherical terminals are bonded to a wiring conductor to be mounted on an external electric circuit board. With such a mounting structure, each electrode of the semiconductor element housed in the semiconductor element housing package is electrically connected to an external electric circuit via the metallized wiring layer and the connection terminal.

【0007】また、半導体素子収納用パッケージにおけ
る絶縁基板としては、最近では、低温焼成化、低誘電率
化および高電気伝導性の銅配線が可能なことから、絶縁
基板をガラスセラミック焼結体により構成することも提
案されている。
Further, recently, as an insulating substrate in a package for housing a semiconductor element, a glass ceramic sintered body is used as an insulating substrate because copper wiring having a low temperature firing, a low dielectric constant, and a high electric conductivity is possible. Configurations have also been proposed.

【0008】[0008]

【発明が解決しようとする課題】上記のパッケージにお
ける絶縁基板として従来より使用されているアルミナ、
ムライトなどのセラミックスは、200MPa以上の高
強度を有し、しかもメタライズ配線層などとの多層化技
術として信頼性の高い点で多用されているが、絶縁基板
がガラス−エポキシ樹脂複合材料、ガラス−ポリイミド
樹脂複合材料などの有機樹脂を含むプリント基板などの
外部電気回路基板に表面実装した場合、半導体素子の作
動時に発する熱が絶縁基板と外部電気回路基板の両方に
繰り返し印加されると、前記外部電気回路基板と絶縁基
板との熱膨張係数差が10ppm/℃以上と大きいため
に、熱応力が発生するという問題がある。
Alumina conventionally used as an insulating substrate in the above package,
Ceramics such as mullite have a high strength of 200 MPa or more and are often used as a multi-layer technology with metallized wiring layers because of their high reliability, but the insulating substrate is made of glass-epoxy resin composite material, glass- When surface mounted on an external electric circuit board such as a printed circuit board containing an organic resin such as a polyimide resin composite material, when heat generated during operation of the semiconductor element is repeatedly applied to both the insulating substrate and the external electric circuit board, the external Since the difference in thermal expansion coefficient between the electric circuit board and the insulating substrate is as large as 10 ppm / ° C. or more, there is a problem that thermal stress is generated.

【0009】この熱応力は、パッケージにおける端子数
が300未満と比較的少なかったり、接続端子がピンか
らなる場合、あるいはパッケージ自体のサイズが小さい
場合には、発生する熱応力も小さい。しかしながら、接
続端子数が300以上となったり、パッケージサイズが
大型化すると、発生する応力も増大する傾向にあり、半
導体素子の作動/停止によりこれがパッケージの外部電
気回路基板への半田実装部に繰り返し印加されると、パ
ッケージの接続端子の外周部、及び外部電気回路基板の
配線導体と接続端子との接合界面に応力が集中し、パッ
ケージにおいて接続端子が絶縁基板より剥離したり、接
続端子が外部電気回路基板の配線導体から剥離し、パッ
ケージの接続端子を外部電極回路の配線導体に長期にわ
たり安定に電気的接続できないという致命的な欠点を有
していた。特に、上記傾向は、前記QFP、LCCおよ
びBGA型等の表面実装型のパッケージにおいて顕著で
ある。
This thermal stress is relatively small when the number of terminals in the package is relatively small, less than 300, or when the connection terminals are composed of pins or when the size of the package itself is small. However, when the number of connection terminals becomes 300 or more, or when the package size is increased, the generated stress tends to increase, and this is repeated on the solder mounting portion of the package on the external electric circuit board by the operation / stop of the semiconductor element. When this voltage is applied, stress concentrates on the outer peripheral portion of the connection terminal of the package and on the joint interface between the wiring conductor of the external electric circuit board and the connection terminal. It has a fatal disadvantage that it is separated from the wiring conductor of the electric circuit board and the connection terminal of the package cannot be stably electrically connected to the wiring conductor of the external electrode circuit for a long period of time. In particular, the above tendency is remarkable in the surface mount type packages such as the QFP, LCC and BGA types.

【0010】従って、本発明は、半導体素子収納用パッ
ケージ等の配線基板を、絶縁体が有機樹脂を主体として
なる外部電気回路基板にロウ付けによって表面実装する
際に、強固に且つ長期にわたり安定した接続状態を維持
できる高信頼性の配線基板の実装構造を提供することを
目的とするものである。
Accordingly, the present invention provides a stable and stable circuit board for a long period of time when a wiring board such as a package for housing a semiconductor element is surface-mounted by brazing to an external electric circuit board whose insulator is mainly composed of an organic resin. It is an object of the present invention to provide a highly reliable wiring board mounting structure capable of maintaining a connection state.

【0011】[0011]

【課題を解決するための手段】本発明者らは、パッケー
ジ等の配線基板の外部電気回路基板への実装時において
発生する熱応力を緩和させる方法について種々検討を重
ねた結果、配線基板の最大長さ、配線基板の絶縁基板と
外部電気回路間のロウ付け高さ、および配線基板と外部
電気回路基板との熱膨張差を特定の関係になるように制
御することにより、半田に発生する応力を軽減し、長期
にわたり安定した実装が可能となることを見いだし、本
発明に至った。
Means for Solving the Problems The present inventors have conducted various studies on a method of alleviating the thermal stress generated when a wiring board such as a package is mounted on an external electric circuit board. Stress generated in the solder by controlling the length, the brazing height between the insulating board of the wiring board and the external electric circuit, and the thermal expansion difference between the wiring board and the external electric circuit so as to have a specific relationship And found that stable mounting can be performed over a long period of time, leading to the present invention.

【0012】即ち、本発明の配線基板の実装構造は、セ
ラミック絶縁基板と、該絶縁基板に配設されたメタライ
ズ配線層と、前記絶縁基板に取着され前記メタライズ配
線層と電気的に接続された接続端子とを具備する配線基
板を、少なくとも有機樹脂を含む絶縁体の表面に配線導
体が被着形成された外部電気回路基板上に載置し、前記
配線基板の接続端子と前記外部電気回路基板の配線導体
とをロウ付けして実装してなる配線基板の実装構造であ
って、下記数1
That is, the mounting structure of the wiring board according to the present invention comprises a ceramic insulating substrate, a metallized wiring layer provided on the insulating substrate, and a metallized wiring layer attached to the insulating substrate and electrically connected to the metallized wiring layer. A wiring board having a connection terminal and an external electric circuit board on which a wiring conductor is adhered and formed on an insulator containing at least an organic resin. A mounting structure of a wiring board, wherein the wiring conductor of the board is soldered and mounted.

【0013】[0013]

【数1】 (Equation 1)

【0014】で表されるF値が2000以下であること
を特徴とするものである。
The F value represented by the formula is 2,000 or less.

【0015】特に、前記配線基板における接続端子間の
最大離間距離が6mm以上であること、前記絶縁基板の
40〜400℃における熱膨張係数が8〜25ppm/
℃であること、前記外部電気回路基板の40〜400℃
における熱膨張係数が8〜28ppm/℃であることが
望ましい。
In particular, the maximum separation distance between connection terminals on the wiring board is 6 mm or more, and the coefficient of thermal expansion of the insulating substrate at 40 to 400 ° C. is 8 to 25 ppm /
℃, 40-400 ℃ of the external electric circuit board
Is preferably from 8 to 28 ppm / ° C.

【0016】また、前記絶縁基板としては、特に、配線
基板における絶縁基板が、ガラスセラミック焼結体から
なり、具体的には、Li2 Oを5〜30重量%含有する
リチウム珪酸ガラス20〜80体積%と、フォルステラ
イト、クリストバライトおよびクォーツの少なくとも1
種を含むフィラー80〜20体積%とからなる混合物を
成形し、焼成したものであることが望ましい。
As the insulating substrate, in particular, the insulating substrate in the wiring substrate is formed of a glass ceramic sintered body, specifically, lithium silicate glass containing Li 2 O in an amount of 5 to 30% by weight. % By volume and at least one of forsterite, cristobalite and quartz
It is desirable that the mixture be made of a mixture comprising 80 to 20% by volume of a filler containing seeds and fired.

【0017】[0017]

【発明の実施の形態】以下、本発明を一実施例を示す添
付図面に基づき詳細に説明する。図1及び図2は、本発
明の一例を示す図であり、セラミック絶縁基板の表面あ
るいは内部にメタライズ配線層が配設された、いわゆる
配線基板を基礎的構造とするもので、図1は、本発明に
おける配線基板の一例としてBGA型パッケージと、そ
の実装構造を示すものであり、AはBGA型パッケー
ジ、Bは外部電気回路基板である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the accompanying drawings showing an embodiment. FIGS. 1 and 2 are views showing an example of the present invention, which is based on a so-called wiring board having a metallized wiring layer disposed on the surface or inside of a ceramic insulating substrate, and FIG. 1 shows a BGA type package and its mounting structure as an example of a wiring board in the present invention, wherein A is a BGA type package, and B is an external electric circuit board.

【0018】図1において、パッケージAは、セラミッ
ク絶縁基板1と蓋体2とメタライズ配線層3と接続端子
4およびパッケージの内部に収納される半導体素子5に
より構成され、絶縁基板1に形成されたキャビティ6内
に半導体素子5が収納され、キャビティ6は、蓋体2に
よって気密に封止されている。
In FIG. 1, a package A includes a ceramic insulating substrate 1, a lid 2, a metallized wiring layer 3, connection terminals 4, and a semiconductor element 5 housed inside the package. The semiconductor element 5 is housed in the cavity 6, and the cavity 6 is hermetically sealed by the lid 2.

【0019】また、絶縁基板1の下面には接続端子4が
形成され、絶縁基板1の表面および内部に配設されたメ
タライズ配線層3と電気的に接続されている。この図1
のBGA型パッケージにおいては、接続端子4は、例え
ば、絶縁基板1の下面に形成された多数の電極パッド7
と半田(錫−鉛合金)などの高融点ロウ材からなるボー
ル状の端子8が低融点半田9によって取着された構造か
らなる。
A connection terminal 4 is formed on the lower surface of the insulating substrate 1 and is electrically connected to the metallized wiring layer 3 disposed on the surface and inside of the insulating substrate 1. This figure 1
In the BGA type package, the connection terminals 4 are formed, for example, by a large number of electrode pads 7 formed on the lower surface of the insulating substrate 1.
And a ball-shaped terminal 8 made of a high melting point brazing material such as solder (tin-lead alloy).

【0020】一方、外部電気回路基板Bは、いわゆるプ
リント基板からなり、ガラス−エポキシ樹脂、ガラス−
ポリイミド樹脂複合材料などの有機樹脂を含む材料から
なる絶縁体10の表面に、Cu、Au、Al、Ni、P
b−Snなどの金属からなる配線導体11が被着形成さ
れたものであり、以下、単にプリント基板と称する場合
もある。
On the other hand, the external electric circuit board B is made of a so-called printed board, and is made of glass-epoxy resin, glass-
Cu, Au, Al, Ni, P on the surface of the insulator 10 made of a material containing an organic resin such as a polyimide resin composite material.
The wiring conductor 11 made of a metal such as b-Sn is adhered and formed, and may hereinafter be simply referred to as a printed circuit board.

【0021】上記BGA型パッケージAを上記プリント
基板Bに実装するには、パッケージAの絶縁基板1下面
のボール状接続端子8をプリント基板Bの配線導体11
上に載置当接させ、しかる後、低融点半田などのロウ材
12によってプリント基板B上に実装される。
To mount the BGA type package A on the printed circuit board B, the ball-shaped connection terminals 8 on the lower surface of the insulating substrate 1 of the package A are connected to the wiring conductors 11 of the printed circuit board B.
It is mounted on the printed circuit board B with a brazing material 12 such as low melting point solder.

【0022】本発明によれば、図1に示されるような実
装構造において、半導体素子収納用パッケージ等の配線
基板Aの前記絶縁基板に取着された複数の接続端子のう
ち、2つの接続端子間の最大離間距離をL(mm)、配
線基板Aにおける絶縁基板1と外部電気回路基板Bとの
熱膨張係数差をΔα(ppm/℃)、絶縁基板1と外部
電気回路基板B間のロウ付け高さをH(mm)とした
時、下記数1
According to the present invention, in the mounting structure as shown in FIG. 1, two connection terminals out of the plurality of connection terminals attached to the insulating substrate of the wiring board A such as a package for housing semiconductor elements. L (mm), the difference in thermal expansion coefficient between the insulating substrate 1 and the external electric circuit board B in the wiring board A is Δα (ppm / ° C.), and the solder between the insulating substrate 1 and the external electric circuit board B When the mounting height is H (mm),

【0023】[0023]

【数1】 (Equation 1)

【0024】で表されるF値が2000以下であること
が重要である。
It is important that the F value represented by the following is not more than 2000.

【0025】ここで、2つの接続端子間の最大離間距離
Lとは、配線基板の絶縁基板に取着された複数の接続端
子のうち、1つの接続端子と他の接続端子との離間距離
の最大値であり、例えば、接続端子群のうちの端部に取
着された接続端子と、他方の端部に取着された接続端子
間の離間距離であり、より具体的には、図2(a)に示
すように、接続端子群が、四角形状に配列された場合に
は、その四角形状の対角線長さに相当する。また、図2
(b)に示すような、複雑形状に配列される場合には、
図2(b)に示すように、最も離れた端子間距離が相当
する。
Here, the maximum separation distance L between two connection terminals is defined as the separation distance between one connection terminal and another connection terminal among a plurality of connection terminals attached to the insulating substrate of the wiring board. The maximum value is, for example, the separation distance between the connection terminal attached to one end of the connection terminal group and the connection terminal attached to the other end. More specifically, FIG. As shown in (a), when the connection terminal group is arranged in a square shape, it corresponds to the diagonal length of the square shape. FIG.
When arranged in a complicated shape as shown in (b),
As shown in FIG. 2B, the farthest distance between terminals corresponds.

【0026】また、ロウ付け高さHとは、図3の実装部
の拡大図に示すように、(a)の図1の配線基板の実装
構造においては、外部電気回路基板B表面の配線導体1
1の表面から、配線基板Aにおける電極パッド7の表面
までの距離である。また、(b)に、他の接続端子構造
を示した。この(b)によれば、配線基板Aの下面に凹
部13が形成され、その凹部13内に電極パッド7が形
成され、その凹部13内にボール状端子8が設置された
構造からなる。この場合、ロウ付け高さHは、外部電気
回路基板B表面の配線導体11の表面から、配線基板A
の絶縁基板1の底面までの距離となる。なお、上記
(a)(b)の構成において、ボール状端子8が存在す
ることなくロウ材のみで実装される場合や、ボール状端
子8に代わり、柱状端子等を用いる場合も同様な考え方
にてロウ付け高さHは決定される。
As shown in the enlarged view of the mounting portion in FIG. 3, the brazing height H is the wiring conductor on the surface of the external electric circuit board B in the mounting structure of the wiring board in FIG. 1
1 to the surface of the electrode pad 7 on the wiring board A. (B) shows another connection terminal structure. According to (b), the recess 13 is formed on the lower surface of the wiring board A, the electrode pad 7 is formed in the recess 13, and the ball-shaped terminal 8 is provided in the recess 13. In this case, the brazing height H is determined from the surface of the wiring conductor 11 on the surface of the external electric circuit board B to the wiring board A.
To the bottom surface of the insulating substrate 1. In the above configurations (a) and (b), the same concept is applied to a case where the ball-shaped terminal 8 is mounted without using the brazing material alone or a case where a pillar-shaped terminal or the like is used instead of the ball-shaped terminal 8. The brazing height H is determined.

【0027】配線基板Aの絶縁基板1と外部電気回路基
板Bとの間に発生する応力は、前記数1で示すように、
配線基板の最大長さLおよび両者の熱膨張係数差Δαが
大きいほど大きくなる。これは最大長さと熱膨張係数差
が大きくなると温度変化によって絶縁基板1と外部電気
回路基板Bとの熱膨張もしくは収縮差が大きくなるため
である。
The stress generated between the insulating board 1 of the wiring board A and the external electric circuit board B is expressed by the following equation (1).
The larger the maximum length L of the wiring board and the difference in thermal expansion coefficient Δα between the two, the larger it becomes. This is because, when the difference between the maximum length and the thermal expansion coefficient increases, the difference in thermal expansion or contraction between the insulating substrate 1 and the external electric circuit board B increases due to a temperature change.

【0028】しかし、絶縁基板1と外部電気回路基板B
とのロウ付け高さHを高くすることでこの応力は減少で
きる。つまり、絶縁基板1の最大長さL及び絶縁基板と
外部電気回路基板との熱膨張係数差Δαがある程度大き
くても両者の間のロウ付け高さを調節することで信頼性
を得ることができるのである。前記数1は、要素に基づ
く高い信頼性が得られるための関係を導き出したもので
ある。
However, the insulating substrate 1 and the external electric circuit board B
By increasing the brazing height H, the stress can be reduced. That is, even if the maximum length L of the insulating substrate 1 and the thermal expansion coefficient difference Δα between the insulating substrate and the external electric circuit board are large to some extent, reliability can be obtained by adjusting the brazing height between the two. It is. Equation (1) derives a relationship for obtaining high reliability based on the elements.

【0029】従って、配線基板の最大長さL、外部電気
回路基板との熱膨張係数差Δα、絶縁基板と外部電気回
路基板間のロウ付け高さHが上記式の範囲を満たさない
と、ロウ付け部に作用する応力が大きくなり、電気的接
続状態が経時的に悪化することを防止することができな
くなるのである。
Therefore, if the maximum length L of the wiring board, the difference in thermal expansion coefficient Δα between the wiring board and the external electric circuit board, and the brazing height H between the insulating board and the external electric circuit board do not satisfy the range of the above formula, As a result, the stress acting on the attachment portion increases, and it becomes impossible to prevent the electrical connection state from deteriorating with time.

【0030】特に、本発明の実装構造によれば、前記数
1で表されるF値が1000以下、さらには500以下
であることが望ましい。また、熱膨張差に起因する応力
の影響が大きくなる接続端子間の最大離間距離が6mm
以上、特に10mm以上、さらには12mm以上の配線
基板を40〜400℃における熱膨張係数が8〜28p
pm/℃の外部電気回路基板への実装に好適である。
In particular, according to the mounting structure of the present invention, it is desirable that the F value represented by the above equation 1 is 1000 or less, more preferably 500 or less. In addition, the maximum separation distance between the connection terminals at which the influence of the stress due to the difference in thermal expansion becomes large is 6 mm.
As described above, in particular, a wiring board having a length of 10 mm or more, and more preferably a length of 12 mm or more, has a thermal expansion coefficient of 8 to 28 p at 40 to 400 ° C.
It is suitable for mounting on an external electric circuit board at pm / ° C.

【0031】本発明の好適な態様によれば、配線基板の
セラミック絶縁基板は、40〜400℃における熱膨張
係数を8〜25ppm/℃として、外部電気回路基板と
の熱膨張差Δαが絶対値で0〜5ppm/℃であるとと
もに、配線基板の外部電気回路基板へのロウ付け高さH
が0.1〜1.2mmであることが望ましい。これは、
熱膨張係数差が大きい場合、発生する応力がロウ付け高
さへの依存性が高くなるために、ロウ付け高さの微妙な
調整が必要となるのに対して、熱膨張係数差を小さくす
ることにより、発生する応力を小さくできるために、前
記F値を前記範囲に制御する上で、ロウ付け高さの許容
範囲を拡大することができるためである。なお、ロウ付
け高さHが上記範囲を逸脱すると、ロウ付け部におい
て、断線、半田間のショートなどの実装時の不良が発生
しやすくなるためである。
According to a preferred aspect of the present invention, the ceramic insulating substrate of the wiring board has a thermal expansion coefficient of 8 to 25 ppm / ° C. at 40 to 400 ° C. and an absolute value of a thermal expansion difference Δα from an external electric circuit board. And the soldering height H of the wiring board to the external electric circuit board.
Is desirably 0.1 to 1.2 mm. this is,
When the difference in thermal expansion coefficient is large, the generated stress is highly dependent on the brazing height, so that fine adjustment of the brazing height is required, whereas the thermal expansion coefficient difference is reduced. Thereby, since the generated stress can be reduced, the allowable range of the brazing height can be expanded in controlling the F value within the range. If the brazing height H deviates from the above range, mounting failures such as disconnection and short-circuit between solders are likely to occur at the brazing portion.

【0032】なお、ロウ付け高さHを調整する方法とし
ては、図3において、電極パッド7にボール状端子8を
ロウ付けする場合のロウ材9の取付け高さを調整した
り、、配線基板と外部電気回路基板との実装時に適当な
高さのスペーサーを設置して調整する方法、ボール状端
子8や柱状端子などの大きさ(例えば、球径)等によっ
て調整する方法などが採用できる。
As a method of adjusting the brazing height H, the mounting height of the brazing material 9 when brazing the ball-shaped terminals 8 to the electrode pads 7 in FIG. A method of installing and adjusting a spacer having an appropriate height when mounting the semiconductor device and an external electric circuit board, and a method of adjusting the size (for example, a ball diameter) of the ball-shaped terminals 8 and the column-shaped terminals can be adopted.

【0033】配線基板におけるセラミックス絶縁基板を
構成する好適な絶縁材料としては、前記F値が上記の範
囲を満足するものであれば、Al2 3 、AlN、Zr
2、ムライト、Si3 4 、SiC等を主体とするセ
ラミックス、ガラス、ガラスセラミックス等の公知の絶
縁材料が用いることができる。
As a preferable insulating material for forming the ceramic insulating substrate in the wiring board, Al 2 O 3 , AlN, Zr as long as the F value satisfies the above range.
Known insulating materials such as ceramics mainly composed of O 2 , mullite, Si 3 N 4 , and SiC, glass, and glass ceramics can be used.

【0034】これらの中でも、配線基板として、表面お
よび内部に配設されたメタライズ配線層を金、銅、銀の
うちの少なくとも1種により構成し、且つ絶縁基板と同
時焼成によって作製できるものであることが望ましい。
かかる点で、絶縁基板は1000℃以下で焼成可能であ
ることが望まれ、例えば、1000℃以下で焼成可能な
ガラス、またはガラスセラミックスが最も好適である。
Among these, the metallized wiring layer disposed on the surface and inside is made of at least one of gold, copper, and silver, and can be manufactured by simultaneous firing with the insulating substrate. It is desirable.
From this point, it is desired that the insulating substrate can be fired at 1000 ° C. or lower, and for example, glass or glass ceramics that can be fired at 1000 ° C. or lower is most preferable.

【0035】また、ガラスまたはガラスセラミックスと
しては、ホウケイ酸ガラス、ソーダ石灰ガラスなどのガ
ラスや、これらのガラスにフィラー成分として、Al2
3、ZrO2 、SiO2 、MgO、CaO、AlNな
どを配合したガラスセラミックス等が挙げられる。
Examples of the glass or glass ceramic include borosilicate glass and soda-lime glass and the like, and Al 2 O 3 as a filler component in these glasses.
Glass ceramics containing O 3 , ZrO 2 , SiO 2 , MgO, CaO, AlN, and the like are included.

【0036】また、かかる絶縁基板として40〜400
℃における熱膨張係数が8〜25ppm/℃のガラスセ
ラミック材料としては、Li2 Oを5〜30重量%含有
する結晶性リチウム珪酸ガラスを20〜80体積%と、
少なくともフォルステライトとクリストバライトとを含
むフィラー成分80〜20体積%とからなる混合物を成
形し、焼成したガラスセラミック焼結体が好適に使用さ
れる。
Further, as such an insulating substrate, 40 to 400
As a glass ceramic material having a thermal expansion coefficient of 8 to 25 ppm / ° C. at 20 ° C., 20 to 80% by volume of a crystalline lithium silicate glass containing 5 to 30% by weight of Li 2 O;
A glass ceramic sintered body obtained by molding and firing a mixture comprising at least 80 to 20% by volume of a filler component containing at least forsterite and cristobalite is preferably used.

【0037】本発明によれば、結晶性リチウム珪酸ガラ
スを上記の範囲で配合することにより、1000℃以下
の温度で焼成でき、焼結後の焼結体のヤング率が200
GPa以下、熱膨張係数8ppm/℃以上のガラスセラ
ミックスを得ることができる。
According to the present invention, by blending the crystalline lithium silicate glass in the above range, it can be fired at a temperature of 1000 ° C. or less, and the sintered body after sintering has a Young's modulus of 200%.
A glass ceramic having GPa or less and a thermal expansion coefficient of 8 ppm / ° C. or more can be obtained.

【0038】かかるガラスセラミック材料について以下
に具体的に説明する。用いる結晶性リチウム珪酸ガラス
としては、Li2 Oを5〜30重量%の割合で含有する
とともに、SiO2 を60〜85重量%含み、Li2
とSiO2 の合量が65〜95重量%であり、残部がA
2 3 、アルカリ土類酸化物、アルカリ金属酸化物、
ZnO、P2 5 等から構成されるものが好適である。
The glass ceramic material will be specifically described below. As the crystalline lithium silicate glass to be used, Li 2 O is contained at a ratio of 5 to 30% by weight, SiO 2 is contained at a ratio of 60 to 85% by weight, and Li 2 O is used.
And the total amount of SiO 2 is 65 to 95% by weight, and the balance is A
l 2 O 3 , alkaline earth oxides, alkali metal oxides,
Those composed of ZnO, P 2 O 5 and the like are preferable.

【0039】この結晶性リチウム珪酸ガラスの軟化点は
420〜460℃であることが望ましい。また、屈伏点
は400℃〜800℃、特に400〜650℃であるこ
とが成形用有機バインダーを効率的に除去できるととも
に、銅との同時焼結性を高める点で望ましい。
The softening point of the crystalline lithium silicate glass is desirably 420 to 460 ° C. Further, the yield point is desirably 400 ° C. to 800 ° C., particularly preferably 400 ° C. to 650 ° C., in order to efficiently remove the molding organic binder and to enhance co-sintering with copper.

【0040】一方、結晶性リチウム珪酸ガラスとともに
配合されるフィラー成分としては、少なくともフォルス
テライト、クリストバライトを含むことが、熱膨張係数
を前記範囲に制御する上で好適である。また、フィラー
の種類によってヤング率や熱膨張係数を制御することも
可能であって、その他のフィラー成分としては、クォー
ツ(SiO2 )、トリジマイト(SiO2 )、クリスト
バライト(SiO2 )、フォルステライト(2MgO・
SiO2 )、スピネル(MgO・Al2 3 )、ウォラ
ストナイト(CaO・SiO2 )、モンティセラナイト
(CaO・MgO・SiO2 )、ネフェリン(Na2
・Al2 3 ・SiO2 )、リチウムシリケート(Li
2 O・SiO2 )、ジオプサイド(CaO・MgO・2
SiO2)、メルビナイト(3CaO・MgO・2Si
2 )、アケルマイト(2CaO・MgO・2Si
2 )、マグネシア(MgO)、アルミナ(Al
2 3 )、カーネギアイト(Na2 O・Al2 3 ・2
SiO2 )、エンスタタイト(MgO・SiO2 )、ホ
ウ酸マグネシウム(2MgO・B2 3 )、セルシアン
(BaO・Al2 3 ・2SiO2 )、B2 3 ・2M
gO・2SiO2 、ガーナイト(ZnO・Al
2 3 )、ペタライト(LiAlSi4 10)が挙げら
れる。
On the other hand, it is preferable to include at least forsterite and cristobalite as the filler component blended with the crystalline lithium silicate glass in order to control the thermal expansion coefficient within the above range. It is also possible to control the Young's modulus and the coefficient of thermal expansion depending on the type of filler, and as other filler components, quartz (SiO 2 ), tridymite (SiO 2 ), cristobalite (SiO 2 ), forsterite ( 2MgO ・
SiO 2), spinel (MgO · Al 2 O 3) , wollastonite (CaO · SiO 2), Monty Sera Knight (CaO · MgO · SiO 2) , nepheline (Na 2 O
・ Al 2 O 3 .SiO 2 ), lithium silicate (Li
2 O.SiO 2 ), diopside (CaO.MgO.2)
SiO 2 ), melvinite (3CaO.MgO.2Si)
O 2 ), Akermite (2CaO.MgO.2Si)
O 2 ), magnesia (MgO), alumina (Al
2 O 3), Kanegiaito (Na 2 O · Al 2 O 3 · 2
SiO 2 ), enstatite (MgO.SiO 2 ), magnesium borate (2MgO.B 2 O 3 ), celsian (BaO.Al 2 O 3 .2SiO 2 ), B 2 O 3 .2M
gO.2SiO 2 , garnite (ZnO.Al
2 O 3 ) and petalite (LiAlSi 4 O 10 ).

【0041】この結晶性ガラスとフィラーとの混合物を
用いて、配線基板を作製するには、適当な成形用有機樹
脂バインダーを添加した後、所望の成形手段、例えば、
ドクターブレード、圧延法、金型プレス等によりシート
状に成形する。
In order to prepare a wiring board using the mixture of the crystalline glass and the filler, an appropriate molding organic resin binder is added, and then a desired molding means, for example,
It is formed into a sheet by a doctor blade, a rolling method, a mold press or the like.

【0042】そして、このシート状成形体の表面に銅や
金などのメタライズペーストをスクリーン印刷法等によ
って印刷し、また、場合によっては、前記グリーンシー
トに適当な打ち抜き加工してスルーホールを形成し、こ
のホール内にもメタライズペーストを充填する。そして
これらのグリーンシートを複数枚積層し焼成する。
Then, a metallizing paste such as copper or gold is printed on the surface of the sheet-like molded body by a screen printing method or the like, and in some cases, the green sheet is appropriately punched to form through holes. This hole is also filled with a metallizing paste. Then, a plurality of these green sheets are laminated and fired.

【0043】焼成にあたっては、まず、成形のために配
合したバインダー成分を除去する。
In firing, first, the binder component blended for molding is removed.

【0044】バインダーの除去は、700℃前後の大気
雰囲気中で行われるが、配線導体としてCuを用いる場
合には、水蒸気を含有する100〜700℃の窒素雰囲
気中で行われる。この時、成形体の収縮開始温度は70
0〜850℃程度であることが望ましく、かかる収縮開
始温度がこれより低いとバインダーの除去が困難となる
ため、成形体中の結晶化ガラスの特性、特に屈伏点を前
述したように制御することが必要となる。
The removal of the binder is performed in an air atmosphere at about 700 ° C. When Cu is used as the wiring conductor, the removal is performed in a nitrogen atmosphere containing water vapor at 100 to 700 ° C. At this time, the shrinkage start temperature of the molded body is 70
It is desirable that the temperature is about 0 to 850 ° C., and if the shrinkage onset temperature is lower than this, it is difficult to remove the binder. Is required.

【0045】焼成は、850℃〜1050℃の酸化性雰
囲気中で行われ、これにより相対密度90%以上まで緻
密化される。この時の焼成温度が850℃より低いと緻
密化することができず、1050℃を越えるとメタライ
ズ配線層との同時焼成でメタライズ層が溶融してしま
う。
The calcination is performed in an oxidizing atmosphere at 850 ° C. to 1050 ° C., whereby the relative density is increased to 90% or more. If the firing temperature at this time is lower than 850 ° C., densification cannot be achieved, and if it exceeds 1050 ° C., the metallized layer is melted by simultaneous firing with the metallized wiring layer.

【0046】このようにして作製された配線基板の絶縁
基板を構成するガラスセラミック焼結体中には、フィラ
ーとして添加したフォルステライトやクリストバライト
等の結晶相や、これらフィラー成分に基づくエンスタタ
イト等の結晶相、さらには結晶性ガラスから析出したリ
チウムシリケート結晶相が存在する。その他、結晶性ガ
ラスとフィラーとの反応により生成した結晶相も存在す
る場合がある。そして、これらの結晶相の粒界には、微
量のガラス相が存在する場合もある。これらの熱膨張係
数の大きい結晶相を析出させることにより、高熱膨張係
数を有するガラスセラミック焼結体を作製することがで
きる。
The glass-ceramic sintered body constituting the insulating substrate of the wiring board thus manufactured contains a crystalline phase such as forsterite or cristobalite added as a filler or an enstatite or the like based on these filler components. There is a crystal phase and further a lithium silicate crystal phase precipitated from the crystalline glass. In addition, there may be a crystal phase generated by the reaction between the crystalline glass and the filler. Then, a small amount of a glass phase may be present at the grain boundaries of these crystal phases. By precipitating a crystal phase having a large thermal expansion coefficient, a glass ceramic sintered body having a high thermal expansion coefficient can be produced.

【0047】本発明によれば、上記のように、ガラス−
エポキシ樹脂基板などのプリント基板からなる外部電気
回路に対する配線基板の実装構造において、配線基板と
外部電気回路基板間に発生する応力を低減し、その結
果、その応力による配線基板の接続端子と外部電気回路
の配線導体との接続不良が発生するのを防止することが
でき、これによって例えば、パッケージ内に収納された
半導体素子と外部電気回路基板とを長期間にわたり正確
に、且つ強固に電気的接続させることが可能となる。
According to the present invention, as described above,
In the mounting structure of a wiring board for an external electric circuit composed of a printed board such as an epoxy resin board, the stress generated between the wiring board and the external electric circuit board is reduced, and as a result, the connection terminals of the wiring board and the external electric circuit due to the stress are reduced. It is possible to prevent the occurrence of a connection failure with the wiring conductor of the circuit, whereby, for example, the semiconductor element housed in the package and the external electric circuit board are accurately and firmly electrically connected for a long period of time. It is possible to do.

【0048】[0048]

【実施例】【Example】

実施例1 表1、2に示す絶縁基板を形成する各種セラミック材料
について、表1、2の焼成条件で焼成して5×4×40
mmの形状の焼結体を作製し、各焼結体について40〜
400℃における熱膨張係数を測定し表1、2に示し
た。
Example 1 Various ceramic materials for forming the insulating substrates shown in Tables 1 and 2 were fired under the firing conditions in Tables 1 and 2 to obtain 5 × 4 × 40.
mm sintered body was prepared, and for each sintered body, 40 to
The thermal expansion coefficients at 400 ° C. were measured and are shown in Tables 1 and 2.

【0049】また、表1、2に示す各種セラミック材料
を用いて、表1、2の材質からなるメタライズ金属を含
むペーストを塗布、およびスルーホールを形成し、ま
た、基板の下面にスルーホールに接続する箇所にCuも
しくはWのメタライズからなる接続パッドを形成し、表
1、2の条件でメタライズ配線層、スルーホール、電極
パッドとともに同時焼成して配線基板を作製した。そし
て、接続パッドにNiメッキを施した後に、この電極パ
ッドに高融点半田(Pb90重量%−Sn10重量%)
からなるボール状接続端子を低融点半田(Pb40重量
%−Sn60重量%)によって取り着けた。なお、接続
端子は、1cm2 当たり30端子の密度で図3(a)に
示すように下面全体に形成した。また、接続端子におけ
る最大離間距離が16mmの116端子、および71m
mの732端子が取着された配線基板を作製した。な
お、配線基板の厚みはすべて1.6mmとした。
Also, using various ceramic materials shown in Tables 1 and 2, a paste containing a metallized metal made of the materials shown in Tables 1 and 2 is applied, and a through hole is formed. A connection pad made of Cu or W metallization was formed at the place to be connected, and simultaneously baked together with the metallized wiring layer, through hole and electrode pad under the conditions shown in Tables 1 and 2, to produce a wiring board. Then, after the connection pads are plated with Ni, a high melting point solder (Pb 90% by weight-Sn 10% by weight) is applied to the electrode pads.
Ball-shaped connection terminals made of low melting point solder (Pb 40% by weight-Sn 60% by weight). The connection terminals were formed on the entire lower surface at a density of 30 terminals per 1 cm 2 as shown in FIG. Also, 116 terminals having a maximum separation distance of 16 mm at the connection terminals, and 71 m
A wiring board to which m 732 terminals were attached was fabricated. In addition, the thickness of all the wiring boards was 1.6 mm.

【0050】一方、外部電気回路基板として、ガラス−
エポキシ基板からなる40〜400℃における熱膨張係
数が13ppm/℃の絶縁体の表面に銅箔からなる配線
導体が形成されたプリント基板を準備した。
On the other hand, as an external electric circuit board, glass
A printed circuit board was prepared in which a wiring conductor made of copper foil was formed on the surface of an insulator made of an epoxy substrate having a thermal expansion coefficient of 13 ppm / ° C. at 40 to 400 ° C.

【0051】そして、上記の配線基板を上記プリント基
板の上の配線導体とパッケージ用絶縁基板の接続端子が
接続されるように位置合わせし、前記低融点半田を用い
て配線基板をプリント基板表面に実装した。なお、この
時のロウ付け高さHを、ボール状端子の電極パッドへの
半田による取付高さを変えることと、高融点半田からな
るボールの径を変えて調整した。
Then, the wiring board is aligned so that the wiring conductors on the printed board and the connection terminals of the package insulating board are connected, and the wiring board is mounted on the printed board surface using the low melting point solder. Implemented. The brazing height H at this time was adjusted by changing the mounting height of the ball-shaped terminals to the electrode pads by soldering and by changing the diameter of the ball made of high melting point solder.

【0052】(熱サイクル試験)次に、上記のようにし
てパッケージ基板をプリント基板表面に実装したものを
大気の雰囲気にて−40℃と125℃の各温度に制御し
た恒温槽に試験サンプルを15分/15分の保持を1サ
イクルとして最高1000サイクル繰り返した。
(Thermal Cycle Test) Next, the test sample obtained by mounting the package substrate on the surface of the printed circuit board as described above was placed in a thermostat controlled at -40 ° C. and 125 ° C. in the atmosphere of the air. Up to 1000 cycles were repeated with 15 minutes / 15 minutes holding as one cycle.

【0053】そして、各サイクル毎にプリント基板の配
線導体とパッケージ用基板との電気抵抗を測定し電気抵
抗に変化が現れるまでのサイクル数を表1、2に示し
た。
The electrical resistance between the wiring conductor of the printed circuit board and the package substrate was measured for each cycle, and the number of cycles until the electrical resistance changed was shown in Tables 1 and 2.

【0054】[0054]

【表1】 [Table 1]

【0055】[0055]

【表2】 [Table 2]

【0056】表1、2より明らかなように、絶縁基板の
最大長さL,外部電気回路基板との熱膨張係数差Δα、
絶縁基板と外部電気回路基板間のロウ付け高さHで関係
づけられたF値が2000以下の試料は、いずれも10
00サイクルまで抵抗変化は全く認められず、極めて安
定で良好な電気的接続状態を維持できた。しかし、F値
が2000よりも小さい試料では1000サイクル未満
で抵抗変化が検出され、実装後の信頼性に欠けることが
わかった。
As is clear from Tables 1 and 2, the maximum length L of the insulating substrate, the difference in thermal expansion coefficient Δα from the external electric circuit board,
Samples having an F value of 2000 or less related by the brazing height H between the insulating substrate and the external electric circuit board are all 10 samples.
No change in resistance was observed at all until the 00th cycle, and an extremely stable and favorable electrical connection state could be maintained. However, in a sample having an F value smaller than 2,000, a change in resistance was detected in less than 1,000 cycles, and it was found that reliability after mounting was lacking.

【0057】実施例2 ガラスセラミック焼結体として、表3に示すように、リ
チウム珪酸ガラス(組成:74重量%SiO2 、14重
量%Li2 O、4重量%Al2 3 、2重量%K2 O、
2重量%P2 5 、2重量%Na2 O、2重量%Zn
O、屈伏点480℃、40〜400℃における熱膨張係
数10.3ppm/℃)とアルミナの体積比を変えて混
合し、実施例1と同様にして成形し、脱バインダー処理
し、焼成した。そして、上記のようにして得られた焼結
体に対して実施例1と同様にして、熱膨張係数を確認し
た。
Example 2 As a glass ceramic sintered body, as shown in Table 3, lithium silicate glass (composition: 74 wt% SiO 2 , 14 wt% Li 2 O, 4 wt% Al 2 O 3 , 2 wt% K 2 O,
2% by weight P 2 O 5 , 2% by weight Na 2 O, 2% by weight Zn
O, a thermal expansion coefficient at a deformation point of 480 ° C. and 40 to 400 ° C., and a volume ratio of alumina were changed and mixed, molded in the same manner as in Example 1, debindered, and fired. Then, the thermal expansion coefficient of the sintered body obtained as described above was confirmed in the same manner as in Example 1.

【0058】また、実施例1と同様にしてメタライズ配
線層としてCuを用いて配線基板を作成し、これを実施
例1と同じガラス−エポキシ基板に実装し、実装時の熱
サイクル試験を行いプリント基板とパッケージ基板との
電気抵抗の変化を調べた。
Further, a wiring board was prepared by using Cu as the metallized wiring layer in the same manner as in Example 1, mounted on the same glass-epoxy substrate as in Example 1, and subjected to a thermal cycle test during mounting, followed by printing. The change in electrical resistance between the substrate and the package substrate was examined.

【0059】[0059]

【表3】 [Table 3]

【0060】表3より明らかなように、絶縁基板の最大
長さL、外部電気回路基板との熱膨張係数差Δα、絶縁
基板と外部電気回路基板間のロウづけ高さHで関係づけ
られたF値が2000以下の試料は、いずれも1000
サイクルまで抵抗変化は全く認められず、極めて安定で
良好な電気的接続状態を維持できた。しかし、F値が2
000よりも小さい試料では1000サイクル未満で接
続部の破壊による電気抵抗の変化が見られた。
As is clear from Table 3, the maximum length L of the insulating substrate, the difference in thermal expansion coefficient Δα from the external electric circuit board, and the brazing height H between the insulating substrate and the external electric circuit board were related. Samples with an F value of 2000 or less were all 1000
No change in resistance was observed at all until the cycle, and an extremely stable and good electrical connection state could be maintained. However, if the F value is 2
In a sample smaller than 000, a change in electric resistance due to breakage of the connection portion was observed in less than 1000 cycles.

【0061】実施例3 表4、5に示すようにリチウム珪酸ガラス(組成:78
重量%SiO2 、10重量%Li2 O、4重量%Al2
3 、4重量%K2 O、2重量%P2 5 、2重量%N
2 O、屈伏点480℃、40〜400℃における熱膨
張係数10.3ppm/℃)と、フィラーとしてフォル
ステライト、クリストバライト、ペタライト、ネフェリ
ン、リチウムシリケートを用いて、それらのフィラーを
表4、5の体積比率で混合し、実施例1と同様にして成
形し、脱バインダー処理し焼成した。そして得られた焼
結体に対して実施例1と同様にして、ヤング率、熱膨張
係数を確認した。
Example 3 As shown in Tables 4 and 5, lithium silicate glass (composition: 78
Wt% SiO 2 , 10 wt% Li 2 O, 4 wt% Al 2
O 3 , 4% by weight K 2 O, 2% by weight P 2 O 5 , 2% by weight N
a 2 O, yield point 480 ° C., the thermal expansion coefficient 10.3 ppm / ° C.) at 40 to 400 ° C., forsterite as a filler, using cristobalite, petalite, nepheline, lithium silicate, Tables 4 and 5 and their filler , And molded in the same manner as in Example 1, debinding treatment and firing. The Young's modulus and the coefficient of thermal expansion of the obtained sintered body were confirmed in the same manner as in Example 1.

【0062】また、実施例1と同様にグリーンシートを
作成した後にCuメタライズペーストをスクリーン印刷
法により配線パターンに塗布し、シートの所定箇所に基
板の下面まで通過するスルーホールを形成しその中にも
Cuメタライズペーストを充填した。そして、実施例1
と同様に、このグリーンシートを積層圧着、焼成し、パ
ッケージ用の配線基板を作成し、このパッケージ用配線
基板をプリント基板表面に実装し、実施例1と同様な方
法で熱サイクル試験を行い、最高1000サイクルまで
行った。
After a green sheet is formed in the same manner as in Example 1, a Cu metallizing paste is applied to the wiring pattern by a screen printing method, and a through hole is formed at a predetermined portion of the sheet to pass through to the lower surface of the substrate. Was also filled with Cu metallized paste. And Example 1
In the same manner as described above, this green sheet is laminated and pressed and fired to prepare a wiring board for a package. The wiring board for the package is mounted on the surface of a printed circuit board, and subjected to a thermal cycle test in the same manner as in Example 1. Up to 1000 cycles were performed.

【0063】[0063]

【表4】 [Table 4]

【0064】[0064]

【表5】 [Table 5]

【0065】表4、5より明らかなように、絶縁基板の
最大長さL、外部電気回路基板との熱膨張係数差Δα、
絶縁基板と外部電気回路基板間のロウづけ高さHで関係
づけられたF値が2000以下の試料は、いずれも10
00サイクルまで抵抗変化は全く認められず、極めて安
定で良好な電気的接続状態を維持できた。しかし、F値
が2000よりも小さい試料では1000サイクル未満
で抵抗変化が検出され、実装後の信頼性に欠けることが
わかった。
As is clear from Tables 4 and 5, the maximum length L of the insulating substrate, the difference in thermal expansion coefficient Δα from the external electric circuit board,
Samples having an F value of 2000 or less associated with the brazing height H between the insulating substrate and the external electric circuit board are all 10 samples.
No change in resistance was observed at all until the 00th cycle, and an extremely stable and favorable electrical connection state could be maintained. However, in a sample having an F value smaller than 2,000, a change in resistance was detected in less than 1,000 cycles, and it was found that reliability after mounting was lacking.

【0066】[0066]

【発明の効果】以上詳述したように、本発明の配線基板
の実装構造によれば、大型のセラミック配線基板を熱膨
張係数が大きいプリント基板などの外部電気回路基板に
実装した場合に、両者の熱膨張係数の差に起因する応力
発生が小さく、配線基板と外部電気回路とを長期間にわ
たり正確、かつ強固に電気的接続させることが可能とな
り、配線基板の半導体回路素子の大型化による多端子化
に十分対応できる信頼性の高い配線基板の実装構造を実
現できる。
As described in detail above, according to the mounting structure of the wiring board of the present invention, when a large ceramic wiring board is mounted on an external electric circuit board such as a printed board having a large thermal expansion coefficient, both of them can be used. Stress due to the difference in thermal expansion coefficient between the wiring board and the external electric circuit can be accurately and firmly electrically connected for a long period of time. It is possible to realize a highly reliable wiring board mounting structure capable of sufficiently supporting terminals.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明におけるボールグリッドアレイ型の半導
体素子収納用パッケージの実装構造を説明するための断
面図である。
FIG. 1 is a cross-sectional view for explaining a mounting structure of a ball grid array type semiconductor element storage package according to the present invention.

【図2】本発明における接続端子間の最大離間距離Lを
説明するための図である。
FIG. 2 is a diagram for explaining a maximum separation distance L between connection terminals according to the present invention.

【図3】本発明における実装部の拡大図であり、(a)
は図1のパッケージの実装部、(b)は他の接続端子構
造における実装部である。
FIG. 3 is an enlarged view of a mounting unit according to the present invention, and FIG.
Is a mounting part of the package of FIG. 1, and (b) is a mounting part in another connection terminal structure.

【符号の説明】[Explanation of symbols]

1 セラミック絶縁基板 2 蓋体 3 メタライズ配線層 4 接続端子 5 半導体素子 6 キャビティ 7 電極パッド 8 ボール状端子 9 低融点半田 10 絶縁体 11 配線導体 12 ロウ材 13 凹部 A 配線基板 B 外部電気回路基板 DESCRIPTION OF SYMBOLS 1 Ceramic insulating substrate 2 Lid 3 Metallized wiring layer 4 Connection terminal 5 Semiconductor element 6 Cavity 7 Electrode pad 8 Ball-shaped terminal 9 Low melting point solder 10 Insulator 11 Wiring conductor 12 Brazing material 13 Depression A Wiring board B External electric circuit board

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H05K 3/36 (72)発明者 隈田原 均 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 永江 謙一 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. 6 Identification code FI H05K 3/36 (72) Inventor Hitoshi Kumadahara 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute (72) Inventor Kenichi Nagae 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】セラミックス絶縁基板と、該絶縁基板に配
設されたメタライズ配線層と、前記絶縁基板に取着され
前記メタライズ配線層と電気的に接続された複数の接続
端子とを具備する配線基板を、少なくとも有機樹脂を含
む絶縁体の表面に配線導体が被着形成された外部電気回
路基板上に載置し、前記配線基板の接続端子と前記外部
電気回路基板の配線導体とをロウ付けして実装してなる
配線基板の実装構造において、下記数1 【数1】 で表されるF値が2000以下であることを特徴とする
配線基板の実装構造。
1. A wiring comprising a ceramic insulating substrate, a metallized wiring layer disposed on the insulating substrate, and a plurality of connection terminals attached to the insulating substrate and electrically connected to the metallized wiring layer. The substrate is placed on an external electric circuit board on which a wiring conductor is attached and formed on the surface of an insulator containing at least an organic resin, and the connection terminals of the wiring board and the wiring conductor of the external electric circuit board are brazed. In the mounting structure of the wiring board which is mounted by mounting, A mounting structure of a wiring board, wherein the F value represented by is 2000 or less.
【請求項2】前記配線基板における前記接続端子の最大
離間距離が6mm以上であることを特徴とする請求項1
記載の配線基板の実装構造。
2. The wiring board according to claim 1, wherein the maximum separation distance of the connection terminals is 6 mm or more.
The mounting structure of the wiring board described.
【請求項3】前記絶縁基板の40〜400℃における熱
膨張係数が8〜25ppm/℃であることを特徴とする
請求項1記載の配線基板の実装構造。
3. The mounting structure according to claim 1, wherein the thermal expansion coefficient of the insulating substrate at 40 to 400 ° C. is 8 to 25 ppm / ° C.
【請求項4】前記絶縁基板が、ガラスセラミック焼結体
からなることを特徴とする請求項3記載の配線基板の実
装構造。
4. The mounting structure according to claim 3, wherein said insulating substrate is made of a sintered glass ceramic.
【請求項5】前記外部電気回路基板の40〜400℃に
おける熱膨張係数が8〜28ppm/℃であることを特
徴とする請求項1記載の配線基板の実装構造。
5. The mounting structure according to claim 1, wherein the external electric circuit board has a coefficient of thermal expansion at 40 to 400 ° C. of 8 to 28 ppm / ° C.
【請求項6】前記絶縁基板が、Li2 Oを5〜30重量
%含有するリチウム珪酸ガラス20〜80体積%と、フ
ォルステライト、クリストバライトおよびクォーツの少
なくとも1種を含むフィラー80〜20体積%とからな
る混合物を成形し、焼成したものであることを特徴とす
る請求項4記載の配線基板の実装構造。
6. The insulating substrate according to claim 1, wherein said insulating substrate comprises 20 to 80% by volume of lithium silicate glass containing 5 to 30% by weight of Li 2 O, and 80 to 20% by volume of a filler containing at least one of forsterite, cristobalite and quartz. 5. The mounting structure for a wiring board according to claim 4, wherein the mixture is formed by molding and firing.
JP25882296A 1996-09-30 1996-09-30 Wiring board mounting structure Expired - Fee Related JP3740225B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP25882296A JP3740225B2 (en) 1996-09-30 1996-09-30 Wiring board mounting structure
US08/939,563 US6027791A (en) 1996-09-30 1997-09-29 Structure for mounting a wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25882296A JP3740225B2 (en) 1996-09-30 1996-09-30 Wiring board mounting structure

Publications (2)

Publication Number Publication Date
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930395B2 (en) * 2000-12-05 2005-08-16 Matsushita Electric Industrial Co., Ltd. Circuit substrate having improved connection reliability and a method for manufacturing the same
US7748110B2 (en) 2004-02-20 2010-07-06 Panasonic Corporation Method for producing connection member

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930395B2 (en) * 2000-12-05 2005-08-16 Matsushita Electric Industrial Co., Ltd. Circuit substrate having improved connection reliability and a method for manufacturing the same
US7748110B2 (en) 2004-02-20 2010-07-06 Panasonic Corporation Method for producing connection member

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