JPH10107171A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH10107171A JPH10107171A JP25443296A JP25443296A JPH10107171A JP H10107171 A JPH10107171 A JP H10107171A JP 25443296 A JP25443296 A JP 25443296A JP 25443296 A JP25443296 A JP 25443296A JP H10107171 A JPH10107171 A JP H10107171A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- masking tape
- input
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に係わり、特にメッキによる半導体装置の入出力端子
（メッキバンプ）の形成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to the formation of input / output terminals (plated bumps) of a semiconductor device by plating.
【０００２】[0002]
【従来の技術】図２に示す従来技術において、パッケー
ジ基板１の表面側に半導体素子７を搭載し、ボンディン
グワイヤ６の接続を行い、封止樹脂８で封止しており、
パッケージ基板１の裏面側には入出力端子としての半田
ボール１２が形成されている。この図２の従来技術で
は、パッケージ基板側の入出力端子の形成は、予め基板
とは別に形成された半田ボール１２を所望の間隔、数で
配置された基板側の入出力パット上に、所定の治具等を
用いて配置していた。しかしながらこのような方法では
治具の寸法精度、パッケージ反り等の影響でボールを位
置精度良く接着することができなっかった。2. Description of the Related Art In the prior art shown in FIG. 2, a semiconductor element 7 is mounted on the surface side of a package substrate 1, connected to bonding wires 6, and sealed with a sealing resin 8.
On the back side of the package substrate 1, solder balls 12 are formed as input / output terminals. In the prior art shown in FIG. 2, the input / output terminals on the package substrate side are formed by placing solder balls 12 formed in advance separately from the substrate on the input / output pads on the substrate side arranged at a desired interval and number. It was arranged using a jig or the like. However, in such a method, the ball cannot be bonded with high positional accuracy due to the influence of the dimensional accuracy of the jig, the warpage of the package, and the like.
【０００３】位置精度良く入出力端子を形成する技術と
しては、メッキ技術によりバンプを形成する例が特開昭
６２−２７７７５３号公報に開示されている。As a technique for forming an input / output terminal with high positional accuracy, an example of forming a bump by a plating technique is disclosed in Japanese Patent Application Laid-Open No. 62-27753.
【０００４】この技術を図３を参照して説明すると、２
枚のグリーンシート１Ａ、１Ｂから多層配線基板１が構
成されている。基板１の表面側（上面側）は半導体素子
７が搭載され、その電極とボンディングワイヤ接続パッ
ト２がボンディングワイヤ６により接続され、全体がキ
ャップ１３により封止されている。基板１の裏面側（下
面側）にはメッキバンプ１１が形成され、ボンディング
ワイヤ接続パット２とメッキバンプ１１とはスルーホー
ル４Ａ、４Ｂおよび内部配線パターン３を通して導通さ
れている。This technique will be described with reference to FIG.
The multilayer wiring board 1 is composed of the green sheets 1A and 1B. A semiconductor element 7 is mounted on the front side (upper side) of the substrate 1, its electrodes and the bonding wire connection pads 2 are connected by bonding wires 6, and the whole is sealed by a cap 13. A plating bump 11 is formed on the back side (lower side) of the substrate 1, and the bonding wire connection pad 2 and the plating bump 11 are electrically connected through the through holes 4A and 4B and the internal wiring pattern 3.
【０００５】[0005]
【発明が解決しようとする課題】上記従来技術の第１の
問題点は、メッキバンプを位置精度良く、また方向精度
良く形成することができないことである。A first problem of the above prior art is that the plated bump cannot be formed with high positional accuracy and high directional accuracy.
【０００６】その理由は、メッキバンプ形成時の所望の
バンプ形態になるように治具又は構造により、バンプ形
成を制御していないからである。[0006] The reason is that bump formation is not controlled by a jig or a structure so that a desired bump form at the time of plating bump formation is obtained.
【０００７】第２の問題点は、半導体装置の実装時の取
り扱いにより、メッキバンプを欠損、破損させる恐れが
あることである。[0007] The second problem is that the handling of the semiconductor device at the time of mounting may cause the plating bump to be damaged or damaged.
【０００８】その理由は、メッキバンプを保護していな
いためである。The reason is that the plated bumps are not protected.
【０００９】したがって本発明の目的は、メッキバンプ
を所望の形態（寸法精度、方向精度）に形成し、さらに
半導体装置の実装時の取り扱いからメッキバンプを保護
することができる半導体装置の製造方法を提供すること
である。Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of forming plated bumps in a desired form (dimensional accuracy, directional accuracy) and protecting the plated bumps from handling during mounting of the semiconductor device. To provide.
【００１０】[0010]
【課題を解決するための手段】本発明の特徴は、パッケ
ージ基板に端子としてのバンプを形成する半導体装置の
製造方法において、前記パンプの平面形状と一致した多
数の開口部を有するマスキングテープを用い、この開口
部内にメッキにより前記バンプを形成する半導体装置の
製造方法にある。ここで前記マスキングテープはポリイ
ミドテープ等の絶縁膜テープであることができる。A feature of the present invention is that in a method of manufacturing a semiconductor device in which bumps are formed as terminals on a package substrate, a masking tape having a large number of openings conforming to the planar shape of the pump is used. And a method of manufacturing a semiconductor device in which the bump is formed in the opening by plating. Here, the masking tape may be an insulating film tape such as a polyimide tape.
【００１１】このような本発明では、基板に配置された
入出力端子配置パットに、このパットと同一の寸法、ピ
ッチにより開口部が形成されたテープのこの開口部が一
致するようにテープを接着する。According to the present invention, the tape is adhered to the input / output terminal arranging pad arranged on the substrate so that the opening of the tape having the opening formed with the same dimensions and pitch as the pad coincides with the pad. I do.
【００１２】入出力端子配置パットは基板内の内部配
線、スルーホールにより基板側面にあらかじめ用意した
メッキ引き出し線と電気的な導通を得ることができるた
め、電解メッキを行うことにより、入出力端子配置パッ
ト上にマスキングテープ開口部形状と同一のメッキバン
プを形成することができる。また、開口部の形状を制御
することにより、メッキバンプの形態も制御することが
できる。The input / output terminal arrangement pad can obtain electrical continuity with a plating lead wire prepared in advance on the side surface of the substrate by internal wiring and through holes in the substrate. A plated bump having the same shape as the opening of the masking tape can be formed on the pad. Further, by controlling the shape of the opening, the form of the plated bump can also be controlled.
【００１３】[0013]
【発明の実施の形態】以下図面を参照して本発明を説明
する。図１は本発明の実施の形態の半導体装置の製造方
法を工程順に示した断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【００１４】まず図１（Ａ）において、セラミックまた
はプラスチック多層配線基板１は２枚のシート基板１
Ａ、１Ｂから構成され、表面（上面）に複数のボンディ
ングワイヤ接続パット２が形成され、裏面（下面）に複
数の入出力端子配置パット１０が形成され、それぞれの
ボンディングワイヤ接続パット２はそれに対応する入出
力端子配置パット１０にスルーホール４Ａ、４Ｂおよび
内部配線パターン３を通して電気的に導通している。First, in FIG. 1A, a ceramic or plastic multilayer wiring board 1 is composed of two sheet substrates 1.
A, 1B, a plurality of bonding wire connection pads 2 are formed on the front surface (upper surface), and a plurality of input / output terminal arrangement pads 10 are formed on the back surface (lower surface), and each bonding wire connection pad 2 corresponds thereto. The input / output terminal arrangement pad 10 is electrically connected through the through holes 4A and 4B and the internal wiring pattern 3.
【００１５】さらにそれぞれの入出力端子配置パット１
０はメッキ引き出し線５により側面にも電気的に引き出
されている。Further, each input / output terminal arrangement pad 1
Numeral 0 is also electrically drawn to the side surface by the plating lead wire 5.
【００１６】次に図１（Ｂ）において、半導体素子７を
表面に搭載（ダイボンディング）し、その電極とボンデ
ィングワイヤ接続パット２とをボンディングワイヤ６で
接続し、封止樹脂８で封止する。Next, in FIG. 1B, a semiconductor element 7 is mounted on the surface (die bonding), its electrode and the bonding wire connection pad 2 are connected by a bonding wire 6 and sealed by a sealing resin 8. .
【００１７】次に図１（Ｃ）において、多数の開口部１
９を有するマスキングテープ９を裏面に接着する。入出
力端子配置パット１０はそれぞれ開口部１９内に露出し
ている。Next, in FIG. 1C, a large number of openings 1 are formed.
9 is adhered to the back surface. The input / output terminal arrangement pads 10 are respectively exposed in the openings 19.
【００１８】このマスキングテープ９は絶縁テープ、好
ましくはポリイミドドテープであり、その厚さは約０．
５ｍｍである。またメッキバンプの平面形状を決定する
開口部１９の平面形状は１辺が０．９ｍｍの正方形であ
り、入出力端子配置パット１０と同様に開口部１９は
１．２７ｍｍのピッチでマトリックス状に配列されてい
る。The masking tape 9 is an insulating tape, preferably a polyimide tape, and has a thickness of about 0.1 mm.
5 mm. The planar shape of the openings 19 for determining the planar shape of the plated bumps is a square with 0.9 mm on a side, and the apertures 19 are arranged in a matrix at a pitch of 1.27 mm as in the input / output terminal arrangement pad 10. Have been.
【００１９】またこのマスキングテープ９を接着する接
着剤は温度に対して耐性があり、温度をかけて剥離する
ために、温度により密着性が落ちる性質である必要があ
るから、この接着剤はポリイミド系の接着剤であること
が好ましい。The adhesive for adhering the masking tape 9 is resistant to temperature and needs to have a property of deteriorating the adhesion due to temperature in order to be peeled off when heated. The adhesive is preferably a system adhesive.
【００２０】次に図１（Ｄ）において、基板の側面へ引
き出されたメッキ引き出し線５の全てにメッキ用の電圧
を印加することにより基板側面から電気的導通を得て、
メッキを行いテープ開口部分１９の内部に所望の形態の
メッキバンプ１１を形成することができる。Next, in FIG. 1 (D), a voltage for plating is applied to all of the plating lead wires 5 drawn to the side surface of the substrate to obtain electrical continuity from the side surface of the substrate.
By plating, a desired form of the plated bump 11 can be formed inside the tape opening portion 19.
【００２１】次に図１（Ｅ）において、側面に引き出さ
れたメッキ引き出し線５の部分を研磨によりカットし、
マスキングテープ９を基板１から剥がすことにより半導
体装置を形成する。このマスキングテープ９の剥離は、
熱をかけて接着力を弱めておいて、ピンセットのような
治具でマスキングテープ９を持ち上げることにより行う
ことができる。Next, in FIG. 1 (E), a portion of the plating lead wire 5 drawn out to the side is cut by polishing.
The semiconductor device is formed by peeling off the masking tape 9 from the substrate 1. The peeling of the masking tape 9
This can be performed by raising the masking tape 9 with a jig such as tweezers while weakening the adhesive force by applying heat.
【００２２】あるいはマスキングテープを剥離しないで
そのまま外部基板であるプリント基板に実装することも
考えられる。この場合、熱によってバンプが溶けてもマ
スキングテープの存在により流れず耐熱性が向上すると
考えられる。Alternatively, it is conceivable to mount the masking tape on a printed circuit board as an external board without peeling off the masking tape. In this case, even if the bumps are melted by the heat, the presence of the masking tape prevents the bumps from flowing and improves the heat resistance.
【００２３】[0023]
【発明の効果】本発明の第１の効果は、メッキバンプを
位置精度良く、また方向精度良く所望の形態に形成する
ことができることである。A first effect of the present invention is that a plated bump can be formed in a desired form with high positional accuracy and high directional accuracy.
【００２４】その理由は、メッキバンプ形成時にマスキ
ングテープを使うことにより、バンプ形態を制御するこ
とができるためである。The reason for this is that the use of a masking tape at the time of forming the plated bumps makes it possible to control the form of the bumps.
【００２５】第２の効果は、半導体装置の取り扱いから
メッキバンプを保護することができることである。The second effect is that the plating bump can be protected from handling of the semiconductor device.
【００２６】その理由は、マスキングテープによりメッ
キバンプを保護するためである。The reason is to protect the plated bumps with a masking tape.
【図１】本発明の実施の形態の半導体装置の製造方法を
工程順に示す断面図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
【図２】従来技術を示す断面図である。FIG. 2 is a sectional view showing a conventional technique.
【図３】他の従来技術を示す断面図である。FIG. 3 is a sectional view showing another conventional technique.
１ セラミックまたはプラスチック多層配線基板 １Ａ、１Ｂ シート基板 ３ 内部配線パターン ４Ａ、４Ｂ スルーホール ５ メッキ引き出し線 ６ ボンディングワイヤ ７ 半導体素子 ８ 封止樹脂 ９ マスキングテープ １０ 入出力端子配置パット １１ メッキバンプ １２ 半田ボール １３ キャップ １９ 開口部 DESCRIPTION OF SYMBOLS 1 Ceramic or plastic multilayer wiring board 1A, 1B Sheet substrate 3 Internal wiring pattern 4A, 4B Through hole 5 Plating lead 6 Bonding wire 7 Semiconductor element 8 Sealing resin 9 Masking tape 10 I / O terminal arrangement pad 11 Plating bump 12 Solder ball 13 Cap 19 Opening
Claims (2)
形成する半導体装置の製造方法において、前記パンプの
平面形状と一致した多数の開口部を有するマスキングテ
ープを用い、この開口部内にメッキにより前記バンプを
形成することを特徴とする半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a bump as a terminal is formed on a package substrate, a masking tape having a large number of openings conforming to the planar shape of the pump is used, and the bump is formed in the opening by plating. A method for manufacturing a semiconductor device, comprising:
プであることを特徴とする請求項１記載の半導体装置の
製造方法。2. The method according to claim 1, wherein the masking tape is a polyimide tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25443296A JPH10107171A (en) | 1996-09-26 | 1996-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25443296A JPH10107171A (en) | 1996-09-26 | 1996-09-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10107171A true JPH10107171A (en) | 1998-04-24 |
Family
ID=17264915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25443296A Pending JPH10107171A (en) | 1996-09-26 | 1996-09-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10107171A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011111300A1 (en) * | 2010-03-09 | 2011-09-15 | パナソニック株式会社 | Semiconductor package having electrode on side surface, and semiconductor device |
-
1996
- 1996-09-26 JP JP25443296A patent/JPH10107171A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011111300A1 (en) * | 2010-03-09 | 2011-09-15 | パナソニック株式会社 | Semiconductor package having electrode on side surface, and semiconductor device |
| US20120326293A1 (en) * | 2010-03-09 | 2012-12-27 | Panasonic Corporation | Semiconductor package having electrode on side surface, and semiconductor device |
| US8659138B2 (en) | 2010-03-09 | 2014-02-25 | Panasonic Corporation | Semiconductor package having electrode on side surface, and semiconductor device |
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