JPH10107143A - Interconnection structure for semiconductor element and manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to eliminate a stress when a junction is shallow by a method wherein a first interconnection layer is formed from a source/drain region up to an isolation oxide film and a second interconnection layer which is formed on the surface of the oxide film on their upper layer part is connected to the source/drain layer by using the first interconnection layer. SOLUTION: In a DRAM cell, a substrate 40 is provided with an isolation oxide film 41, and a prescribed region on an active region which is isolated by the oxide film 41 is provided with a polygate electrode 43. A lightly doped source/drain region 44 and a heavily doped source/drain region 47 are formed on both sides of the polygate electrode 43, and sidewall oxide films 46 are formed on both side faces of the polygate electrode 43. A silicide layer 50 is formed from one out of the source/drain regions up to the isolation oxide film 41, an oxide film 51 is formed on it, and a contact hole is formed in the oxide film 41 in such a way that the silicide layer 50 on the isolation oxide film 41 is exposed. A second polycrystal silicon layer 52 and a tungsten silicide layer 53 are provided so as to come into contact with the exposed silicide layer 50.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a wiring structure of a semiconductor device having a contact wiring suitable for a highly integrated device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In general, as the degree of integration of semiconductor devices increases, many DRAM cell arrays and their structures advantageous for high integration have been proposed. For example, a CUB (Capacitor Under Bit Line) structure is applied up to a 16M DRAM class, and a COB (Capacito Under Bit Line) structure is applied after a 64M DRAM class.
r Over Bit Line) As the degree of integration of the semiconductor device increases, the size of the chip decreases, and at the same time, the size of the contact hole also decreases, the level difference increases, and the aspect ratio of the contact hole increases. Therefore, there is a demand for a new wiring forming method that can appropriately cope with these.

A conventional DRAM cell array plan view and wiring structure will be described below with reference to the accompanying drawings. FIG. 1 is a plan view of an array and a cross-sectional view of a wiring structure of a cell having a conventional CUB structure. As shown in FIG. 1, a plurality of gate lines 2, which are also word lines, are formed on a substrate 1 at regular intervals. A large number of node electrodes 3 that are in contact with the substrate 1 and that extend between adjacent gate lines 2 are arranged. A plate electrode 4 is formed on the node electrode 3 with a dielectric material interposed therebetween. A bit line 5 is formed at right angles to the word line 2 through a capacitor region. This bit line 2 is partially connected to the substrate 1.

In such a CUB structure, as shown in FIG. 1, a capacitor is formed below a bit line 5. Since the bit line must be in contact with the substrate, the area of the capacitor below the bit line is limited. In highly integrated devices, the area of the capacitor decreases rapidly. Nevertheless, memories require high capacity capacitors. For this purpose, the structure of the capacitor must be made three-dimensional and its height must be increased. But,
When the height of the capacitor is increased, the position of the bit line 5 is also increased, and the aspect ratio of the contact hole is increased. There are many technical difficulties when embedding a conductive layer in a bit line contact hole and when patterning a bit line 5. Therefore, a 64M DR
New cell arrays and layouts have been required for AM class devices.

FIG. 2 is an array plan view and a cross-sectional view of a wiring structure of a conventional cell having a COB structure. As shown in FIG. 2, the gate lines 11 are similarly formed on the substrate 10 in a line. The bit line 12 is arranged at right angles to the gate line 11, but is arranged at a position immediately above the gate line. Of course, the bit line 12 is in contact with the substrate 10. The node electrode 13 of the capacitor of the cell having this structure is formed between adjacent gate lines 11 in a rectangular shape over both regions. A plate electrode 14 is formed on the node electrode 13 with a dielectric interposed therebetween. In such a COB structure, the bit line 12 is formed before the capacitor is formed. Therefore, the COB structure can be used for the capacitor region up to the region where the bit line 12 is formed, thereby increasing the area of the capacitor.

[0006]

However, the conventional CU
The wiring structure and manufacturing method of the DRAM cell having the B and COB structures have the following problems. First, since the wiring is in direct contact with the substrate, in a highly integrated device, there is a problem of stress with the substrate, particularly when a contact hole is formed at a shallow junction. Second, the alignment margin between the contact hole and the source / drain impurities is reduced, and a problem of short circuit between the wiring and the gate electrode or between the wiring and the semiconductor substrate due to misalignment is likely to occur. Also,
The COB structure does not increase the aspect ratio of the contact hole of the bit line 12. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a DRAM cell having a contact wiring suitable for a highly integrated device.

[0007]

A wiring structure of a DRAM cell according to the present invention comprises a substrate having an active region and an isolation oxide film on the surface, a gate electrode formed insulated in one region on the active region, and a gate. First and second impurity regions formed on the substrate on both sides of the electrode, a first wiring layer electrically connected to the second impurity region and formed on the isolation oxide film, and a first wiring An insulating film formed on the entire surface of the substrate so as to have a contact hole in a portion of the layer placed on the isolation oxide film; and an insulating film connected to the first wiring layer through the contact hole and formed on the insulating film. And a second wiring layer. In addition, the method of the present invention includes defining an active region and a field region on a substrate, forming an isolation oxide film on the field region, forming a gate electrode on a portion of the active region, and forming active regions on both sides of the gate electrode on the substrate. A first and a second impurity region are formed in a region portion, and a first wiring layer is formed from the second impurity region on an isolation oxide film adjacent to the second impurity region. . An insulating film is formed on the surface, and the first film on the field oxide film is formed.
A contact hole leading to the wiring layer is formed, and the second wiring layer is connected to the first wiring layer via the contact hole.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The wiring structure and manufacturing method of a DRAM cell according to the present invention as described above will be described in detail with reference to the accompanying drawings. FIG. 3 is a plan view showing an array of DRAM cells according to the present invention. As shown in FIG. 3, the array of DRAM cells of the present invention has a COB structure, and the bit lines 55 and the word lines 56 are orthogonal.
The rectangular active regions 54 are crossed or arranged in parallel with the bit lines 55 and do not overlap. In the figure, they are parallel. The contact wiring of the bit line 55 includes a linear active region 54 and the isolation oxide film 41 in contact with the active region (see FIG. 4).
Is formed in contact with the silicide layer 50 formed in a part of the substrate.

FIG. 4 is a structural sectional view taken along line CC 'of FIG. As shown in FIG. 4, in the cross section of the wiring structure of the DRAM cell of the present invention, an isolation oxide film 41 is provided on a substrate 40, and a poly gate electrode 43 is provided in a predetermined region on an active region isolated by the oxide film. Substrate poly gate electrode 43
A low concentration source / drain region 44 and a high concentration source / drain region 47 are formed on both sides of
There are side wall oxide films 46 on both sides. The silicide layer 5 extends over one of the source / drain regions and the isolation oxide film 41.
0 is formed. On these, there is an oxide film 51 formed by CVD, and the silicide layer 5 on the isolation oxide film 41 is provided.
A contact hole is formed in the oxide film so that 0 is exposed. There is a second polycrystalline silicon 52 and a tungsten silicide layer 53 which are sequentially formed so as to be in contact with the exposed silicide layer 50.

FIGS. 5 and 6 are sectional views taken along the line CC 'of FIG. The method for forming a wiring of a DRAM cell according to the present invention comprises:
First, as shown in FIG. 5A, a linear active region 54 (see FIG. 3) is formed by etching a substrate 40 having a P-type well using a linear mask. In order to electrically disconnect the elements from each other, a photosensitive film is applied to the entire surface of the substrate 40, the photosensitive film on the isolation region is removed by exposure and development processes, and the remaining photosensitive film is used as a mask. A thermal process is performed to form an isolation oxide film 41 for isolating the elements from each other. Next, a gate oxide film 42 is formed on the entire surface of the substrate 40 by a thermal oxidation method, and a polycrystalline silicon layer is deposited by an LPCVD method. Instead of the polycrystalline silicon layer, an amorphous silicon layer may be deposited and then doped for polycrystallization. Further, L is formed on the entire surface to form a gate electrode.
An oxide film is deposited by PCVD, a photosensitive film is applied on the oxide film, and the photosensitive film is removed by an exposure and development process except for a portion where a gate electrode is formed. The oxide film and the polycrystalline silicon layer are patterned by using the removed photosensitive film as a mask to form a gate cap oxide film 45 and a poly gate electrode 43. Then, low concentration source / drain regions 44 are formed on both sides of the poly gate electrode 43 of the substrate 40 by ion implantation.
To form Further, an undoped CVD oxide film is deposited on the entire surface of the substrate 40 and anisotropically etched by RIE to form sidewall oxide films 46 on both side surfaces of the poly gate electrode 43.
To form High concentration source / drain regions 47 are formed on both sides of the sidewall oxide film 46 by ion implantation.

Next, as shown in FIG.
A titanium layer (Ti) 48 for forming a metal silicide is deposited over the entire surface by sputtering, other physical methods, or chemical methods. At this time, Co, W, M
o and Ni can be used. Next, a first polycrystalline silicon layer 49 is deposited on the entire surface by the LPCVD method. An amorphous silicon layer may be deposited instead of the first polycrystalline silicon layer 49. Thereafter, as shown in FIG. 5 (c), a photosensitive film is applied to the entire surface, and has a pattern for local wiring of silicide which is placed substantially perpendicularly to the direction of the active region and the isolation oxide film 41. Anisotropic etching is performed using a mask. The photosensitive film is removed, and then the first polysilicon layer 49 is etched using the removed photosensitive film as a mask.

As shown in FIG. 6D, the substrate 40 is heat-treated to form a titanium layer (Ti) 48 and a first polycrystalline silicon layer 4.
9 to form a silicide (TiSix) layer 50. This heat treatment is performed in an atmosphere of N ₂ or a non-reactive inert gas at a temperature of about 500 to 700 ° C. By this heat treatment, the titanium layer 48 in contact with the first polycrystalline silicon layer 49 reacts to form a silicide layer 50, and the titanium layer 48 not in contact with the first polycrystalline silicon layer 49
Remains unresponsive. Next, the substrate is treated with NH ₄ OH / H
_The titanium layer 48 that has not reacted is completely immersed in a ₂ O ₂ mixture to completely remove it. Here, when cobalt (Co) metal is used instead of the titanium layer 48, it is immersed and removed in a HNO ₃ / H ₂ O ₂ mixed solution. Next, as shown in FIG. 6E, a CVD oxide film 51 is deposited on the entire surface as an insulating film.
At this time, O ₃ TEOS or a BPSG material which is easy to planarize is used as the insulating film. Then, a photosensitive film is coated on the entire surface of the substrate 40, and the photosensitive film is patterned using a mask having a pattern for electrically connecting the bit line and the pass transistor for accessing data of the DRAM cell. The silicide layer 50 formed on a part of the isolation oxide film 41 by etching the CVD oxide film 51 using the plasma of CHF ₃ or CF ₄ gas by the RIE method.
To be exposed. Next, a second polycrystalline silicon layer 52 is formed on the entire surface of the substrate 40 by low-pressure CVD (LPCVD).
Or an amorphous silicon layer, and a tungsten silicide (WSix) layer 53 is deposited thereon by CVD.

Next, as shown in FIG. 6 (f), a photosensitive film is applied on the tungsten silicide layer 53, and the photosensitive film is removed by photo-etching by exposing and developing steps except for a bit line forming portion. Then, the exposed tungsten silicide layer 53 and the second polycrystalline silicon layer 52 are sequentially etched by the RIE method using the remaining photosensitive film as a mask.

[0014]

According to the wiring structure of the DRAM cell of the present invention, the first wiring layer is formed from the source / drain region to the isolation oxide film, and the first wiring layer is formed on the surface of the oxide film formed on the upper layer. Since the connection from the two wiring layers to the source / drain regions is made at the location of the first wiring layer on the isolation oxide film, there is an effect that it is possible to solve a stress problem with the substrate that may occur in the case of a shallow junction. . Further, according to the present invention, since connection wiring is performed via the first wiring layer formed on the source / drain region and the isolation oxide film, short-circuit between the wiring and the substrate or the gate electrode at the time of misalignment is prevented. This has the effect of solving the problem. Further, when silicide is used as the first wiring layer, electric resistance can be reduced. Furthermore, the method of the present invention does not become particularly complicated as compared with the conventional method, so that it can be directly manufactured by the conventional technique.

[Brief description of the drawings]

FIG. 1 is an array plan view and a structural cross-sectional view of a cell having a conventional CUB structure.

FIG. 2 is an array plan view and a structural cross-sectional view of a cell having a conventional COB structure.

FIG. 3 is a plan view showing an array of DRAM cells according to the first embodiment of the present invention.

FIG. 4 is a structural sectional view taken along line CC ′ of FIG. 3;

FIG. 5 is a process sectional view along a line CC 'of FIG. 3;

FIG. 6 is a process sectional view along a line CC ′ in FIG. 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 40 Substrate 41 Isolation oxide film 42 Gate oxide film 43 Poly gate electrode 44 Low concentration source / drain region 45 Gate cap oxide film 46 Side wall oxide film 47 High concentration source / drain region 48 Titanium layer (Ti) 49 First polycrystalline silicon layer 50 Silicide layer 51 Chemical vapor deposition oxide film 52 First polycrystalline silicon layer 53 Tungsten silicide layer 54 Linear active region 55 Bit line 56 Word line

Claims (5)

[Claims] A substrate having an active region and an isolation oxide film on a surface thereof; a gate electrode formed insulated in one region on the active region; and first and second substrates formed on both sides of the gate electrode. A second impurity region, a first wiring layer electrically connected to the second impurity region and formed on the isolation oxide film, and a portion of the first wiring layer on the isolation oxide film. An insulating film formed on the entire surface of the substrate so as to have a contact hole; and a second wiring layer connected to the first wiring layer via the contact hole and formed on the insulating film. A wiring structure of a semiconductor element characterized by the above-mentioned. 2. The wiring structure according to claim 1, wherein the first wiring layer is formed of a silicide layer. 3. The wiring structure of a semiconductor device according to claim 1, wherein the second wiring layer has a double film structure in which polysilicon and tungsten silicide are stacked. 4. A method comprising: defining an active region and a field region on a substrate, forming an isolation oxide film on the field region; forming a gate electrode on a portion of the active region; First on the active area part on both sides,
Forming a second impurity region; forming a first wiring layer from the second impurity region on an isolation oxide film adjacent to the second impurity region; and forming a contact hole on the first wiring layer. Forming an insulating film on the entire surface of the substrate so as to have: and forming a second wiring layer on the insulating film so as to be connected to the first wiring layer through the contact hole. A method for forming a wiring of a semiconductor element. 5. The step of forming the first wiring layer includes: forming an insulating film sidewall on a side surface of the gate electrode; depositing a refractory metal on the entire surface of the substrate; Forming polysilicon from the second impurity region to an isolating oxide film adjacent to the second impurity region such that silicide is formed by reacting; and removing high melting point metal not reacted in the step. The method for forming a wiring of a semiconductor device according to claim 4, comprising: