JPH10106984A - Polishing method and controller in polishing equipment for semiconductor wafer - Google Patents

Polishing method and controller in polishing equipment for semiconductor wafer

Info

Publication number
JPH10106984A
JPH10106984A JP27730196A JP27730196A JPH10106984A JP H10106984 A JPH10106984 A JP H10106984A JP 27730196 A JP27730196 A JP 27730196A JP 27730196 A JP27730196 A JP 27730196A JP H10106984 A JPH10106984 A JP H10106984A
Authority
JP
Japan
Prior art keywords
polishing
film thickness
time
semiconductor wafer
optimum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27730196A
Other languages
Japanese (ja)
Other versions
JP3558794B2 (en
Inventor
Hidetaka Nakao
秀高 中尾
Takashi Sato
隆志 佐藤
Atsushi Shigeta
厚 重田
Shiro Mishima
志朗 三島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Toshiba Corp
Original Assignee
Ebara Corp
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp, Toshiba Corp filed Critical Ebara Corp
Priority to JP27730196A priority Critical patent/JP3558794B2/en
Publication of JPH10106984A publication Critical patent/JPH10106984A/en
Application granted granted Critical
Publication of JP3558794B2 publication Critical patent/JP3558794B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a controller in a polishing equipment for semiconductor wafers in which a highly accurate polishing is made possible, reflecting such polishing conditions as the updated situation of the surface of a polishing nonwoven fabric and the updated components and temperature of a polishing liquid on the polishing. SOLUTION: This equipment has a polishing-time calculating unit 3, a polishing-time distributing unit 4, and a polishing controlling portion 5. When polishing semiconductor wafers initially, inputting a desired value MT of the film thickness of the wafer and an initial polishing time T0 from an inputting device 2, the first semiconductor wafer is polished only during the time T0 in the polishing portion of the polishing equipment. Thereafter, from the time TO, a measurement value M1 of the pre-polishing film thickness and a measurement value MF1 of the post-polishing film thickness, an optimum polishing time T1 which is applied to each of the second wafer to the wafer with a predetermined sheet number is calculated to polish each semiconductor wafer during the foregoing optimum time T1 . Thereafter, whenever the polishing is completed, the optimum polishing time which is applied to each of the wafer with a specific sheet number to the wafer with a new predetermined sheet number is calculated in succession to polish each semiconductor wafer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体ウエハーを研
磨する半導体研磨装置(ポリッシング装置)において、
研磨する膜厚を精度よく所定値で維持するために最適な
研磨時間で半導体を研磨する半導体ウエハー研磨装置に
おける研磨方法及び研磨制御装置に関するものである。
The present invention relates to a semiconductor polishing apparatus (polishing apparatus) for polishing a semiconductor wafer.
The present invention relates to a polishing method and a polishing control device in a semiconductor wafer polishing apparatus for polishing a semiconductor with an optimum polishing time to accurately maintain a film thickness to be polished at a predetermined value.

【0002】[0002]

【従来の技術】半導体ウエハーの表面を鏡面状に研磨
(ポリッシング)する研磨装置(ポリッシング装置)に
おいて、ウエハー膜厚を所定値に研磨するには、研磨時
間を制御することによって行っている。即ち、研磨量は
ポリッシング速度及び面圧等の研磨条件が一定である
と、研磨量はポリッシング時間に比例するから、研磨時
間を制御することにより、膜厚を所定の値に維持でき
る。
2. Description of the Related Art In a polishing apparatus (polishing apparatus) for polishing (polishing) the surface of a semiconductor wafer to a mirror surface, the polishing of the wafer film to a predetermined value is performed by controlling the polishing time. That is, if the polishing amount is constant under polishing conditions such as the polishing speed and the surface pressure, the polishing amount is proportional to the polishing time. Therefore, by controlling the polishing time, the film thickness can be maintained at a predetermined value.

【0003】従来、このポリッシング時間を得るため
に、作業者が先ず研磨前に1枚の半導体ウエハーの膜厚
を測定し(通常のポリッシング装置では装置の外で行
う)、続いて該1枚の半導体ウエハーをポリッシング装
置で所定時間研磨し、研磨後に該半導体ウエハーの膜厚
を測定し(ポリッシング装置内で測定することも装置外
で測定することもある)、研磨前の膜厚と研磨後の膜厚
と、目標膜圧と、ポリッシング時間とから最適なポリッ
シング時間を計算し、この最適なポリッシング時間で、
後の半導体ウエハーの研磨を行っている。
Conventionally, in order to obtain this polishing time, an operator first measures the film thickness of one semiconductor wafer before polishing (in a normal polishing apparatus, the thickness is measured outside the apparatus), and then, the polishing is performed. The semiconductor wafer is polished by a polishing apparatus for a predetermined time, and after polishing, the film thickness of the semiconductor wafer is measured (in some cases, it is measured inside a polishing apparatus or outside the apparatus). The optimum polishing time is calculated from the film thickness, the target film pressure, and the polishing time, and with this optimum polishing time,
The subsequent polishing of the semiconductor wafer is performed.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記のよ
うにしてポリッシング時間を設定する方法は、人手によ
る困難な作業であると同時に、一回の作業でポリッシン
グ時間を設定するので、ポリッシングが継続していく間
に研磨条件が変化し、同じ研磨時間でも研磨量に差異が
生じる等の問題がある。例えば研磨用不織物の表面が長
時間研磨する間に消耗したり、経時変化を起したり、供
給される研磨液の成分や温度変化等によりの、同じ研磨
時間でも研磨量に差異が生じる等の問題がある。
However, the method of setting the polishing time as described above is a difficult operation by hand, and at the same time, the polishing time is set by one operation, so that the polishing is continued. There is a problem that the polishing conditions change over time, and the polishing amount differs even with the same polishing time. For example, the surface of the polishing non-woven fabric is worn out during long polishing, changes over time, and a difference in the polishing amount occurs even with the same polishing time due to a component of the supplied polishing liquid or a change in temperature. There is a problem.

【0005】また、例えば特公平7−100297号公
報に開示するように、既に研磨した半導体ウエハーの研
磨サイクルでの研磨量及び研磨時間を順次累積し、これ
ら累積値に基づいて平均研磨速度を演算し、この平均速
度と次回の研磨サイクルでの半導体ウエハーの研磨しろ
とに基づいて最適研磨時間を演算し、この最適研磨時間
に基づいて次回の研磨サイクルの研磨を行うものもあ
る。しかしながら、このように研磨時間の累積値の平均
研磨速度を基に最適研磨時間を演算する手法も必ずしも
最適な研磨時間を設定できるものではない。
Further, as disclosed in, for example, Japanese Patent Publication No. 7-100297, the polishing amount and the polishing time in a polishing cycle of a polished semiconductor wafer are sequentially accumulated, and an average polishing rate is calculated based on these accumulated values. In some cases, the optimum polishing time is calculated based on the average speed and the polishing margin of the semiconductor wafer in the next polishing cycle, and the polishing in the next polishing cycle is performed based on the optimum polishing time. However, the method of calculating the optimum polishing time based on the average polishing speed of the accumulated value of the polishing time as described above cannot always set the optimum polishing time.

【0006】何故なら、ロット毎に半導体ウエハーを1
枚ずつ連続して研磨するポリッシング装置においては、
前回の半導体ウエハーが終了した時の研磨用不織物表面
の状況や研磨液の成分や温度が今回や次回の半導体ウエ
アー研磨に大きな影響を与えるものであり、必ずしも過
去の研磨時間の累積値の平均研磨速度が今回や次回の研
磨に大きく影響を与えるものではない。従って、高精度
の膜厚研磨ができないという問題がある。
[0006] One semiconductor wafer is required for each lot.
In a polishing machine that continuously grinds each sheet,
The condition of the surface of the nonwoven fabric for polishing at the end of the previous semiconductor wafer, the composition and temperature of the polishing solution have a great effect on the current and next semiconductor wear polishing, and are not necessarily the average of the accumulated values of past polishing times. The polishing rate does not significantly affect the current or next polishing. Therefore, there is a problem that high-precision film thickness polishing cannot be performed.

【0007】本発明は上述の点に鑑みてなされたもの
で、上記問題点を除去し、最新の研磨用不織物表面の状
況や研磨液の成分や温度等の研磨条件を研磨に反映し、
高精度の研磨ができる半導体ウエハー研磨装置における
研磨方法及び研磨制御装置を提供することを目的とす
る。
The present invention has been made in view of the above points, and eliminates the above-mentioned problems, and reflects the latest polishing conditions such as the state of the surface of the nonwoven fabric for polishing and the components and temperature of the polishing solution in polishing.
An object of the present invention is to provide a polishing method and a polishing control device in a semiconductor wafer polishing apparatus capable of performing highly accurate polishing.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
請求項1に記載の発明は、研磨装置に1ロットが多数枚
からなる半導体ウエハーをロット毎装填し、半導体ウエ
ハーを1枚ずつ目標膜厚値に研磨する半導体ウエハー研
磨装置における研磨方法であって、半導体ウエハーの研
磨後に該研磨における研磨時間、目標膜厚値、半導体ウ
エハーの研磨前の測定膜厚値及び研磨後の測定膜厚値か
ら最適研磨時間を半導体ウエハーの研磨毎に算出し、該
研磨毎に算出した最適研磨時間を次回以降の半導体ウエ
ハーの研磨に適用し、前記1ロットの半導体ウエハーの
全枚数が終了するまで継続することを特徴とする。
According to a first aspect of the present invention, there is provided a polishing apparatus in which a plurality of semiconductor wafers each comprising a large number of lots are loaded in a polishing apparatus for each lot, and the semiconductor wafers are loaded one by one into a target film. A polishing method in a semiconductor wafer polishing apparatus for polishing to a thickness value, comprising: a polishing time after polishing the semiconductor wafer, a target film thickness value, a measured film thickness value before polishing the semiconductor wafer, and a measured film thickness value after polishing. From the above, the optimum polishing time is calculated for each polishing of the semiconductor wafer, and the optimum polishing time calculated for each polishing is applied to the polishing of the next and subsequent semiconductor wafers, and is continued until the total number of the semiconductor wafers of one lot is completed. It is characterized by the following.

【0009】また、請求項2に記載の発明は、研磨装置
に1ロットが多数枚からなる半導体ウエハーをロット毎
装填し、該半導体ウエハーを1枚ずつ連続して研磨する
半導体ウエハー研磨装置における研磨制御装置であっ
て、各種データを入力する入力手段と、半導体ウエハー
の研磨前の膜厚と研磨後の膜厚を測定する膜厚測定手段
と、研磨時間演算手段と、研磨部制御手段を具備し、初
期研磨に際して、入力手段から目標膜厚値を入力すると
共に該目標膜厚値に研磨するのに必要な所定の初期研磨
時間を入力し、研磨部制御手段で研磨部を制御して1枚
目の半導体ウエハーを該初期研磨時間で研磨した後、研
磨時間演算手段で該初期研磨時間及び膜厚測定手段で測
定された研磨前の測定膜厚値と研磨後の測定膜厚値から
次回以降所定枚数目までの最適研磨時間を算出し、該次
回以降所定枚数目までの半導体ウエハーの研磨を該最適
研磨時間で行い、その研磨終了毎後に研磨時間演算手段
で該最適研磨時間と膜厚測定手段で測定された研磨前の
測定膜厚値と研磨後の測定膜厚値とからそれ以降の所定
枚数目の半導体ウエハーの最適研磨時間を算出し、該所
定枚数目の半導体ウエハーを該最適研磨時間で研磨し、
以降順次研磨終了毎にそれ以降の所定枚数目の半導体ウ
エハーの最適研磨時間を算出し、該最適研磨時間で該所
定枚数目の半導体ウエハーを研磨することを特徴とす
る。
According to a second aspect of the present invention, there is provided a polishing apparatus in which a plurality of semiconductor wafers of one lot are loaded into a polishing apparatus for each lot, and the semiconductor wafers are continuously polished one by one. A control device, comprising: input means for inputting various data; film thickness measuring means for measuring a film thickness before and after polishing of a semiconductor wafer; a polishing time calculating means; and a polishing section control means. At the time of initial polishing, a target film thickness value is inputted from the input means, a predetermined initial polishing time required for polishing to the target film thickness value is inputted, and the polishing section is controlled by the polishing section control means so that 1 is obtained. After the first semiconductor wafer is polished for the initial polishing time, the polishing time calculating means calculates the initial polishing time and the measured film thickness before polishing and the measured film thickness after polishing measured by the film thickness measuring means. The predetermined number of times thereafter The optimal polishing time is calculated in the following, the next and subsequent predetermined number of semiconductor wafers are polished by the optimal polishing time, and each time the polishing is completed, the optimal polishing time and the film thickness measuring means are measured by the polishing time calculating means. From the measured film thickness value before polishing and the measured film thickness value after polishing, an optimum polishing time for a predetermined number of semiconductor wafers thereafter is calculated, and the predetermined number of semiconductor wafers are polished with the optimum polishing time. And
Thereafter, each time polishing is sequentially completed, the optimum polishing time for the subsequent predetermined number of semiconductor wafers is calculated, and the predetermined number of semiconductor wafers are polished with the optimum polishing time.

【0010】請求項1及び請求項2に記載の発明によれ
ば、上記のように研磨後にその都度最適研磨時間を算出
し、次回以降の半導体ウエハーの研磨を該算出した最適
研磨時間で行うので、例えば研磨用不織物表面の状況や
研磨液の成分や温度等の研磨条件が変化しても、その変
化した最新の研磨条件がそれ以降の半導体ウエハーの研
磨に反映できるので、半導体ウエハーの膜厚を高精度の
膜厚に研磨することができる。
According to the first and second aspects of the present invention, the optimum polishing time is calculated each time after polishing as described above, and the subsequent polishing of the semiconductor wafer is performed with the calculated optimum polishing time. For example, even if the polishing conditions such as the condition of the surface of the non-woven fabric for polishing and the composition and temperature of the polishing liquid change, the changed latest polishing conditions can be reflected in the subsequent polishing of the semiconductor wafer. The thickness can be polished to a highly accurate thickness.

【0011】また、請求項3に記載の発明は請求項2に
記載の半導体ウエハー研磨装置の研磨制御装置におい
て、前記膜厚測定手段は半導体ウエハーの複数点の膜厚
を測定し、その平均値を測定膜厚とすることを特徴とす
る。
According to a third aspect of the present invention, in the polishing control device of the semiconductor wafer polishing apparatus according to the second aspect, the film thickness measuring means measures the film thickness at a plurality of points on the semiconductor wafer, and averages the measured values. Is the measured film thickness.

【0012】[0012]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。図1は本発明の半導体ウエハー研
磨装置の研磨制御装置の構成を示す図である。図示する
ように、本研磨制御装置は、膜厚測定部1、入力装置
2、ポリッシング時間演算ユニット3、ポリッシング時
間振り分けユニット4、研磨部制御部5を具備する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a polishing control device of a semiconductor wafer polishing apparatus according to the present invention. As shown in the figure, the present polishing control device includes a film thickness measuring unit 1, an input device 2, a polishing time calculation unit 3, a polishing time distribution unit 4, and a polishing unit control unit 5.

【0013】膜厚測定部1は研磨前の半導体ウエハーの
膜厚を測定する研磨前測定機能1aと、研磨後の半導体
ウエハーの膜厚を測定する研磨後測定機能1bを具備
し、研磨前の測定膜厚値MI及び研磨後の測定膜厚値MF
をポリッシング時間演算ユニット3に入力する。ポリッ
シング時間演算ユニット3は後に詳述するように、次回
以降の半導体ウエハーの最適研磨時間T1〜TNを研磨終
了毎に算出し、ポリッシング時間振り分けユニット4に
出力する。なお、膜厚測定部1における膜厚の測定は半
導体ウエハーの面の複数点の膜厚を測定し、その平均値
から測定膜厚値MI及びMFを得る。ことにより精度の良
い測定膜厚値が得られる。
The film thickness measuring section 1 has a pre-polishing measuring function 1a for measuring the film thickness of the semiconductor wafer before polishing and a post-polishing measuring function 1b for measuring the film thickness of the semiconductor wafer after polishing. measuring film thickness value M I and the measured thickness value M F after polishing
Is input to the polishing time calculation unit 3. As will be described in detail later, the polishing time calculation unit 3 calculates the optimum polishing times T 1 to T N for the next and subsequent semiconductor wafers each time polishing is completed, and outputs the calculated polishing times to the polishing time distribution unit 4. The measurement of the film thickness at the film thickness measuring unit 1 measures the thickness of the plurality of points of the surface of the semiconductor wafer, to obtain a measurement thickness value M I and M F from the average value. As a result, a highly accurate measured film thickness value can be obtained.

【0014】研磨部制御部5は研磨する半導体ウエハー
毎に最適研磨時間を格納する研磨時間格納部5aを具備
し、前記ポリッシング時間振り分けユニット4は前記ポ
リッシング時間演算ユニット3で算出された最適研磨時
間T1〜TNをそれぞれ研磨時間格納部5aの2枚目、3
枚目、・・・・、N−1枚目、N枚目の記憶エリアに格
納する。研磨部制御部5は後に詳述するようにポリッシ
ング装置のポリッシング部(研磨部)を研磨時間格納部
5aに格納された最適研磨時間T1〜TNで制御して各半
導体ウエハーを研磨する。
The polishing section control section 5 includes a polishing time storage section 5a for storing an optimum polishing time for each semiconductor wafer to be polished, and the polishing time distribution unit 4 stores the optimum polishing time calculated by the polishing time calculation unit 3. T 1 to T N are respectively set to the second and third polishing time storage units 5a,
..,..., N−1 and N. The polishing section control section 5 controls the polishing section (polishing section) of the polishing apparatus with the optimum polishing times T 1 to T N stored in the polishing time storage section 5a to polish each semiconductor wafer, as will be described in detail later.

【0015】図2は上記研磨制御装置が用いられるポリ
ッシング装置の概略構成を示す図である。ポリッシング
装置は多数枚の半導体ウエハーが収納された収納ケース
25,25’を搬入搬送するロードアンロード部21、
搬送装置22、ポリッシング(研磨)部23、洗浄部2
4及び図1に示す研磨制御装置の膜厚測定部1が所定の
配置で配置されている。
FIG. 2 is a diagram showing a schematic configuration of a polishing apparatus using the above-mentioned polishing control device. The polishing apparatus includes a loading / unloading unit 21 for carrying in and carrying storage cases 25 and 25 'storing a large number of semiconductor wafers;
Transport device 22, polishing (polishing) unit 23, cleaning unit 2
4 and a film thickness measuring unit 1 of the polishing control device shown in FIG. 1 are arranged in a predetermined arrangement.

【0016】搬送装置22はロボット等からなり、ロー
ドアンロード部21に搬入された収納ケース25から半
導体ウエハーを1枚ずつ取り出し、膜厚測定部1に送
る。該膜厚測定部1では先ず研磨前の膜厚を測定する。
続いて搬送装置22は該研磨前の膜厚測定が終了した半
導体ウエハーをポリッシング部23に渡す。ポリッシン
グ部33では、例えばトップリングに半導体ウエハーを
ターンテーブル上面に貼付た研磨用不織物面に所定の圧
力で当接させ、トップリングの回転とターンテーブルの
回転による相互運動で半導体ウエハーを所定時間研磨す
る。この研磨時間は前記のように研磨部制御部5のポリ
ッシング時間記憶部5aの各記憶エリアに格納された最
適研磨時間T1〜TNで行う。
The transfer device 22 is composed of a robot or the like, and takes out semiconductor wafers one by one from the storage case 25 carried into the load / unload unit 21 and sends the semiconductor wafers to the film thickness measuring unit 1. The film thickness measuring section 1 first measures the film thickness before polishing.
Subsequently, the transfer device 22 transfers the semiconductor wafer, for which the film thickness measurement before polishing has been completed, to the polishing unit 23. In the polishing section 33, for example, the semiconductor wafer is brought into contact with the top ring at a predetermined pressure against a nonwoven fabric surface for polishing attached to the upper surface of the turntable, and the semiconductor wafer is moved for a predetermined time by the mutual movement due to the rotation of the top ring and the rotation of the turntable. Grind. The polishing time is determined by the optimum polishing times T 1 to T N stored in the respective storage areas of the polishing time storage unit 5a of the polishing unit control unit 5 as described above.

【0017】研磨の終了した半導体ウエハーは搬送装置
22で洗浄部24に送られ、該洗浄部24で洗浄し乾燥
した後、搬送装置22で膜厚測定部1に送られ、該膜厚
測定部1で研磨後の膜厚が測定され、膜厚測定後はロー
ドアンロード部21に移送され、該ロードアンロード部
21に別途配置されている研磨終了後の半導体ウエハー
を収納する収納ケース25’に収納される。上記のよう
に収納ケース25に収納された1ロットの半導体ウエハ
ーは搬送装置22により1枚ずつ取り出され、研磨、洗
浄・乾燥、研磨後の膜厚測定の作業が繰り返される。こ
の収納ケースの全部の半導体ウエハーの上記作業が研磨
が終了した時点、即ち1ロットの半導体ウエハーの研磨
が終了した時点で次のロットの研磨作業に移る。
The polished semiconductor wafer is sent to the cleaning unit 24 by the transfer unit 22, washed and dried by the cleaning unit 24, and then sent to the film thickness measurement unit 1 by the transfer unit 22. In step 1, the thickness of the polished film is measured. After the film thickness is measured, the polished semiconductor wafer is transferred to the load / unload unit 21 and is separately disposed in the load / unload unit 21 for storing the polished semiconductor wafer. Is stored in. The semiconductor wafers of one lot stored in the storage case 25 as described above are taken out one by one by the transfer device 22, and the operations of polishing, washing / drying, and measuring the film thickness after polishing are repeated. When the above-mentioned operation for all the semiconductor wafers in the storage case has been finished, ie, when the polishing of one lot of semiconductor wafers has been finished, the polishing operation for the next lot is started.

【0018】図3及び図4は上記研磨制御装置の研磨処
理作業の流れを示す図であり、同図に基づいて研磨処理
作業を説明する。先ず図3において研磨装置のロードア
ンロード部21に研磨を必要とする1ロット(例えば2
5枚)半導体ウエハーを収納した収納ケース25をセッ
トする。次に、入力装置2から目標膜厚値MTと初期ポ
リッシング(研磨)時間T0を入力する。該目標膜厚値
Tはポリッシング時間演算ユニット3に転送され、初
期ポリッシング時間T0はポリッシング時間演算ユニッ
ト3と研磨部制御部5に転送され、研磨部制御部5では
ポリッシング時間記憶部5aの1枚目の記憶エリアに格
納される。
FIG. 3 and FIG. 4 are diagrams showing the flow of the polishing processing operation of the above-mentioned polishing control device. The polishing processing operation will be described with reference to FIG. First, in FIG. 3, one lot (for example, 2 lots) requiring polishing in the load / unload unit 21 of the polishing apparatus is used.
(5 sheets) A storage case 25 storing semiconductor wafers is set. Then, enter the target thickness value M T and the initial polishing from the input device 2 (polishing) time T 0. Is the target thickness value M T is transferred to the polishing time calculation unit 3, an initial polishing time T 0 is transferred to the polishing unit control unit 5 and the polishing time calculation unit 3, the polishing unit control unit 5 in the polishing time storage unit 5a It is stored in the first storage area.

【0019】初期ポリッシング時間T0は膜厚が前記目
標膜厚値MTになるまで研磨するのに必要な時間で研磨
前の膜厚と目標膜厚値より経験的に算出される。上記の
ように搬送装置22は収納ケース25から1枚目の半導
体ウエハーW1を取り出し、膜厚測定部1に移送する。
この時2枚目の半導体ウエハーW2は収納ケース25内
で待機状態になる。膜厚測定部1は該半導体ウエハーW
1の研磨前の膜厚を測定し、その膜厚測定値MIをポリッ
シング時間演算ユニット3に転送する。
The initial polishing time T 0 is the thickness is calculated the target thickness value empirically from the pre-polishing film thickness and the target film thickness value at the time required to polish to a M T. As described above, the transfer device 22 takes out the first semiconductor wafer W 1 from the storage case 25 and transfers it to the film thickness measuring unit 1.
At this time, the second semiconductor wafer W 2 enters a standby state in the storage case 25. The film thickness measuring unit 1 is provided with the semiconductor wafer W
The film thickness before polishing of 1 was measured, and transfers the measured film thickness M I in the polishing time calculating unit 3.

【0020】続いて搬送装置は22は半導体ウエハーW
1をポリッシング部23に移送する。該ポリッシング部
23では半導体ウエハーW1を研磨部制御部5の制御に
より初期ポリッシング時間T0だけ研磨する。該研磨が
終了すると搬送装置22は半導体ウエハーW1を洗浄部
24に移送し、該洗浄部24で洗浄・乾燥された半導体
ウエハーW1は再び搬送装置は22により、膜厚測定部
1に移送され、ここで半導体ウエハーW1の研磨後の膜
厚が測定され、その測定膜厚値MF1はポリッシング時間
演算ユニット3に転送される。膜厚測定終了後、半導体
ウエハーW1は搬送装置22でロードアンロード部21
に移送され、研磨終了後の半導体ウエハーを収容する収
納ケース25’に収納される。
Subsequently, the transfer device 22 is a semiconductor wafer W
1 is transferred to the polishing section 23. The polishing section 23 polishes the semiconductor wafer W 1 for an initial polishing time T 0 under the control of the polishing section control section 5. When the polishing is completed, the transfer device 22 transfers the semiconductor wafer W 1 to the cleaning unit 24, and the semiconductor wafer W 1 cleaned and dried in the cleaning unit 24 is transferred again to the film thickness measuring unit 1 by the transfer device 22. It is, where the measured thickness after the polishing of the semiconductor wafer W 1 is the measured thickness value M F1 is transferred to the polishing time calculating unit 3. After the completion of the film thickness measurement, the semiconductor wafer W 1 is transferred to the load / unload unit 21 by the transfer device 22.
And is stored in a storage case 25 'for storing the semiconductor wafer after polishing.

【0021】続いてポリッシング時間演算ユニット3で
は、前記初期ポリッシング時間T0、半導体ウエハーW1
の研磨前の測定膜厚値MI、研磨後の測定膜厚値MF1
び目標膜厚値MTから最適ポリッシング時間(目標膜厚
値MTにするための最適なポリッシング時間)T1{T1
=f(MT,MI,MF1,T0)}を演算して求める。該
最適ポリッシング時間T1はポリッシング時間振り分け
ユニット4に転送され、研磨部制御部5のポリッシング
時間記憶部5aの2枚目及び3枚目の記憶エリアに格納
する。
Subsequently, in the polishing time calculation unit 3, the initial polishing time T 0 , the semiconductor wafer W 1
Measurements thickness value before polishing of M I, measured thickness value M F1 and the target thickness value M T (optimal polishing time to the target thickness value M T) optimum polishing time from the polished T 1 { T 1
= F (M T , M I , M F1 , T 0 )}. The optimum polishing time T 1 is transferred to the polishing time distribution unit 4 and stored in the second and third storage areas of the polishing time storage unit 5 a of the polishing unit control unit 5.

【0022】この最適ポリッシング時間T1が演算され
たことを確認したら、作業者は前記待機を解除して図4
に示すように、2枚目以降の半導体ウエハーの研磨作業
を開始する。搬送装置22は2枚目の半導体ウエハーW
2を収納ケース25から取り出しポリッシング部23に
移送する。ポリッシング部23では研磨部制御部5の制
御により、ポリッシング時間記憶部5aの2枚目の記憶
エリアに格納され最適ポリッシング時間T1だけ2枚目
の半導体ウエハーW2を研磨する。
After confirming that the optimum polishing time T 1 has been calculated, the operator cancels the waiting and releases the waiting time as shown in FIG.
As shown in (2), the polishing operation for the second and subsequent semiconductor wafers is started. The transfer device 22 is a second semiconductor wafer W
2 is taken out of the storage case 25 and transferred to the polishing section 23. The control of the polishing unit 23 in the polishing unit control unit 5 is stored in the second sheet storage area of the polishing time storing unit 5a polishing the optimum polishing time T 1 by the second sheet of the semiconductor wafer W 2.

【0023】搬送装置22は研磨の終了した半導体ウエ
ハーW2を洗浄部24に移送し、ここで洗浄され乾燥さ
れた半導体ウエハーW2は再び搬送装置22で膜厚測定
部1に移送される。膜厚測定部1は半導体ウエハーW2
の研磨後の膜厚を測定し、その膜厚測定値MF2をポリッ
シング時間演算ユニット3に転送する。研磨後の膜厚が
測定された半導体ウエハーW2は搬送装置22でロード
アンロード部21に移送され、研磨終了後の半導体ウエ
ハーを収容する収納ケースに25’収納される。
The transfer device 22 transfers the polished semiconductor wafer W 2 to the cleaning unit 24, and the washed and dried semiconductor wafer W 2 is transferred to the film thickness measuring unit 1 again by the transfer device 22. The film thickness measuring unit 1 is a semiconductor wafer W 2
The film thickness after the polishing were measured, and transfers the measured film thickness M F2 in polishing time calculating unit 3. The semiconductor wafer W 2 that the film thickness after polishing is measured is transferred to the loading and unloading unit 21 by the transfer device 22, it is 25 'housed in the housing case for housing the semiconductor wafer after polishing.

【0024】ポリッシング時間演算ユニット3は、前記
目標膜厚値MT、2枚目の半導体ウエハーW2の研磨前の
測定膜厚値MI、研磨後の膜厚測定値MF2、最適ポリッ
シング時間T1から4枚目の半導体ウエハーW4を研磨す
る最適研磨時間T4{T4=f(MT,MI,MF2
1)}を演算して求め、この最適研磨時間T4をポリッ
シング時間振り分けユニット4に転送し、研磨部制御部
5のポリッシング時間記憶部5aの4枚目の記憶エリア
に格納する。
The polishing time calculation unit 3 calculates the target film thickness M T , the measured film thickness M I before polishing of the second semiconductor wafer W 2 , the measured film thickness M F2 after polishing, the optimum polishing time. Optimal polishing time T 4 {T 4 = f for polishing the fourth semiconductor wafer W 4 from T 1 (M T , M I , M F2 ,
T 1 )} is calculated, and this optimum polishing time T 4 is transferred to the polishing time distribution unit 4 and stored in the fourth storage area of the polishing time storage unit 5 a of the polishing unit control unit 5.

【0025】前記2枚目の半導体ウエハーW2の研磨作
業に並行して3枚目の半導体ウエハーW3の研磨作業も
スタートする。搬送装置22は3枚目の半導体ウエハー
3を収納ケース25から取り出しポリッシング部23
に移送し、該ポリッシング部23では研磨部制御部5の
制御により、ポリッシング時間記憶部5aの3枚目の記
憶エリアに格納され最適ポリッシング時間T1で3枚目
の半導体ウエハーW3を研磨する。
A polishing operation for the third semiconductor wafer W 3 is started in parallel with the polishing operation for the second semiconductor wafer W 2 . The transfer device 22 takes out the third semiconductor wafer W 3 from the storage case 25 and performs the polishing section 23.
Transferred to the control of the polishing section 23 in the polishing unit control unit 5, to polish the 3rd stored in the storage area optimal polishing time T 1 in 3rd semiconductor wafer W 3 of the polishing time storage unit 5a .

【0026】研磨の終了した半導体ウエハーW3は搬送
装置22により洗浄部24に移送され、洗浄・乾燥され
た半導体ウエハーW3は膜厚測定部1に移送され、膜厚
測定部1で研磨後の膜厚が測定され、その膜厚測定値M
F3はポリッシング時間演算ユニット3に転送される。研
磨後の膜厚が測定された半導体ウエハーW3は搬送装置
22でロードアンロード部21に移送され、研磨終了後
の半導体ウエハーを収容する収納ケース25’に収納さ
れる。
The polished semiconductor wafer W 3 is transferred to the cleaning unit 24 by the transfer unit 22, and the washed and dried semiconductor wafer W 3 is transferred to the film thickness measuring unit 1, and polished by the film thickness measuring unit 1. Is measured, and the measured film thickness M
F3 is transferred to the polishing time calculation unit 3. Semiconductor wafer W 3 that the film thickness after polishing is measured is transferred to the loading and unloading unit 21 by the transfer device 22, it is housed in the housing case 25 'which houses the semiconductor wafer after polishing.

【0027】ポリッシング時間演算ユニット3は、前記
目標膜厚値MT、3枚目の半導体ウエハーW3の研磨前の
測定膜厚値MI、研磨後の膜厚測定値MF3、最適ポリッ
シング時間T1から5枚目の半導体ウエハーW5を研磨す
る最適研磨時間T5(T5=f(MT,MI,MF3
3))を演算して求め、この最適研磨時間T5をポリッ
シング時間振り分けユニット4に転送し、研磨部制御部
5のポリッシング時間記憶部5aの5枚目の記憶エリア
に格納する。
The polishing time calculation unit 3 calculates the target film thickness M T , the measured film thickness M I before polishing of the third semiconductor wafer W 3 , the measured film thickness M F3 after polishing, the optimum polishing time. optimum polishing time T 5 (T 5 = f ( M T, M I, M F3 from T 1 to polish the semiconductor wafer W 5 of 5 th,
T 3 )) is calculated, and this optimum polishing time T 5 is transferred to the polishing time distribution unit 4 and stored in the fifth storage area of the polishing time storage unit 5 a of the polishing unit control unit 5.

【0028】4枚目の半導体ウエハーW4の研磨作業
は、搬送装置22により4枚目の半導体ウエハーW4
取り出しポリッシング部23に移送され、該ポリッシン
グ部23で研磨部制御部5の制御により、ポリッシング
時間記憶部5aの4枚目の記憶エリアに格納され最適ポ
リッシング時間T4で4枚目の半導体ウエハーW4を研磨
する。
The polishing operation of the semiconductor wafer W 4 of the fourth sheet is transferred to the polishing section 23 takes out the semiconductor wafer W 4 of the fourth sheet by the transfer device 22, the control of the polishing unit control unit 5 in the polishing section 23 to polish the 4 th semiconductor wafer W 4 at 4th stored in the storage area optimal polishing time T 4 of the polishing time storage unit 5a.

【0029】研磨の終了した半導体ウエハーW4は洗浄
部24で洗浄・乾燥され、更に膜厚測定部1に移送さ
れ、膜厚測定部1で研磨後の膜厚が測定され、その測定
膜厚値MF4はポリッシング時間演算ユニット3に転送さ
れ、半導体ウエハーW4はロードアンロード21で研磨
終了後の半導体ウエハーを収容する収納ケース25’に
収納される。
The polished semiconductor wafer W 4 is cleaned and dried in the cleaning unit 24, further transferred to the film thickness measuring unit 1, where the polished film thickness is measured by the film thickness measuring unit 1. the value M F4 is transferred to the polishing time calculation unit 3, the semiconductor wafer W 4 is accommodated in the storage case 25 'which houses the semiconductor wafer after polishing at the load-unload 21.

【0030】ポリッシング時間演算ユニット3は、前記
目標膜厚値MT、前記研磨前の測定膜厚値MI、研磨後の
測定膜厚値MF4、最適ポリッシング時間T4から6枚目
の半導体ウエハーW6を研磨する最適研磨時間T6{T6
=f(MT,MI,MF4,T4)}を演算して求め、この
最適研磨時間T6をポリッシング時間振り分けユニット
4に転送し、研磨部制御部5のポリッシング時間記憶部
5aの6枚目の記憶エリアに格納する。
The polishing time calculation unit 3 calculates the sixth semiconductor wafer from the target film thickness M T , the measured film thickness M I before polishing, the measured film thickness M F4 after polishing, and the optimum polishing time T 4. optimum polishing time T 6 to polish the wafer W 6 {T 6
= F (M T , M I , M F4 , T 4 )}, and transfers this optimum polishing time T 6 to the polishing time distribution unit 4 to store the optimum polishing time T 6 in the polishing time storage unit 5 a of the polishing unit control unit 5. The image is stored in the sixth storage area.

【0031】以下同様に5枚目の半導体ウエハーW5
研磨作業は研磨部制御部5のポリッシング時間記憶部5
aの5枚目の記憶エリアに格納された最適研磨時間T5
で研磨してその研磨終了後に7枚目の最適研磨時間T7
を演算し、6枚目の半導体ウエハーW6の研磨作業は研
磨部制御部5のポリッシング時間記憶部5aの6枚目の
記憶エリアに格納された最適研磨時間T6で研磨してそ
の研磨終了後に8枚目の最適研磨時間T8を演算する。
Similarly, the polishing operation of the fifth semiconductor wafer W 5 is performed by the polishing time storage unit 5 of the polishing unit control unit 5.
The optimal polishing time T 5 stored in the fifth memory area of a
, And after the polishing is completed, the optimal polishing time T 7 for the seventh sheet
The polishing of the sixth semiconductor wafer W 6 is polished with the optimum polishing time T 6 stored in the sixth storage area of the polishing time storage unit 5 a of the polishing unit control unit 5 and the polishing is completed. Thereafter, the optimum polishing time T8 for the eighth wafer is calculated.

【0032】このようにK枚目の半導体ウエハーWK
研磨終了後、研磨前の測定膜厚値MI、研磨後の膜厚測
定値MFK、最適ポリッシング時間TKからK+2枚目の
半導体ウエハーWK+2を研磨する最適研磨時間TK+2(T
K+2=f(MT,MI,MFK,TK))を演算して求め、研
磨部制御部5のポリッシング時間記憶部5aのK+2枚
目の記憶エリアに格納する。
After the polishing of the K-th semiconductor wafer W K is completed, the measured film thickness M I before polishing, the measured film thickness M FK after polishing, and the K + 2 semiconductor wafer from the optimum polishing time T K. Optimal polishing time T K + 2 for polishing wafer W K + 2 (T
K + 2 = f (M T , M I , M FK , T K )) is calculated and stored in the (K + 2) th storage area of the polishing time storage unit 5 a of the polishing unit control unit 5.

【0033】なお、上記実施の形態では、研磨前の膜厚
測定は1枚目の半導体ウエハーW1のみで行い、その測
定膜厚値を用いているが、1枚毎に研磨前の膜厚を測定
し、その都度、測定膜厚値MI1、MI2〜MINを得るよう
にしても良い。
In the above embodiment, the film thickness before polishing is measured only on the first semiconductor wafer W1, and the measured film thickness value is used. May be measured, and the measured film thickness values M I1 , M I2 to M IN may be obtained each time.

【0034】また、上記実施の形態では、初期ポリッシ
ング時間T0、研磨前の測定膜厚値MI、研磨後の測定膜
厚値MF1及び目標膜厚値MTから演算して得た最適ポリ
ッシング時間T1{T1=f(MT,MI,MF1,T0)}
を2枚目及び3枚目の半導体ウエハーの研磨に使用し、
以下研磨終了毎にそれから2枚目に当る半導体ウエハー
の最適ポリッシング時間を演算して求めているが、これ
に限定されるものではなく、例えば、最適ポリッシング
時間T1を2枚目、3枚目、4枚目の半導体ウエハーの
研磨に使用し、以下研磨終了毎にそれから3枚目に当る
半導体ウエハーの最適ポリッシング時間を演算して求め
ても良く、また最適ポリッシング時間T1を2枚目の半
導体ウエハーの研磨に使用し、以下研磨終了毎にその次
の半導体ウエハーの最適ポリッシング時間を演算して求
めてもよく良い。
In the above embodiment, the optimum polishing time T 0 , the measured film thickness M I before polishing, the measured film thickness M F1 after polishing, and the optimum film thickness M T obtained from the target film thickness MT are calculated. Polishing time T 1 {T 1 = f (M T , M I , M F1 , T 0 )}
Is used for polishing the second and third semiconductor wafers,
While seeking by calculating it from the optimum polishing time of the semiconductor wafer to hit the second sheet to the polishing each termination below, but the invention is not limited thereto, for example, the second sheet the optimum polishing time T 1, 3 sheet , used to polish 4 th semiconductor wafer, then the semiconductor wafer to hit the third sheet may be determined by calculating the optimal polishing time and the optimum polishing time T 1 to the second sheet to the polishing each ends below It may be used for polishing a semiconductor wafer, and the optimum polishing time of the next semiconductor wafer may be calculated and obtained every time the polishing is completed.

【0035】要は、1枚目の半導体ウエハーを初期研磨
時間T0で研磨した後、該初期研磨時間T0及び研磨前の
測定膜厚値MIと研磨後の測定膜厚値MF1から次回以降
所定枚数目までの最適研磨時間を算出し、該所定枚数目
までの半導体ウエハーを該最適研磨時間で研磨し、以降
順次研磨終了毎にそれ以降の所定枚数目の半導体ウエハ
ーの最適研磨時間を算出し、該最適研磨時間で該所定枚
数目の半導体ウエハーを研磨するようにすれば良い。
[0035] In short, the first sheet of the semiconductor wafer after polishing in the initial polishing time T 0, from the measured thickness value M F1 after polishing and measurement thickness value M I before initial polishing time T 0 and polishing Calculate the optimal polishing time from the next time to the predetermined number of wafers, polish the semiconductor wafers up to the predetermined number of wafers with the optimal polishing time, and thereafter, each time polishing is completed, the optimal polishing time of the subsequent predetermined number of semiconductor wafers May be calculated and the predetermined number of semiconductor wafers may be polished at the optimum polishing time.

【0036】[0036]

【発明の効果】以上説明したように請求項1及び請求項
2に記載の発明によれば、半導体ウエハーの研磨後に該
研磨における研磨時間、目標膜厚値、半導体ウエハーの
研磨前の測定膜厚値及び研磨後の測定膜厚値から最適研
磨時間を半導体ウエハーの研磨毎に算出し、該研磨毎に
算出した最適研磨時間を次回以降の半導体ウエハーの研
磨に適用するので、最新の研磨条件を研磨に反映し、半
導体ウエハーの膜厚を高精度に研磨できるという優れた
効果が得られる。
As described above, according to the first and second aspects of the present invention, the polishing time after polishing the semiconductor wafer, the target film thickness value, the measured film thickness before polishing the semiconductor wafer. The optimum polishing time is calculated for each polishing of the semiconductor wafer from the values and the measured film thickness values after polishing, and the optimum polishing time calculated for each polishing is applied to the subsequent polishing of the semiconductor wafer. An excellent effect is obtained in that the thickness of the semiconductor wafer can be polished with high precision, which is reflected in polishing.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体ウエハー研磨装置の研磨制御装
置の構成を示す図である。
FIG. 1 is a diagram showing a configuration of a polishing control device of a semiconductor wafer polishing apparatus according to the present invention.

【図2】本発明の研磨制御装置が用いられるポリッシン
グ装置の概略構成を示す図である。
FIG. 2 is a diagram showing a schematic configuration of a polishing apparatus using the polishing control device of the present invention.

【図3】本発明の研磨制御装置の研磨処理作業の流れを
示す図である。
FIG. 3 is a diagram showing a flow of a polishing processing operation of the polishing control device of the present invention.

【図4】本発明の研磨制御装置の研磨処理作業の流れを
示す図である。
FIG. 4 is a diagram showing a flow of a polishing processing operation of the polishing control device of the present invention.

【符号の説明】[Explanation of symbols]

1 膜厚測定部 2 入力装置 3 ポリッシング時間演算ユニット 4 ポリッシング時間振り分けユニット 5 研磨部制御部 21 ロードアンロード部 22 搬送装置 23 ポリッシング部 24 洗浄部 25 収納ケース 25’ 収納ケース Reference Signs List 1 film thickness measurement unit 2 input device 3 polishing time calculation unit 4 polishing time distribution unit 5 polishing unit control unit 21 load / unload unit 22 transfer device 23 polishing unit 24 cleaning unit 25 storage case 25 'storage case

───────────────────────────────────────────────────── フロントページの続き (72)発明者 重田 厚 神奈川県川崎市幸区堀川町72番地 株式会 社東芝川崎事業所内 (72)発明者 三島 志朗 三重県四日市市由之一色町字中龍宮800番 地 株式会社東芝四日市工場内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Atsushi Shigeta Inventor 72, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside of Toshiba Kawasaki Works Co., Ltd. Address Toshiba Corporation Yokkaichi Plant

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 研磨装置に1ロットが多数枚からなる半
導体ウエハーをロット毎装填し、該半導体ウエハーを1
枚ずつ目標膜厚値に研磨する半導体ウエハー研磨装置に
おける研磨方法であって、 半導体ウエハーの研磨後に該研磨における研磨時間、目
標膜厚値、半導体ウエハーの研磨前の測定膜厚値及び研
磨後の測定膜厚値から最適研磨時間を半導体ウエハーの
研磨毎に算出し、該研磨毎に算出した最適研磨時間を次
回以降の半導体ウエハーの研磨に適用し、前記1ロット
の半導体ウエハーの全枚数が終了するまで継続すること
を特徴とする半導体ウエハー研磨装置の研磨方法。
1. A polishing apparatus is loaded with a lot of semiconductor wafers, one lot of which is a lot, and the semiconductor wafer is loaded with one lot.
A polishing method in a semiconductor wafer polishing apparatus for polishing a wafer to a target film thickness value one by one, wherein a polishing time in the polishing after polishing the semiconductor wafer, a target film thickness value, a measured film thickness value before polishing the semiconductor wafer, and a post-polishing time. The optimum polishing time is calculated for each polishing of the semiconductor wafer from the measured film thickness value, and the optimum polishing time calculated for each polishing is applied to the polishing of the next and subsequent semiconductor wafers. A polishing method for a semiconductor wafer polishing apparatus, wherein the polishing is continued until the polishing is completed.
【請求項2】 研磨装置に1ロットが多数枚からなる半
導体ウエハーをロット毎装填し、該半導体ウエハーを1
枚ずつ目標膜厚値に研磨する半導体ウエハー研磨装置に
おける研磨制御装置であって、 各種データを入力する入力手段と、前記半導体ウエハー
の研磨前の膜厚と研磨後の膜厚を測定する膜厚測定手段
と、研磨時間演算手段と、研磨部制御手段を具備し、初
期研磨に際して、前記入力手段から目標膜厚値を入力す
ると共に該目標膜厚値に研磨するのに必要な所定の初期
研磨時間を入力し、前記研磨部制御手段で研磨部を制御
して1枚目の半導体ウエハーを該初期研磨時間で研磨し
た後、前記研磨時間演算手段で該初期研磨時間及び前記
膜厚測定手段で測定された研磨前の測定膜厚値と研磨後
の測定膜厚値から次回以降所定枚数目までの最適研磨時
間を算出し、該次回以降所定枚数目までの半導体ウエハ
ーの研磨を該最適研磨時間で行い、その研磨終了毎後に
前記研磨時間演算手段で該最適研磨時間と前記膜厚測定
手段で測定された研磨前の測定膜厚値と研磨後の測定膜
厚値とからそれ以降の所定枚数目の半導体ウエハーの最
適研磨時間を算出し、該所定枚数目の半導体ウエハーを
該最適研磨時間で研磨し、以降順次研磨終了毎にそれ以
降所定枚数目の半導体ウエハーの最適研磨時間を算出
し、該最適研磨時間で該所定枚数目の半導体ウエハーを
研磨することを特徴とする半導体ウエハー研磨装置にお
ける研磨制御装置。
2. A polishing apparatus is loaded with a lot of semiconductor wafers, one lot of which is a lot, and the semiconductor wafers are loaded in one lot.
What is claimed is: 1. A polishing control device for a semiconductor wafer polishing apparatus for polishing a wafer to a target film thickness value, comprising: an input unit for inputting various data; and a film thickness for measuring a film thickness before polishing and a film thickness after polishing of the semiconductor wafer. A measuring unit, a polishing time calculating unit, and a polishing unit control unit, and a predetermined initial polishing required for inputting a target film thickness value from the input unit and polishing to the target film thickness value during initial polishing. After inputting the time, the polishing section is controlled by the polishing section control means and the first semiconductor wafer is polished with the initial polishing time, and then the initial polishing time and the film thickness measuring means are calculated by the polishing time calculation means. From the measured film thickness value before polishing and the measured film thickness value after polishing, the optimal polishing time for the next and subsequent predetermined number of wafers is calculated, and the polishing of the semiconductor wafers for the next and subsequent predetermined number of wafers is performed. In the laboratory After each polishing, a predetermined number of semiconductor wafers from the optimum polishing time, the measured film thickness value before polishing, and the measured film thickness value after polishing measured by the film thickness measuring means by the polishing time calculation means. The optimum polishing time is calculated, and the predetermined number of semiconductor wafers are polished with the optimum polishing time. Thereafter, each time the polishing is sequentially completed, the optimum polishing time of the predetermined number of semiconductor wafers is calculated, and the optimum polishing time is calculated. A polishing controller for polishing a predetermined number of semiconductor wafers.
【請求項3】 前記膜厚測定手段は半導体ウエハーの複
数点の膜厚を測定し、その平均値を測定膜厚とすること
を特徴とする請求項2に記載の半導体ウエハーの研磨装
置。
3. The apparatus for polishing a semiconductor wafer according to claim 2, wherein said film thickness measuring means measures film thicknesses at a plurality of points on the semiconductor wafer and sets an average value as a measured film thickness.
JP27730196A 1996-09-27 1996-09-27 Polishing method and polishing apparatus for semiconductor wafer Expired - Lifetime JP3558794B2 (en)

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