JPH10106259A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of times of interruption of access from a CPU to a memory by refresh operation. SOLUTION: An I/O monitor circuit 2 monitors operation of a CPU bus 10 and delivers an I/O access signal 11 to a memory 8 at the time other than accessing time and then a refresh control circuit 5 performs refeshing operation by controlling a memory control bus 15. When the memory 8 is accessed continuously and refresh operation through the I/O access signal 11 is interrupted, a timer circuit 9 performs minimum necessary refresh operation. According to the arrangement, efficiency of access from the CPU 1 to the memory 8 can be enhanced even when continuous I/O access is followed by continuous memory access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control device of a computer device using a memory (DRAM) requiring a refresh operation.

[0002]

2. Description of the Related Art As a conventional memory control device of this type, a circuit for performing a refresh operation at regular intervals by a timer has been known for a long time.
Japanese Patent Laid-Open No. 4-13207 discloses a technique in which a refresh operation is performed at the time of access to a memory other than a memory such as an access or a ROM access to increase the efficiency of access from the CPU to the memory.
8 and JP-A-5-174574.

FIG. 5 is a block diagram for explaining the technique described in the above-mentioned publication in which a refresh operation at the time of I / O access is added to the above-mentioned known technique.

In order for the CPU 1 to access the memory 8, the CPU 1 outputs a signal to the CPU bus 10 that the access is to the memory 8. The control circuit 3 which has received this signal outputs a signal for accessing the memory 8 to the memory control bus 15. This allows the CPU 1 to access the memory 8.

[0005] Further, since the memory 8 is a memory that requires refreshing, the memory 8 requires a refresh operation. This refresh operation is realized by the timer circuit 9 performing the refresh operation at regular intervals. The refresh control circuit 50 to which the timer signal 19 output from the timer circuit 9 is input is connected to the memory control circuit 3
Outputs a bus request signal 13 to the memory control bus 1
Request a surrender of 5. The memory control circuit 3 to which the bus request signal 13 has been input interrupts access to the memory 8 at a break between cycles, and outputs a bus permission signal 12.
The refresh control circuit 50 that has received the bus permission signal 12 outputs a refresh operation control signal to the memory control bus 15, and the memory 8 that has received this signal performs the refresh operation.

An I / O monitoring circuit 2 monitoring the operation of the CPU 1 as an operation of the CPU bus 10 monitors that the CPU 1 is not accessing the memory 8 and outputs an I / O access signal 11. The refresh control circuit 50 that has received the I / O access signal 11 confirms that the memory control circuit 3 is not accessing the memory 8 by exchanging the bus request signal 13 and the bus permission signal 12, and The refresh operation is performed on the memory 8 since the I / O monitoring circuit 2 has confirmed that the access is not from the CPU 1 to the memory 8.
Can be refreshed.

Further, when a refresh operation is performed by monitoring the CPU bus 10, the refresh operation is not required by the timer circuit 9, so that the timer signal 19 output from the timer circuit 9 is input to the refresh control circuit 5. Even if the refresh control circuit 50
Is not performed.

However, in the present apparatus, the reason why the refresh operation by the timer circuit 9 is not performed is that immediately after the refresh operation by monitoring the CPU bus 10 is performed.
Only times.

[0009]

In the above-mentioned conventional memory control device, when a continuous access from the CPU to the memory is performed, the refresh by the I / O monitoring circuit added so as not to interrupt the access from the CPU to the memory. Since the operation is not performed, if the CPU continuously accesses the memory, only the refreshment by the timer circuit is performed, and the
In this case, there is a problem that the access to the memory is interrupted and the access performance to the memory is reduced.

In the present invention, by reducing the number of times that the refresh operation is performed by the timer circuit, the number of times that the access from the CPU to the memory is interrupted is reduced.
It is an object of the present invention to provide a memory control device capable of speeding up access from U to a memory.

[0011]

According to the present invention, there is provided a memory control device for forcibly performing a refresh operation of a memory at regular time intervals, wherein the refresh operation is performed by an operation other than the access to the memory. The forced refresh operation is omitted by the number of times.

More specifically, the device of the present invention is a memory control device for forcibly performing a refresh operation of a memory at fixed time intervals. In the memory control device, a timer for generating a timing which triggers a minimum refresh operation required for the memory is provided. A circuit, a timer count circuit for counting the number of times the timing has occurred, a refresh counter circuit for counting the number of refresh operations actually performed, and a comparison circuit for comparing the count numbers of the two counter circuits. The forcible refresh operation is requested only when the count number of the timer counter circuit is larger.

In the present invention, the minimum required refresh timing is generated by a timer circuit. The timer counter circuit counts this timing, and the count value of the refresh counter circuit that counts the number of refresh operations that have actually occurred. And a comparison circuit. When the count value of the timer counter circuit is larger than the count value of the refresh counter circuit, a refresh request signal is output, and the refresh operation is performed by the timer, thereby monitoring the I / O operation and the like. The number of refresh operations by the circuit can be used for the actual refresh operation without waste, and the number of refresh operations by the timer can be reduced.

[0014]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a CPU 1, an I / O monitoring circuit 2, a memory control circuit 3, a comparison circuit 4, a refresh control circuit 5, a timer counter circuit 6, and a refresh counter. It comprises a circuit 7, a memory 8, and a timer circuit 9.

When the CPU 1 accesses the memory 8, the CPU 1 outputs a signal to the CPU bus 10 indicating that the access is to the memory 8. When a signal indicating access to the memory 8 is output to the CPU 1 bus 10, the memory control circuit 3 controls the memory control bus 15 to access the memory 8. As a result, the CPU 1 has accessed the memory 8.

Since the memory 8 is a memory that requires a refresh operation, a refresh operation at regular intervals is required to retain data in addition to access from the CPU 1. The circuit that performs this refresh operation is the refresh control circuit 5. The refresh control circuit 5 has an I / O
When either the access signal 11 or the refresh request signal 14 is input, a bus request signal 13 is output to the memory control circuit 3 to request the memory control bus 15 to surrender. The memory control circuit 3 that has received the bus request signal 13 immediately outputs the bus permission signal 12 if the memory 8 is not being accessed, and cycles the access to the memory 8 if the memory 8 is being accessed. The bus permission signal 12 is output after the interruption at the break. The refresh control circuit 5 that has received the bus permission signal 12 outputs a refresh operation signal to the memory control bus 15, executes a refresh operation of the memory 8, and outputs a refresh signal 18 to the refresh counter circuit 7.

The I / O monitoring circuit 2 monitors signals on the CPU bus 10 and each time the CPU 1 accesses a device other than the memory 8, for example, an I / O or a ROM, the refresh control circuit 5. , An I / O access signal 11 is output, and a refresh operation for memory 8 is performed. In the refresh operation in this case, since the I / O monitoring circuit 2 confirms that the access is not to the memory 8, the refresh operation can be performed without interrupting the access to the memory 8 from the CPU 1.

The comparison circuit 4 counts the number of times the timer signal 19 is generated from the timer circuit 9 to generate the timing for securing the minimum required number of refreshes for the memory 8. 16 and the refresh counter value 1 of the refresh counter circuit 7 for counting the number of refresh signals 18 generated when the refresh operation is performed.
By comparing the two count values 7 and 7, when the timer counter value 16 becomes larger than the refresh counter value 17, the refresh request signal 14 is output, and the refresh operation for the memory 8 is performed. In this case, the refresh operation is performed by the timer circuit 9 which operates independently.
Since the refresh operation occurs at the timing of the occurrence of, the access from the CPU 1 to the memory 8 may be interrupted halfway.

In a general-purpose memory, the minimum required number of refreshes is 1024 times during 16 [ms].
The operation is stopped after counting to 23, and when the timer counter value 16 of the timer counter circuit 6 becomes 1024, the refresh operation is forcibly performed. As a result, when the refresh signal 18 is input, the refresh counter value 17 is returned to 0, and the operation is restarted. At this time, both the timer counter value 16 of the timer counter circuit 6 and 0 are returned. As a result, 16
This prevents 1024 or more I / O accesses from occurring during [ms], and prevents the refresh operation from occurring due to bias or refresh operation.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a time chart showing a refresh operation by I / O access according to this embodiment.

When the CPU 1 accesses the memory, C
A signal indicating a memory access is output on the PU bus 10, and a signal indicating the memory access is output to the memory control bus 15, whereby the memory access is performed.

When the CPU 1 makes an I / O access, a signal indicating the I / O access is output on the CPU bus 10, and the I / O access signal 11 output by detecting this signal is used as a trigger. When a signal indicating the refresh operation is output to the memory control bus 15, the refresh operation of the memory 8 is performed. At this time, the bus request signal 1 is used as a signal for confirming the right to use the memory control bus 15.
3 is output, but since the I / O access is being performed, the bus permission signal 12 is generated without any problem, and the refresh operation can be performed.

Further, a refresh signal 18 is generated by a refresh operation executed for each I / O access, and the refresh counter value is increased.

FIG. 3 is a time chart showing the refresh operation by the timer of the embodiment.

When the timer signal 19 is input, the timer counter value 16 increases and the refresh counter value 1
If the timer counter value 16 becomes larger than 7, the refresh request signal 14 is output. In FIG. 3, when the first timer signal 19 is generated, the refresh counter value 17 is "10" and the timer counter value 16 is "11", so that the refresh request signal 14 is generated and the bus request signal is generated. 13 outputs. At this time, since the CPU bus signal 10 is not a memory access, the bus permission signal 12 is immediately output, and a refresh operation occurs. By this refresh operation,
A refresh signal is generated and the refresh counter value 1
Since 7 is increased to “11”, the value becomes the same as the timer counter value 16, so that there is no refresh request signal.
In addition, the memory access of the CPU bus signal 10 generated during the refresh operation has to wait until the refresh operation ends because the memory control bus 15 is being used in the refresh operation.

Next, when the second timer signal 19 is generated, the timer counter value 16 becomes "12" and becomes larger than the refresh counter value 17, so that the refresh request signal 14 is output and the bus request signal 13 is also output, but since the memory control bus signal 15 is in the memory access state, the bus permission signal 12 is issued while waiting until the access to the memory is cut off. The refresh operation of the memory 8 is executed by the bus permission signal 12, and the refresh signal increases the refresh counter value 17 to terminate the refresh operation. Also in this case, the continuous access to the memory 8 of the CPU bus 10 is interrupted, and the access is waited during the refresh operation.

FIG. 4 is a time chart showing the operation of the comparison circuit 4 in this embodiment.

In FIG. 4, the refresh operation occurs four times due to the input of the I / O access signal 11 four times in succession. Due to the refresh signal 18 generated by this, the refresh counter value 17 is increased four times and “1”
It changes from “0” to “14”. Thereafter, the timer counter value 16 is increased by the generated timer signal 19, but the timer counter value 16 increases from “10” to “14” until the timer signal 19 is generated four times, but the refresh counter value is increased. The refresh operation does not occur because it is not larger than 17. Next, when the fifth timer signal 19 is generated, the timer counter value 16
Becomes “15” and the refresh counter value 17
Therefore, the refresh operation of the memory 8 occurs.

In this manner, the number of refresh operations of the memory 8 by the timer signal 19 can be reduced by the number of the I / O access signals 11.

Next, another embodiment of the present invention will be described.

In the embodiment shown in FIG. 1, the fact that the access is not from the CPU 1 to the memory 8
This is realized by monitoring the I / O access state.
Access to the cache memory using the SRAM on the CPU bus 10 that does not require a refresh operation, and the operation of the CPU 1
If the operation is such that it is possible to determine that the CPU 1 is not accessing the memory 8 by, for example, detecting an idle state where the CPU 1 is not operating by monitoring the operating state of the CPU 1, the same effect can be obtained by monitoring the operation. be able to.

Further, since the minimum required number of refreshes of a general-purpose memory is 1024 during 16 [ms], the refresh counter circuit 7 in the embodiment of FIG. It has been described that the operation is stopped. However, when the minimum required number of refreshes of the memory is generally N times during T [ms], the refresh counter circuit 7 performs the operation at (N-1) times. Stop,
The operation will be restarted when the Nth refresh operation occurs. At this time, the timer signal 19 generated by the timer circuit 9 is once every T / N [ms].

[0035]

According to the present invention, the value of the counter circuit that counts the number of times the refresh operation has occurred and the value of the counter circuit that counts the minimum number of required refresh operations by the timer are compared by the comparison circuit. , CP
Since the refresh operation by the timer is omitted by the number of times of the refresh operation generated except for the access from the U to the memory, the possibility of interrupting the access from the CPU to the memory is reduced, and the efficiency of the access from the CPU to the memory is increased. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart showing a refresh operation by I / O access in the embodiment of FIG. 1;

FIG. 3 is a time chart showing a refresh operation by a timer in the embodiment of FIG. 1;

FIG. 4 is a time chart illustrating an operation of the comparison circuit in the embodiment of FIG. 1;

FIG. 5 is a block diagram showing an example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 I / O monitoring circuit 3 Memory control circuit 4 Comparison circuit 5, 50 Refresh control circuit 6 Timer counter circuit 7 Refresh counter circuit 8 Memory 9 Timer circuit 10 CPU bus 11 I / O access signal 12 Bus permission signal 13 Bus request Signal 14 Refresh request signal 15 Memory control bus 16 Timer counter value 17 Refresh counter value 18 Refresh signal 19 Timer signal.

Claims (5)

[Claims] 1. A memory control device for forcibly performing a refresh operation of a memory at fixed time intervals, wherein the refresh operation is performed in response to an operation other than access to the memory, and the forced refresh operation is performed by the number of times. The memory control device characterized by omitting the above. 2. A timer circuit for generating a timing which triggers a refresh operation at least necessary for a memory, a timer count circuit for counting the number of times the timing has occurred, and counting the number of refresh operations actually performed. A refresh counter circuit that performs the refresh operation, and a comparison circuit that compares the count numbers of the two counter circuits, and requests the forced refresh operation only when the count number of the timer counter circuit is larger. 2. The memory control device according to claim 1, wherein: 3. An operation other than accessing the memory,
2. The memory control device according to claim 1, wherein the memory control device is an input / output device access, an access to a ROM, an access to an SRAM that does not require a refresh operation, or an idle state of a CPU. 4. The memory control device according to claim 1, wherein whether the operation is other than the access to the memory is detected by monitoring a CPU bus or a memory control bus. 5. The memory control device according to claim 1, wherein a refresh operation triggered by an operation other than an access to the memory is performed for each access.