JPH10104317A - Boundary scan malfunction prevention circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the malfunction of boundary scanning. SOLUTION: A wiring board 11 has LSI 12 and 13 with a plurality of boundary scanning mechanisms, each LSI has a test mode selection input terminal(TMS) for performing boundary scanning and a test rest input terminal(TRST), and a boundary scanning mechanism retains 'Test-Logic-Reaset' state while maintaining the TMS terminal at an H level or maintaining the TRST terminal at an L level. A boundary scanning malfunction prevention circuit is provided at a wiring board and has an external TRST terminal that is connected to the TSRT terminal, and the external TRST terminal is retained at a ground level at a back wiring board 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boundary scan malfunction prevention circuit and, more particularly, to a circuit for preventing malfunction in an integrated circuit having a boundary scan mechanism.

[0002]

2. Description of the Related Art Generally, a boundary scan (hereinafter referred to as BS)
In an integrated circuit (hereinafter abbreviated as IC) having a mechanism, a BS test (substrate manufacturing defect test and IC
5 test terminals ｛TD exclusively for internal logic test)
I (Test data input terminal: Test Data In)
put), TDO (test data output terminal (TestD
ata Output), TCK (Test Clock Input Terminal: Test Clock Input), TMS
(Test mode selection input terminal: Test Mode S
select input), TRST (test reset input terminal).

[0003] Referring to FIG. 3, in the example shown in FIG. 3, first and second LSIs 12 and 13 are mounted on a board (PWB: printed wiring board) 11, and each LSI 12 and 13 has a TDI terminal. , TDO terminal, TCK terminal, TM
An S terminal and a TRST terminal are provided (hereinafter, each terminal of the first LSI 12 is assigned a first, and a second LSI 1
2 is attached to each terminal of No. 3). On the other hand, the PWB 11 also has a TDI terminal, a TDO terminal, a TCK terminal, and a TMS terminal (hereinafter, referred to as an external TDI terminal, an external TDO terminal, an external TCK terminal, and an external TMS terminal) as external terminals.

A first TDI terminal, a first TCK terminal, and a first TMS terminal are respectively an external TDI terminal and an external TDI terminal.
Connected to the CK terminal and the external TMS terminal.
TCK terminal and the second TMS terminal are external TC
It is connected to the K terminal and the external TMS terminal. And
The voltage VDD is applied to the first TDI terminal and the first and second TMS terminals.

A power-on-clear (POC) circuit 14 is connected to the first and second TRST terminals, a first TDO terminal is connected to a second TDI terminal, and a second TD
The O terminal is connected to an external TDO terminal. PB shown
W is mounted on an electronic device (device) or the like, and this device is provided with a back wiring board (back board: BWB) 15.

In LSIs 12 and 13, TDI, T
DO, TCK and TMS terminals are IEEE114
Unused terminal processing is performed according to 9.1, and TRST
Terminals are treated as optional by IEEE 1149.1, and processing on the board is left to the circuit designer.

Each of the first and second LSIs 12 and 13 has a test access port controller (TAP: T
EST Access Ports) 12a and 13a, and each TAP controller 12a and 13
Reference numeral a denotes a state transition machine, which switches between a test operation and a normal operation of the LSI by transiting a state (state) inside the LSI in accordance with a TMS signal synchronized with a TCK signal described later.

[0008] A serial test data input signal is applied to the TDI terminal, and a serial test data output signal is output from the TDI terminal. The TCK terminal is supplied with a clock signal (TCK signal) dedicated to the boundary scan test, and the TMS terminal is supplied with a signal (TMS signal) for controlling the state transition of the TAP controller in synchronization with the TCK signal. Then, a signal (TRST signal) for changing the state of the TAP controller from the test mode to the normal mode (normal operation) with a low (L) of one TCK signal is applied to the TRST terminal.

In the above-described apparatus, when the power is turned on, the TRST terminals of the LSIs 12 and 13 are temporarily connected to the POC circuit 14 that outputs an L level, so that the states of the TAP controllers 12a and 13a are changed. Performs normal operation [Test-Logic-Reset]
Transition to the state.

In the above example, a PWB on which two LSIs are mounted has been described. However, in a PWB on which a plurality of LSIs or ICs are mounted, the TDI terminal of the first-stage LSI is connected to an external TDI terminal, and At the time of testing, test data is provided serially. Further, the TDO terminal of the first-stage LSI is connected to the TDI terminal of the next-stage LSI, and the TDO terminal of the next-stage LSI is connected to the TDI terminal of the subsequent stage. Similarly, the TDI and TDO terminals of each LSI are serially connected to form one scan path. The TDO terminal of the last LSI is connected to the external TDO.
The terminal is connected to the terminal, and the test data is output serially during the BS test.

[0011]

By the way, the above-mentioned PW
In B, the state of the TAP controller is always set to [Test-Logic-Res
t] state, which may be a temporary source. That is, if a signal for controlling the TAP controller is affected by noise or the like, the TAP state may shift to a test state. Then, when the TAP state transits from the [Test-Logic-Reset] state, the LSI enters a state where normal operation cannot be performed at all.

When such a state occurs, it is necessary to temporarily turn off (turn off) the power of the apparatus and then turn on the power again. Even if the test terminal is configured to be controllable from the outside, a high (H) level is set to 5 at the TMS terminal.
It is necessary to input more than clock.

As described above, TAP is generated by noise or the like.
When the state shifts to the test state, there is a possibility that other devices connected to the device are adversely affected. That is, P
In WB, there is a problem that malfunction of BS cannot be prevented.

An object of the present invention is to provide a circuit capable of preventing a malfunction of a BS.

[0015]

According to the present invention, a TSM terminal and a TRST terminal for performing a boundary scan are used together with a wiring board on which an integrated circuit having a boundary scan mechanism is mounted. To maintain the TSM terminal at a high level or
While the RST terminal is kept at a low level, the boundary scan mechanism performs [Test-Logic-Reset].
A boundary scan malfunction prevention circuit for maintaining a state and preventing a malfunction of the boundary scan mechanism, comprising: an external TRST terminal provided on the wiring board and connected to the TRST terminal; and an external TRST terminal. And a holding means for holding at a ground level, thereby obtaining a boundary scan malfunction prevention circuit.

Specifically, the wiring board is housed in an apparatus having a back wiring board,
The terminal is set to the ground level on the back wiring board.

As described above, the LS is connected to the back bird of the apparatus for accommodating the board via the board external terminal (TRST terminal).
Since the TRST terminal of the integrated circuit such as I is connected and the external terminal of the substrate is clamped to the ground level, the TAP state is always set to [Test-Logic-Reset] without being affected by noise or the like. State (normal operation state), and erroneous operation of the boundary scan can be prevented.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

First, the state transition by the TAP controller will be described with reference to FIG. Note that this state transition is the same as the state transition shown in IEEE1149.1.

(1) Test-Logic-Reset The test logic is set to an initial state so that the normal operation of the system logic is enabled.

(2) Run-Test / Idle This is a basic state during test execution, and a specific instruction can be executed in an intermediate state during scan operation.

(3) Select-DR-Scan Initializes the scan sequence of the test data register (BS and bypass register).

(4) Select-IR-Scan Initializes the scan sequence of the instruction register.

(5) Capture-DR This is a basic state in which a response is captured, in which data is loaded in parallel to a test data register selected by an instruction having an execution length.

(6) The test data register is connected between the TDI terminal and the TDO terminal in the Shift-DR shift state, and data is transferred one by one every time the TCK signal rises.
Shift toward O.

(7) Exit1-DR scanning is completed.

(8) Pause the shift operation of the test data register in the serial path between the Pause-DR TDI and TDO.

(9) Exit2-DR scanning is completed.

(10) Output data from the Updata-DR shift register path to the parallel output of the test data register group.

(11) Capture a fixed pattern into the Capture-IR instruction register.

(12) A Shift-IR instruction register is connected between TDI and TDO to shift data toward TDO each time the TCK signal rises.

(13) Exit1-IR scanning is completed.

(14) Pause-IR Shift operation of the instruction register in the serial path between TDI and TDO is suspended.

(15) Exit2-IR scanning ends.

(16) Update-IR Loads a new instruction into the instruction register. The instructions shifted into the instruction register are latched and output in parallel. When the latch is completed, the execution of the instruction starts.

The TAP controller transits the illustrated state diagram according to the TMS signal synchronized with the TCK signal. Further, a control signal is sent to a test circuit inside the LSI (or IC) according to each of the TAP state states described above.

While the TRST signal is at L level or the TMS signal is at H level, the TAP state is [Test-
Logic-Reset] state, and the LSI
Is normal operation. During this state, the LSI can perform input / output control between normal terminals by a user signal.

When the TMS signal goes low, the TAP state changes from the [Test-Logic-Reset] state, and the LSI enters the test state. Also, [Te
[st-Logic-Reset] state,
Normal operation of the LSI is prohibited. During the test state, input / output control of the normal terminal by the user signal becomes impossible. That is, the TAP controller is set to [Test-Log
ic-Reset] state, the H level is continuously input to the TMS terminal or the L level is input to the TRST terminal.
It is necessary to keep entering the level.

Here, the boundary scan malfunction preventing circuit according to the present invention will be described with reference to FIG. In FIG. 2, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In the illustrated device, the external TRS is connected to the PWB 11.
A T terminal is provided, a power supply voltage VDD is applied to the external TRST terminal, and the first and second TR terminals are provided.
The ST terminal is connected. Further, the external TRST terminal is connected to the back board 15, where it is clamped to the ground level. That is, an external TRST terminal, a connection line (referred to as a control line) for connecting the external TRST terminal to the first and second TRST terminals, and a connection line (referred to as a ground line) for clamping the external TRST terminal to ground level. A boundary scan malfunction prevention circuit is configured.

In the illustrated boundary scan malfunction prevention circuit, the first and second TRST terminals are connected to the external TRST terminal.
Since the signal is clamped to the ground level via the terminal (for example, the external TRST terminal is grounded by the back board 15), the signal controlling the TAP controllers 12a and 13a (that is, the TMS signal) is affected by noise or the like. The TAP state is always [T
est-Logic-Reset] state. That is, the LSI does not switch to the test operation during normal operation due to noise or the like, and
The conventionally required POC circuit becomes unnecessary.

In addition, on the back board, an external TR
Since the ST terminal is clamped to the ground level,
When performing the test operation, the first and second TRS
H level can be applied to the T terminal. That is, the TRST terminal can be controlled during the board test.

[0043]

As described above, according to the present invention, the substrate external terminal (TRS) is provided on the back bird of the apparatus for accommodating the substrate.
(T terminal), the TRST terminal of an integrated circuit such as an LSI is connected, and the external terminal of the substrate is clamped to the ground level. Therefore, the TAP state is always kept without being affected by noise or the like. [Test-Logi
[c-Reset] state (normal operation state), thereby preventing a boundary scan malfunction.

[Brief description of the drawings]

FIG. 1 is a state transition diagram for explaining a state transition of a test access controller (TAP).

FIG. 2 is a block diagram showing an example of a boundary scan malfunction prevention circuit according to the present invention together with a printed wiring board.

FIG. 3 is a block diagram illustrating a boundary scan in a conventional printed wiring board.

[Explanation of symbols]

 11 Printed Wiring Board (PWB) 12, 13 LSI 14 Power On Clear (POC) Circuit 15 Back Wiring Board (BWB)

Claims (5)

[Claims] An integrated circuit having a boundary scan mechanism is used together with a wiring board on which the integrated circuit is mounted. The integrated circuit is provided with a test mode selection input terminal and a test reset input terminal for performing a boundary scan,
While the test mode selection input terminal is kept at a high level or the test reset input terminal is kept at a low level, the boundary scan mechanism holds a test logic reset state, in order to prevent a malfunction of the boundary scan mechanism. A boundary scan malfunction preventing circuit, comprising: an external test reset input terminal provided on the wiring board and connected to the test reset input terminal; and holding means for holding the external test reset input terminal at a ground level. A boundary scan malfunction prevention circuit characterized by the following. 2. The circuit according to claim 1, wherein said holding means is ground means for grounding said external test reset input terminal. 3. The circuit for preventing malfunction of a boundary scan according to claim 1, wherein the wiring board is housed in a device having a back wiring board, and the grounding means connects the external test reset input terminal to the back wiring board. And a clamp means for clamping the connection means to the ground level with the back wiring board. 4. The circuit according to claim 1, wherein the wiring board is housed in a device having a back wiring board, and the holding means connects the external test reset input terminal to the back wiring board. 3. The circuit for preventing boundary scan malfunction according to claim 1, wherein the circuit is set to the ground level. 5. The boundary scan malfunction preventing circuit according to claim 4, wherein said holding means connects said external test reset input terminal to said back wiring board, and said holding means connects said back wiring board to said back wiring board. And a clamping means for clamping to the ground level.