JPH0998566A - Power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a desired step-up voltage stably and accurately by constituting a driver circuit such that the output signal voltage is controlled based on the output control signal from a detector and a clock signal. SOLUTION: A driver circuit 101 comprises an inverter constituted of a PMOS transistor P1 and an NMOS transistor N1. The transistor P1 has a gate receiving the output from an OR circuit 110 which receives a clock signal CLK and a control signal CTL from a detector 104 while the transistor N1 has a gate receiving the clock signal CLK. The inverter delivers an output voltage to node E1. Time lag of a first delay circuit 113 is substantially zero when V1 is inputted as one output CLKB of a flip-flop and a signal is produced as one input CLKMB2 of the flip-flop. When GND is inputted, a signal is outputted with a predetermined time lag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for raising or lowering a constant power supply voltage, and more particularly to a low power consumption power supply circuit which suppresses voltage fluctuation during load operation.

[0002]

2. Description of the Related Art Conventionally, a power supply circuit using a charge pump circuit has been proposed, for example, Japanese Patent Laid-Open No. 4-162560.
FIG. 5 shows a basic configuration of a booster power supply circuit using the charge pump circuit shown in the publication. This power supply circuit generates a voltage V2 that is boosted higher than the high-potential-side power supply voltage V1 supplied from the outside, detects a variation from the generated voltage V2 and a desired boosted voltage V3, and Detector 504 which outputs a control signal according to the control signal, a voltage controlled oscillator 503 in which a cycle of a clock signal CLK generated according to the control signal is modulated, and a generated clock signal C.
The driver circuit 501 outputs a voltage to the output node E1 based on LK, and the charge pump circuit 502 boosts the output voltage of the driver circuit 501. Then, the voltage V2 generated by the charge pump circuit 502 is stably held by the holding capacitor C0, and the boosted voltage is supplied to the load 505.

Here, the voltage-controlled oscillator 503 is a PMO.
For example, five S-transistors P4 and inverters 511 including NMOS transistors N4 are connected in a ring shape. And V generated by the detector 504
Control signal CT corresponding to the displacement ΔV2 from the set value V3 of 2
The gate voltage of N4 is controlled by L, and the inverter 511
By varying the operating speed of the clock signal CLK. The driver circuit 501 is composed of a PMOS transistor P3 and an inverter of an NMOS transistor N3. Further, the charge pump circuit 502 includes diodes D1 and D2 and a pump-up capacitor C1.

The voltage V generated in this power supply circuit
2 is expressed by the following equation using the current Iw consumed by the load 105 and the current Is supplied to the load 505 by the power supply circuit. V2 = V3 + ΔV2 = V3 + 1 / C0 · ∫ (Is−Iw) · dt (1) where V3 is the target set value of V2 and ΔV2 is the variation value of V2 from V3.

Now, the supply current Is will be described. (A) When CLK = GND The output CLK of the voltage controlled oscillator 503 is the ground voltage (hereinafter,
Figure 6 shows the operation waveforms of each node when transitioning to GND).
(A). In the initial state, CLK = V1, and therefore the potential of the output node E1 of the driver circuit 501 is GND.
Therefore, the internal node E2 of the charge pump circuit 502 is charged up to V1-Vd through D1. Where Vd is the voltage drop across the diode. CL
When K = GND is given, P3 is turned on, N3 is turned off, and E1 is charged. Due to the coupling that occurs on both sides of C1, first, E1 and E2 are V2-V
It rises to 1 + 2Vd and V2 + Vd. Then, when E2 rises above V2 + Vd, D2 turns on, and the electric charge becomes V2.
Supplied to At this time, the same amount of charge is transferred to E through P3.
Charged to 1. Charges are supplied until E1 finally reaches V1, and the total amount of charges Qs supplied by this one operation is given by the following equation. Qs = C1. (2.V1-V2-2.Vd) (2)

(B) In the case of CLK = V1 FIG. 6 (b) shows the operation waveform of each node in the case of transition to CLK = V1. In the initial state, CLK = GND,
Therefore, the potential of E1 is V1, the supply of charges to the load performed through D2 is completed, and E2 becomes V2 + Vd. Here, when CLK = V1 is given, P3 is turned off, N3 is turned on, and the electric charge of E1 is discharged. E
1 finally drops to GND, but due to the coupling that occurs at both ends of C1, when E2 drops below V1-Vd, D1 turns on and E2 is charged, and E2 is V
Keep 1-Vd. At this time, the total charge amount of charge and discharge is equal to Qs.

Here, it is assumed that the load consumes charges of Qs / 2 and Qs / 3 in a certain cycle T, as shown in FIG. From the equation (1), in order to minimize the variation ΔV2 of V2 from the target design value, the load consumption current Iw and the power supply circuit supply current Is must be matched. Further, according to the above operation principle, the clock signal CLK
The total amount of charge that the power supply circuit supplies to the load during one cycle of
It is. Therefore, in this power supply circuit, ΔV2 is minimized by using the voltage controlled oscillator 503 to modulate the cycle of the clock signal CLK into T, 2T, and 3T, respectively.

[0008]

As described above, in the conventional power supply circuit, the period of the clock signal CLK for driving the driver circuit 501 is controlled so that Iw and Is in the equation (1) are made equal to each other and set to the set value V3. The generation control of the near boosted voltage V2 was performed. However, in this circuit operation, even if the load consumption current Iw suddenly changes within one cycle of the clock signal CLK generated from the voltage controlled oscillator 503,
In principle, it was not possible to control the boosted voltage. In such a case, the maximum amount of boost voltage fluctuation is
This occurs when the load suddenly stops consuming the current Iw, but the charge pump circuit 502 cannot stop its operation and supplies the charge for one pumping operation to the load, and the maximum value of ΔV2 is given by the following equation. ΔV2 (max) = 1 / C0 · ∫Is · dt = Qs / C0 = C1 / (C0 + C1) · (2 · V1-V2-2 · Vd) (3)

In general, it is difficult for the voltage controlled oscillator 503 to accurately determine the CLK cycle, and even if there is no sudden change in the load current, the displacement of the boosted voltage V2 from the target set value V3 is always constant. In addition to this, in the case where the displacements shown in equation (3) overlap, the maximum value of ΔV2 is C1 / (C0 + C1) · (2 · V1-V2-2 ·
Vd) will be even larger. Furthermore, since the conventional voltage controlled oscillator is a ring type, it consumes a large amount of power. An object of the present invention is to provide a power supply circuit that can solve the problems of the conventional power supply circuit as described above and can stably and more accurately generate a desired boosted voltage.

[0010]

A power supply circuit of the present invention includes an oscillator for generating a clock signal, a driver circuit for alternately outputting a power supply voltage and a ground voltage as a driver signal voltage in response to the clock signal, and the driver. A charge pump circuit that is charged by a signal voltage and outputs a predetermined voltage, and a detector that detects a change in the voltage output from the charge pump circuit and is supplied to a load and outputs a control signal corresponding to the change. The driver circuit is characterized in that the output signal voltage is controlled based on the output control signal of the detector and the clock signal.

Here, the driver circuit is constructed as an inverter in which two MOS transistors are connected in series, and a clock signal is input to the gate of one of the MOS transistors, and the clock signal and the output of the detector are input to the gate of the other MOS transistor. A logical product or a logical sum signal of the control signals is input. The oscillator also includes a circuit for switching the high level and low level states of the clock signal, a first delay element for outputting a signal for switching the clock signal from the high level to the low level, and a signal for switching the low level to the high level. A second delay element for outputting, the second delay element outputs a switching signal according to a comparison result obtained by comparing the output of the driver circuit and a predetermined voltage, and the first delay element changes the state of the clock signal. After that, a switching signal is output after a fixed time.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment in which the present invention is applied to a boost power supply circuit. The detector 104, the charge pump circuit 102, and the storage capacitor C0 have the same configuration as the conventional circuit shown in FIG. 5, and the detector 104 has the boosted voltage V2 generated by the power supply circuit and the fluctuation from the desired boosted voltage V3. Is detected and the control signal CTL is output. The charge pump circuit 102 includes diodes D1 and D2 and a pump-up capacitor C1 and boosts the voltage of the node E1 to V2. Further, the storage capacitor C0 is used to stably hold V2.

An oscillator 103 for generating a clock signal CLK and a driver circuit 101 for driving the charge pump circuit 102 using the control signal CTL output from the detector 104 and the clock signal CLK from the oscillator 103 are provided. I have it. The driver circuit 10
1, V1 is supplied as a power supply voltage to the charge pump circuit 102 and the oscillator 103. Further, the load 105 is supplied with the voltage V2 and the current Is, and the load consumes the current Iw.

In the driver circuit 101, an inverter is composed of a PMOS transistor P1 and an NMOS transistor N1, and the clock signal C is provided at the gate of P1.
The output of the OR circuit 110 that receives LK and the control signal CTL from the detector 104 is input, and the clock signal CLK is input to the gate of N1. Then, the output of this inverter outputs a voltage to the node E1.

Further, the oscillator is connected to a flip-flop in which a NAND circuit 111 is connected and connected, a first delay element 113 connected between one output and an input of the flip-flop, and the other input. And a second delay element 114. As shown in FIG.
The first delay element 113 outputs a signal as one input CLKB2 of the flip-flop with almost no time delay when V1 is input as one output CLKB of the flip-flop, and has a constant time when GND is input. A signal is output with a delay, and the output state of the flip-flop is switched according to each signal.

Further, as shown in FIG. 2, the second delay element 1
Reference numeral 14 is composed of a differential amplifier 112 for comparing the output E1 of the driver circuit 101 with V1, and E1 <V1, that is, the case where the charge pump circuit 102 has a charge supply capability to the load, and E1 = V1, that is, charge. When the pump circuit 102 finishes supplying the electric charge to the load and the pump-up capacitor C1 needs to be charged, a signal is output and the output state of the flip-flop is switched. As a result, the first delay element 113 determines the time T1 when CLK = V1, and the second delay element 114 determines the time CLK.
The time T2 when = GND is determined.

The operation of the power supply circuit having the above configuration will be described with reference to FIG. Here, the detector 104 has V2> V3
It is assumed that V1 is output in the case of and GND is output in the case of V2 ≦ V3. Such a detector can be easily configured by using a commonly used differential amplifier.

(A) When CLK = GND and CTL = GND (V2≤V3) Since the OR circuit 110 outputs GND, P1 is turned on,
N1 is turned off, and electric charge is supplied to E1 through P1. As a result, as in the conventional example, E2 to diode D
The electric charge (current Is) is supplied to the load 105 through No. 2.
In response to the supply of electric charges, the potential of E1 rises from GND toward V1.

(B) When CLK = GND and CTL = V1 (V2> V3) Since the OR circuit 110 outputs V1, both P1 and N1 are turned off, and the charge is temporarily supplied to E1 through P1. Be stopped. Therefore, the supply of charges from E2 to the load is also temporarily stopped. Meanwhile, the potential of E1 is held at a constant value in the middle of GND and V1.

(C) When CLK = V1 Since the OR circuit 110 outputs V1, P1 is off and N
1 is turned on, and the electric charge is discharged from E1 through N1. During this period, E2 passes through D1 as in the conventional example to V1-Vd.
Is charged, and the pump-up capacity C1 for the operation of the above 1) is charged.

As described above, in the power supply circuit of this embodiment, even when the clock signal CLK is at a constant GND, that is, at a timing corresponding to one cycle of the CLK signal, V2 by the detector 104 and the boosted voltage set value V3 are set. The operation modes of (a) and (b) can be switched according to the comparison result CTL of. That is, since it is possible to switch the supply of the electric charge from the power supply circuit to the load and the suspension of the supply within one cycle of the clock signal CLK, which has been impossible in the past, it is possible to control the boosted voltage with higher accuracy. It has become possible.

As described above, in the power supply circuit of this embodiment,
Based on the principle described in the section of the prior art, the charge pump circuit 102 utilizes the fact that the amount of charge supplied to V2 through D2 is equal to the amount of charge charged to E1 through P1 of the driver circuit 101. 10
This means that the gate voltage of P1 of 1 is controlled by the CTL signal to control the charge amount supplied to E1, that is, the charge amount (current amount Is) supplied to the load 105. Therefore, in the present invention, the output current of the driver circuit 101 is controlled by the output of the detector 104, and thereby the supply current to the load 105 of the power supply circuit is controlled.

In the power supply circuit described above, the relationship between the actually generated voltage V2 and the desired boosted voltage V3,
It is assumed that the delay time from when the relationship between V2> V3 and V2 ≦ V3 is reversed until the power supply circuit stops or starts the current supply is t0. Then, consider a case where the current consumption of the load repeats 0 and I0 every time t1. In the case of the conventional power supply circuit, the maximum C1 / (C0 + C)
1) V2 varies by (2V1-V2-2Vd).
On the other hand, in the case of the power supply circuit of the present embodiment, due to the existence of the delay time t0, V2 varies by ± I0 · t0 / C0 across V2. Here, C1 * (2V1-V2-2Vd) can be represented by I0 * t2. However, t2 is the maximum period of the oscillator in the power supply circuit, and is usually 10 times or more than t0. Further, since C0 >> C1, V of the conventional power supply circuit is
2 fluctuations are I0 · t2 / C0, which is more than 5 times 2 · I0 · t0 / C0 of the V2 fluctuations of the power supply circuit of the first embodiment. Therefore, according to the present invention, V2 is 1 of the conventional variation amount.
It can be reduced to about / 5.

In the operation mode (c), that is, when CLK = V1, the pump-up capacitor C1 is charged through V1 through D1, and current cannot be supplied to the load during this period. It is in a state. Therefore, in the configuration of FIG. 1, even if V2 falls below V3 during this period, the boosted voltage cannot be controlled. Therefore, as shown in FIG. 3, the driver circuit 101 and the charge pump circuit 1
A plurality of sets of 02 (n sets, n is an integer of 2 or more) may be installed, and an oscillator 201 may be provided to provide multiphase clock signals having different phases. N in the simplest case
= 2, two sets of driver circuit 101 and charge pump circuit 102 are prepared, and clock signals CLK having phases different by 180 degrees are given to them. As a result, even if the driver circuit of the first set is in the operation mode of (c), the driver circuits of the other set can be set to the operation mode of (a) or (b), and the charge pump of either set is always operated. It becomes possible to supply current to the load.

The second embodiment of the driver circuit and the oscillator circuit in the embodiment in which the present invention is applied to the step-down power supply circuit.
FIG. 4 shows a circuit connection state of the differential amplifier 112 which is a delay element.
Shown in The driver circuit uses P2 for charging E1 and E1
AND that inputs N2 and CTL and CLK
It is composed of a circuit 115. However, the AND circuit 115
When one of CTL and CLK is GND, GND is output, and when both are V1, V1 is output. When CLK = V1, the current flowing through N2 can be stopped and restarted according to the output CTL of the detector 104. In addition, the second delay element 1
The differential amplifier 112 functioning as 14A includes E1 and GN.
D is compared and a coincidence signal is output when E1 = GND.

[0026]

As described above, the present invention provides a driver circuit for alternately outputting the power supply voltage and the ground voltage to the charge pump circuit so that the charge pump circuit outputs a predetermined voltage. It is configured to control based on the output control signal from the detector that detects the fluctuation of the voltage that is output from the device and is supplied to the load and outputs the control signal corresponding to this, and the clock signal generated by the oscillator. Therefore, even within one cycle of the clock signal,
It is possible to switch the supply of electric charges from the power supply circuit to the load and the suspension of the supply, the voltage can be controlled with higher accuracy, and the output voltage can be stabilized. Also,
Since it is not necessary to configure the oscillator with a ring-type circuit like the conventional voltage controlled oscillator, it is effective in reducing power consumption.
Further, since the delay element is operated by using the output of the driver circuit to which the clock signal is input, it is possible to accurately determine the cycle.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a power supply circuit of the present invention.

FIG. 2 is a signal waveform diagram showing a relationship between a clock signal of an oscillator circuit, a control signal of a detector, and a driver output.

FIG. 3 is a circuit diagram of an improved embodiment of the present invention.

FIG. 4 is a partial circuit diagram of an embodiment in which the present invention is applied to a step-down power supply circuit.

FIG. 5 is a circuit diagram of an example of a conventional power supply circuit.

6 is a signal waveform diagram showing a relationship between a clock signal and an output in the power supply circuit of FIG.

FIG. 7 is a diagram for explaining a control method for a load in the power supply circuit.

[Explanation of symbols]

 101 driver circuit 102 charge pump circuit 103 oscillator 104 detector 105 load 110 OR circuit 111 NAND circuit 112 differential amplifier 113 first delay element 114 second delay element P1, N1 MOS transistor V1 power supply voltage C1 pump-up capacitance

Claims (6)

[Claims] 1. An oscillator that generates a clock signal, a driver circuit that alternately outputs a power supply voltage and a ground voltage as driver signal voltages in response to the clock signal, and a predetermined voltage that is charged by the driver signal voltage and that outputs a predetermined voltage. And a detector that detects a change in the voltage output from the charge pump circuit and supplied to the load and outputs a control signal corresponding to the change, and the driver circuit outputs the output of the detector. A power supply circuit characterized in that the output signal voltage is controlled based on a control signal and the clock signal. 2. The driver circuit is configured as an inverter in which two MOS transistors are connected in cascade, one of the MOS transistors receives a clock signal at its gate, and the other MOS transistor has its gate controlled by the clock signal and the output control of the detector. The power supply circuit according to claim 1, wherein a logical product or a logical sum signal of the signals is input. 3. The oscillator comprises a circuit for switching between a high level and a low level of a clock signal, a first delay element for outputting a signal for switching the clock signal from a high level to a low level, and a low level to a high level. A second delay element for outputting a switching signal, wherein the second delay element outputs a switching signal according to a comparison result obtained by comparing the output of the driver circuit with a predetermined voltage, and the first delay element is a clock signal. 3. The power supply circuit according to claim 1 or 2, wherein a switching signal is output after a certain period of time after the state change. 4. The second delay element compares the output of the driver circuit with the power supply voltage, outputs a switching signal when the power supply voltage becomes higher than the output voltage, and the charge pump circuit has the power supply voltage. 4. The power supply circuit according to claim 1, wherein the power supply circuit is configured to output a boosted voltage. 5. The second delay element compares the output of the driver circuit with the ground voltage, outputs a switching signal when the ground voltage becomes lower than the output voltage, and the charge pump circuit outputs the switching signal. The power supply circuit according to any one of claims 1 to 3, wherein the power supply circuit is configured to be able to output a voltage that is lower than that. 6. A plurality of sets of driver circuits and charge pump circuits are connected in parallel, and clock signals having different phases are input to the respective driver circuits.
Either power circuit.