JPS5858863A - Switched capacitor transformer - Google Patents

Abstract

PURPOSE:To enable to integrate a switched capacitor transformer by alternately operating (m) pieces of SC transformers connected in parallel with each other with clock signals displaced in phase by 2pi/m, thereby performing the increase in the output power and the decrease in the ripple content ratio. CONSTITUTION:Phase switches 3-5, 15-18 and phase switches 6-9, 12-14 are switched in response to two-phase signals displaced in phase by pi rad. When one clock signal is positive in the first switched capacitor (SC) transformer, phase switches 3, 4, 5 are conducted to store energy in condensers 1, 2 from an input power source 19. Since phase switches 15, 16, 17, 18 are conducted in the second SC transformer connected in parallel with the first transformer, the already existing energy of the condensers 10, 11 is supplied to a load 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switched capacitor transformer (hereinafter referred to as an SC transformer).

A conventional SC transformer driven by a single clock signal is charged and discharged every half cycle, so that the output is only available for half a cycle between -cycles. For this reason,
In order to increase the output power, it is necessary to increase the capacitance of the capacitor or increase the clock frequency.

However, increasing the capacitance of the capacitor makes integration difficult, and increasing the clock frequency increases switching loss and reduces efficiency.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated SC transformer which eliminates the above-mentioned drawbacks, increases output power and reduces ripple content.

The SC transformer of the present invention is configured such that each of m (an integer of 2 or more) SC transformers connected in parallel is operated alternately by a clock signal whose phase is shifted by 2π/m (rad). There is.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and shows the circuit configuration of a step-down SC transformer with a transformation ratio of 1/2. By connecting the part surrounded by the broken line with (n-1) steps i, an arbitrary metamorphic ratio of 1/n (where n is a positive integer) of 8 can be obtained.
A C transformer is obtained.

Figure 2 (a) is a waveform diagram of the clock signal ^ and φ0, Figure 2 (b) is a voltage waveform diagram across capacitors 1 and 20,
FIG. 3(C) is a voltage waveform diagram across the capacitors 10 and 110, and FIG. 2(d) is a voltage waveform diagram across the load 200.

In FIG. 1, phase switches 3 to 5.15 to 18 and phase switches 6 to 9.12 to 14 are π (r
ad) Performs a switching operation in response to phase-shifted two-phase signals φ and φ. In the first SC transformer,
When the clock signal φ is a positive voltage, the phase switch 3
．． 4 and 5 conduct and connect the input power supply 19 to the capacitor 1.
And energy is stored in 2. At this time, in the second SC transformer connected in parallel with the first transformer, its phase switches 15, 16, 17 and 18
Since the capacitors 10 and 11 are conducting, the energy of the capacitors 10 and 11 is supplied to the load 20.

Further, when the clock signal φ0 is a positive voltage, the phase switches 6.7.8.9 and 12,1 which were in a non-conducting state are
3.14 conducts, the energy of capacitors 1 and 2 is supplied to load 20, and the energy from input power supply 19 is stored in capacitor 10 and T1.

By repeating the above operation, two S connected in parallel
Because the C transformer supplies energy to the load 20 alternately every half cycle, the output power is doubled compared to an SC transformer operating with a single clock signal.

In this embodiment, a case has been described in which two SC transformers are connected in parallel and operated by clock signals with a phase shift of π (rad).
More than! ! ) transformers are connected in parallel and each transformer is 2π/m (
By configuring the clock signals to be operated alternately using clock signals whose phases are shifted by rad), an output power that is m times as large as that when operating with a single clock signal can be obtained.

As described above, the present invention has the advantage of increasing output power and reducing ripple content, and facilitating integration.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, and Figure 2 (
FIG. 3A is a clock signal waveform diagram, FIGS. 3B and 3C are voltage waveform diagrams of each capacitor, and FIG. 3D is a load voltage waveform diagram. In the figure, 1.2.10.11... Capacitors, 3 to 9,
■12~18... Phase switch, 19/old/
・Input power supply 1.20...Load. Agent: Susumu Uchihara, patent attorney 1. Pawani...；゛、
・ ゝ～゛～-1 Dormitory 1 Diagram (V) (ku) (shi) Mine Z Continuation from page 1 ■Applicant Takahiro Inoue Kumamoto City Koto-4-1 Koto Dormitory IT-302 ■Applicant Nihonmatsu Corpo 202, 2752 Suya, Nishigoshi-cho, Kikuchi-gun, Kumamoto Prefecture, Ota Part

Claims (1)

[Claims] It is characterized in that each of m (m is an integer of 2 or more) switched capacitor transformers connected in parallel is configured to operate alternately using clock signals whose phases are shifted by 2π rad. Switched capacitor transformer.