JPH0997929A - Chip type led, led array and manufacture thereof - Google Patents

Chip type led, led array and manufacture thereof

Info

Publication number
JPH0997929A
JPH0997929A JP25310895A JP25310895A JPH0997929A JP H0997929 A JPH0997929 A JP H0997929A JP 25310895 A JP25310895 A JP 25310895A JP 25310895 A JP25310895 A JP 25310895A JP H0997929 A JPH0997929 A JP H0997929A
Authority
JP
Japan
Prior art keywords
chip
led
wire
conductor pattern
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25310895A
Other languages
Japanese (ja)
Inventor
Tsutomu Sawabe
勉 澤邊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP25310895A priority Critical patent/JPH0997929A/en
Publication of JPH0997929A publication Critical patent/JPH0997929A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase the bonding strength of a wire which connects a LED chip to 8 conductor pattern on a substrate and reduce dispersion of the bonding strength. SOLUTION: Terminals 12 and 13 are formed at both ends of a chip substrate 11. A LED chip 17 is bonded onto the substrate 11 and wire-bonded to a conductor pattern 15 on the substrate and the chip 17 or wire-bonded zone is sealed with a light-permeable mold resin 20 to form a chip type LED 1. Bonding wire 19 runs perpendicularly to the axial line X passing through both terminals 12 and 13 of the substrate 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【技術分野】本願発明は、チップ型ＬＥＤ、ＬＥＤアレ
イおよびそれらの製造方法に関する。TECHNICAL FIELD The present invention relates to a chip-type LED, an LED array, and a method for manufacturing them.

【０００２】[0002]

【従来の技術】回路基板上に面実装可能な小型の発光素
子として、チップ型ＬＥＤがある。このチップ型ＬＥＤ
１０の従来の代表的な形態を図９に示す。平面視長矩形
状をしたチップ基板１１の上面長手方向両端部には、そ
れぞれ電極被膜１２，１３が形成され、各電極被膜１
２，１３は、基板の側面から裏面に回り込まされて、端
子部１２′，１３′を形成している。基板１１の表面に
おいて、一方の電極被膜１２に導通する第１の導体パタ
ーン１４と、他方の電極被膜１３に導通する第２の導体
パターン１５とが形成されている。第１の導体パターン
１４に設定されたチップボンディング部１６には、ＬＥ
Ｄチップ１７がボンディングされる。また、第２の導体
パターン１５には、ワイヤボンディング部１８が設定さ
れる。ＬＥＤチップ１７の上面パッドと上記第２の導体
パターン１５上のワイヤボンディング部１８との間は、
ボンディングワイヤ１９によって結線されている。そし
て、上記ＬＥＤチップ１７ないしボンディングワイヤ１
９は、透明または半透明のモールド樹脂２０で封止され
ている。また、図９に示す形態を単位としてこれを複数
一体化させたものが、ＬＥＤアレイと呼ばれるものであ
る。2. Description of the Related Art A chip-type LED is known as a small-sized light emitting element that can be surface-mounted on a circuit board. This chip type LED
FIG. 9 shows 10 conventional typical configurations. Electrode coatings 12 and 13 are formed on both ends in the upper surface longitudinal direction of the chip substrate 11 having a rectangular shape in plan view.
2 and 13 are wrapped around from the side surface of the substrate to the back surface to form terminal portions 12 'and 13'. On the surface of the substrate 11, a first conductor pattern 14 that conducts to the one electrode coating 12 and a second conductor pattern 15 that conducts to the other electrode coating 13 are formed. LE is attached to the chip bonding portion 16 set in the first conductor pattern 14.
The D chip 17 is bonded. Further, the wire bonding portion 18 is set on the second conductor pattern 15. Between the upper surface pad of the LED chip 17 and the wire bonding portion 18 on the second conductor pattern 15,
It is connected by a bonding wire 19. Then, the LED chip 17 or the bonding wire 1
9 is sealed with a transparent or semitransparent mold resin 20. Further, an LED array is formed by integrating a plurality of the forms shown in FIG. 9 as a unit.

【０００３】図９に表れているように、上記従来のチッ
プ型ＬＥＤ１０においては、チップボンディング部１６
とワイヤボンディング部１８とは、チップ基板１１の長
手方向に隣接して設定されている。したがって、チップ
ボンディング部１６にボンディングされるＬＥＤチップ
１７の上面パッドとワイヤボンディング部１８との間を
つなぐワイヤ１９は、チップ基板１１の長手方向に延び
ている。As shown in FIG. 9, in the conventional chip type LED 10 described above, the chip bonding portion 16 is used.
And the wire bonding portion 18 are set adjacent to each other in the longitudinal direction of the chip substrate 11. Therefore, the wire 19 connecting the upper surface pad of the LED chip 17 bonded to the chip bonding portion 16 and the wire bonding portion 18 extends in the longitudinal direction of the chip substrate 11.

【０００４】上記のチップ型ＬＥＤ１０は、効率的な製
造を行うべく、大略次のようにして製造される。まず、
図１０および図１１に示すような材料基板３０が準備さ
れる。この材料基板３０は、基本的にはガラスエポキシ
等でできた板の上面にパターン化された導体被膜を形成
したものであるが、目的とするチップ型ＬＥＤ１０の表
面電極被膜１２，１３を都合よく側面二次電極１２ａ，
１３ａないし裏面三次電極１２ｂ，１３ｂにつなげるた
めに、複数本のスリット３１を形成することにより、複
数本の桟３２を形成した形態をもっている。The chip type LED 10 is manufactured in the following manner in order to manufacture it efficiently. First,
A material substrate 30 as shown in FIGS. 10 and 11 is prepared. This material substrate 30 is basically a plate made of glass epoxy or the like with a patterned conductor film formed on the upper surface thereof, but the desired surface electrode films 12, 13 of the chip-type LED 10 can be conveniently formed. Side surface secondary electrode 12a,
A plurality of crosspieces 32 are formed by forming a plurality of slits 31 in order to connect to the back surface tertiary electrodes 13b from 13a.

【０００５】図１１に示すように、各桟３２の両側縁部
には、第１電極被膜１２と第２電極被膜１３とが相互対
向状に形成される。また、第１電極被膜１２から桟３２
の幅方向に延びる複数の第１導体パターン１４が等間隔
に形成されるとともに、第２電極被膜１３から桟３２の
幅方向に延びる複数の第２導体パターン１５が等間隔に
形成される。材料基板３０の表面に形成されるこれら第
１および第２電極被膜１２，１３、ならびに、第１およ
び第２導体パターン１４，１５は、上記スリット３１を
形成する前の材料基板３０の表面に対し、導体を印刷ま
たは蒸着等によって全面形成し、不要部分をエッチング
等によって除去する等して形成することができる。スリ
ット３１の内面には、二次電極被膜１２ａ，１３ａが形
成され、さらに、材料基板３０の裏側、すなわち各桟３
２の裏側には、三次電極１２ｂ，１３ｂが形成されてい
る。As shown in FIG. 11, a first electrode coating 12 and a second electrode coating 13 are formed on both side edges of each crosspiece 32 so as to face each other. In addition, from the first electrode coating 12 to the crosspiece 32
The plurality of first conductor patterns 14 extending in the width direction are formed at equal intervals, and the plurality of second conductor patterns 15 extending in the width direction of the crosspiece 32 from the second electrode coating 13 are formed at equal intervals. The first and second electrode coatings 12 and 13 and the first and second conductor patterns 14 and 15 formed on the surface of the material substrate 30 are different from the surface of the material substrate 30 before the slit 31 is formed. The conductor can be formed by printing, vapor deposition or the like on the entire surface, and removing unnecessary portions by etching or the like. Secondary electrode coatings 12a and 13a are formed on the inner surface of the slit 31, and the back side of the material substrate 30, that is, the crosspieces 3 are formed.
On the back side of 2, the tertiary electrodes 12b and 13b are formed.

【０００６】上記のような材料基板３０に対し、各桟３
２の第１電極被膜１２に導通する第１導体パターン１４
上には、それぞれＬＥＤチップ１７がボンディングされ
る。そうして、各ＬＥＤチップ１７の上面パッドと第２
導体パターン１５との間は、ボンディングワイヤ１９に
よって結線される。各桟３２にその長手方向に並ぶ各チ
ップボンディング部１６の全てにＬＥＤチップ１７をボ
ンディングし、かつ所定のワイヤボンディングがなされ
ると、各桟３２の上面をその長手方向に一連に覆うモー
ルド樹脂２０が、たとえばトランスファモールド法によ
って形成される（図１５）。次に、各桟３２を、図１１
に破線で示すように一定長さごとに切断すると、図９に
示した単位チップ型ＬＥＤ１０が得られる。また、図１
１に示される破線の部位を複数番目おきに切断すること
により、複数個のＬＥＤチップ１７が搭載されたＬＥＤ
アレイが得られる。For each of the material substrates 30 as described above, each bar 3
The first conductor pattern 14 that is electrically connected to the first electrode coating 12 of No. 2
The LED chips 17 are respectively bonded on the upper side. Then, the upper surface pad of each LED chip 17 and the second
A bonding wire 19 connects the conductor pattern 15 and the conductor pattern 15. When the LED chips 17 are bonded to all of the chip bonding portions 16 arranged in the longitudinal direction on the bars 32 and predetermined wire bonding is performed, the molding resin 20 that covers the upper surfaces of the bars 32 in the longitudinal direction in series. Are formed by, for example, the transfer molding method (FIG. 15). Next, each bar 32 is shown in FIG.
When the unit chip type LED 10 shown in FIG. 9 is obtained by cutting at a constant length as indicated by a broken line in FIG. Also, FIG.
An LED in which a plurality of LED chips 17 are mounted by cutting the broken line portion shown in FIG.
An array is obtained.

【０００７】ところで、ＬＥＤチップ１７の上面パッド
と第２導体パターン１５との間のワイヤボンディング
は、キャピラリ４０と呼ばれるボンディングツールを使
用し、上記ＬＥＤチップ１７の上面パッドにいわゆるフ
ァーストボンディングをし、上記第２導体パターン１５
に対して、いわゆるセカンドボンディングをすることに
よって行われる。By the way, for wire bonding between the upper surface pad of the LED chip 17 and the second conductor pattern 15, a bonding tool called a capillary 40 is used to perform so-called first bonding on the upper surface pad of the LED chip 17, and Second conductor pattern 15
On the other hand, so-called second bonding is performed.

【０００８】すなわち、図１２に示すように、材料基板
３０ないしＬＥＤチップ１７を所定の加熱状態においた
上で、キャピラリ４０から導出される金線ワイヤ１９に
加熱溶融によるボール１９ａを形成し、図１３に示すよ
うにキャピラリ４０をＬＥＤチップ１７の上面パッドに
圧しつけることにより、上記ボール１９ａをネイルヘッ
ド状に加熱圧着して上記ファーストボンディングを行
い、次いで図１４に示すようにキャピラリ４０を第２導
体パターン１５上に移動させ、そうしてキャピラリ４０
をこの第２導体パターン１５上に所定の圧力で圧しつ
け、ワイヤ１９の他端部を第２導体パターン１５の上面
に熱圧着させる。そして、特にこのセカンドボンディン
グによるワイヤ１９と第２導体パターン１５との接続強
度を上げるために、いわゆる超音波接合と呼ばれる手法
が併用される。すなわち、上記キャピラリ４０は、超音
波ホーン４１に接続されており、上記キャピラリ４０を
第２導体パターン１５に圧しつけて金線ワイヤのセカン
ドボンディングを行うに際し、上記キャピラリ４０を水
平方向に超音波振動させる。このような超音波振動に起
因して生じる摩擦熱が、ワイヤ１９と第２導体パターン
１５との間の熱圧着接合を支援する。That is, as shown in FIG. 12, after the material substrate 30 or the LED chip 17 is heated in a predetermined state, a ball 19a is formed on the gold wire 19 drawn from the capillary 40 by heating and melting. As shown in FIG. 13, the capillaries 40 are pressed against the upper surface pads of the LED chips 17, so that the balls 19a are thermocompression-bonded in a nail head shape to perform the first bonding, and then the capillaries 40 are secondly bonded as shown in FIG. Move it onto the conductor pattern 15 and then the capillary 40
Is pressed against the second conductor pattern 15 with a predetermined pressure, and the other end of the wire 19 is thermocompression-bonded to the upper surface of the second conductor pattern 15. Then, in particular, in order to increase the connection strength between the wire 19 and the second conductor pattern 15 by this second bonding, a so-called ultrasonic bonding method is used together. That is, the capillary 40 is connected to the ultrasonic horn 41, and when the capillary 40 is pressed against the second conductor pattern 15 to perform the second bonding of the gold wire, the capillary 40 is ultrasonically vibrated in the horizontal direction. Let Friction heat generated due to such ultrasonic vibration assists thermocompression bonding between the wire 19 and the second conductor pattern 15.

【０００９】通常、上記超音波振動の方向は、ワイヤ１
９が延びる方向に設定される。上記したことから判るよ
うに、従来のチップ型ＬＥＤの製造において、ワイヤボ
ンディングにおいてワイヤが延びる方向は、材料基板３
０における桟３２の幅方向となる。したがって、上記超
音波振動の方向もまた、材料基板３０における各桟３２
の幅方向となる。Usually, the direction of the ultrasonic vibration is the wire 1
9 is set in the extending direction. As can be seen from the above, in the manufacture of the conventional chip type LED, the direction in which the wire extends in the wire bonding is the material substrate 3
It is the width direction of the crosspiece 32 at 0. Therefore, the direction of the ultrasonic vibration also depends on the crosspieces 32 in the material substrate 30.
It becomes the width direction.

【００１０】上記桟３２は、その長手方向中間部におい
ては、外力に対してあたかも弦のように容易に変位する
ことができる。したがって、なんらの手当ても行わない
と、上記のようなセカンドボンディングにおいてキャピ
ラリ４０を超音波振動させても、桟３２が超音波振動に
追随して振動してしまい、ワイヤ１９と第２導体パター
ン１５との間に適正な相対動ないしこれに起因する摩擦
熱を発生させることができない。このことは、セカンド
ボンディングの強度に不安を残すことになり、とりわ
け、上記桟の長手方向各部位において、桟の振動容易性
が異なることから、桟３２の長手方向のどの部位から得
られたチップＬＥＤであるかによって、ボンディングワ
イヤ１９の結合強度がまちまちとなる問題が生じる。The crosspiece 32 can be easily displaced at its intermediate portion in the longitudinal direction as if it were a string with respect to an external force. Therefore, without any treatment, even if the capillary 40 is ultrasonically vibrated in the second bonding as described above, the crosspiece 32 vibrates following the ultrasonic vibration, and the wire 19 and the second conductor pattern 15 are vibrated. It is not possible to generate proper relative motion between them and frictional heat resulting therefrom. This leaves anxiety about the strength of the second bonding, and in particular, since the easiness of vibration of the crosspiece is different in each part in the longitudinal direction of the crosspiece, the chip obtained from any part in the longitudinal direction of the crosspiece 32. There is a problem that the bonding strength of the bonding wire 19 varies depending on whether it is an LED.

【００１１】このような問題を解決するための方法とし
て、セカンドボンディングをするに際し、適当な押圧部
材で材料基板を押圧し、超音波振動に追随する桟３２の
振動を抑制することが考えられるが、既にチップボンデ
ィングがなされた材料基板ないし各桟をその上面から適
正に押圧することは非常に困難である。As a method for solving such a problem, it is conceivable to press the material substrate with an appropriate pressing member during the second bonding to suppress the vibration of the crosspiece 32 following the ultrasonic vibration. It is very difficult to properly press the material substrate or each crosspiece already chip-bonded from the upper surface thereof.

【００１２】本願発明は、このような事情のもとで考え
出されたものであって、簡単な構成により、チップ型Ｌ
ＥＤまたはＬＥＤアレイにおけるにおけるＬＥＤチップ
と基板上の導体パターンとの間をつなぐボンディングワ
イヤの結合強度を高めるとともに、ボンディングワイヤ
の結合強度のばらつきを無くすことをその課題としてい
る。The present invention has been devised under such circumstances, and has a simple structure with a chip type L
An object of the invention is to increase the bonding strength of a bonding wire that connects an LED chip in an ED or an LED array and a conductor pattern on a substrate and eliminate variations in the bonding strength of the bonding wire.

【００１３】[0013]

【発明の開示】本願発明の第１の側面によれば、新たな
構造をもつチップ型ＬＥＤが提供され、このチップ型Ｌ
ＥＤは、両端に端子部が形成されたチップ基板と、各端
子部にそれぞれ導通するように上記チップ基板上に形成
された第１および第２の導体パターンと、一方の導体パ
ターン上にボンディングされたＬＥＤチップと、このＬ
ＥＤチップの上面パッドと他方の導体パターン間をつな
ぐワイヤと、上記ＬＥＤチップないしワイヤを覆う透明
または半透明のモールド樹脂とを備えるチップ型ＬＥＤ
において、上記ワイヤは、上記チップ基板における両端
子部間をつなぐ軸線に対してほぼ直交する方向に延ばさ
れていることに特徴づけられる。DISCLOSURE OF THE INVENTION According to the first aspect of the present invention, a chip type LED having a new structure is provided.
The ED is bonded to a chip substrate having terminal portions formed on both ends thereof, first and second conductor patterns formed on the chip substrate so as to be electrically connected to the respective terminal portions, and one conductor pattern. LED chip and this L
A chip-type LED including a wire connecting between the upper surface pad of the ED chip and the other conductor pattern, and a transparent or semitransparent molding resin that covers the LED chip or the wire.
In the above, the wire is extended in a direction substantially orthogonal to an axis connecting both terminal portions of the chip substrate.

【００１４】この第１の側面によるチップ型ＬＥＤの好
ましい実施形態においては、上記第２の導体パターンの
一部は、上記ＬＥＤチップに対して上記チップ基板の幅
方向に隣接させられており、かつ、上記ワイヤは、上記
ＬＥＤチップの上面パッドから基板幅方向に延びて上記
第２の導体パターンに接続されている。In a preferred embodiment of the chip type LED according to the first aspect, a part of the second conductor pattern is adjacent to the LED chip in the width direction of the chip substrate, and The wire extends from the upper surface pad of the LED chip in the board width direction and is connected to the second conductor pattern.

【００１５】本願発明の第２の側面によれば、新たな構
造をもつＬＥＤアレイが提供され、このＬＥＤアレイ
は、両側縁にそれぞれ端子部が形成された基板と、各端
子部に導通するようにそれぞれ等間隔に形成された複数
の第１および第２導体パターンと、各第１の導体パター
ン上にボンディングされたＬＥＤチップと、このＬＥＤ
チップの上面パッドと、対応する第２導体パターン間を
つなぐワイヤと、上記各ＬＥＤチップないしワイヤを一
連に覆う半透明のモールド樹脂とを備えるＬＥＤアレイ
において、上記ワイヤは、上記基板の長手方向に延ばさ
れていることに特徴づけられる。According to the second aspect of the present invention, an LED array having a new structure is provided, and the LED array has a substrate having terminal portions formed on both side edges thereof, and is electrically connected to each terminal portion. A plurality of first and second conductor patterns formed at equal intervals, LED chips bonded on the first conductor patterns, and the LED
In an LED array comprising a top pad of a chip, a wire connecting between corresponding second conductor patterns, and a semitransparent molding resin that covers each LED chip or wire in series, the wire is arranged in a longitudinal direction of the substrate. Characterized by being extended.

【００１６】本願発明の第３の側面によれば、チップ型
ＬＥＤまたはＬＥＤアレイの製造方法が提供され、この
方法は、複数の平行なスリットを設けることにより、材
料基板に複数本の桟を設けるとともに、各桟の両側縁に
第１電極および第２電極を形成し、かつ各桟の表面に上
記各第１電極および第２電極からそれぞれ延出する複数
の第１導体パターンおよび複数の第２導体パターンを形
成し、各第１導体パターン上にＬＥＤチップをボンディ
ングし、各ＬＥＤチップの上面パッドと対応する各第２
導体パターンとの間をワイヤボンディングし、各桟の上
面を一連に樹脂モールドし、各桟を一定長さごとに切断
する工程を含むチップ型ＬＥＤまたはＬＥＤアレイの製
造方法において、上記第２導体パターンにおけるワイヤ
ボンディング部を対応する第１導体パターンにおけるチ
ップボンディング部に対して桟の長手方向に隣接して設
け、上記チップボンディング部にボンディングされたＬ
ＥＤチップの上面に一端をボンディングしたワイヤの他
端部を上記第２導体パターンにおけるワイヤボンディン
グ部にボンディングすることに特徴づけられる。According to a third aspect of the present invention, there is provided a method for manufacturing a chip-type LED or LED array, which comprises providing a plurality of parallel slits on a material substrate to provide a plurality of crosspieces. At the same time, first electrodes and second electrodes are formed on both side edges of each crosspiece, and a plurality of first conductor patterns and a plurality of second conductive patterns extending from the first electrodes and the second electrodes are formed on the surface of each crosspiece. A conductor pattern is formed, an LED chip is bonded on each first conductor pattern, and each second chip corresponds to a top pad of each LED chip.
In the method for manufacturing a chip-type LED or LED array, which includes a step of wire-bonding with a conductor pattern, resin-molding the upper surface of each bar in series, and cutting each bar into a certain length, the second conductor pattern The wire bonding portion in the above is provided adjacent to the chip bonding portion in the corresponding first conductor pattern in the longitudinal direction of the crosspiece, and is bonded to the chip bonding portion by L.
It is characterized in that the other end of the wire, one end of which is bonded to the upper surface of the ED chip, is bonded to the wire bonding portion of the second conductor pattern.

【００１７】この第３の側面によるチップＬＥＤまたは
ＬＥＤアレイの製造方法における好まし実施形態におい
ては、上記ワイヤの他端部を上記第２導体パターンにお
けるワイヤボンディング部にボンディングするに際し、
ボンディングツールを上記桟の長手方向に高周波振動さ
せることに特徴づけられる。In a preferred embodiment of the method for manufacturing a chip LED or LED array according to the third aspect, when the other end of the wire is bonded to the wire bonding portion of the second conductor pattern,
The bonding tool is characterized by high-frequency vibration in the longitudinal direction of the crosspiece.

【００１８】本願発明は要するに、スリットを設けるこ
とによって複数の桟が形成された材料基板を用いてチッ
プ型ＬＥＤまたはＬＥＤアレイを製造する過程におい
て、桟における各単位領域における第１導体パターン上
にボンディングされたＬＥＤチップと、第２導体パター
ンとの間を結線するボンディングワイヤの方向を、桟の
長手方向に設定したものである。ワイヤボンディングに
おいて前述したような超音波接合を併用する場合、超音
波振動の方向は、ワイヤの延びる方向、すなわち桟の長
手方向となるが、各桟の長手方向外力に対する剛性は、
幅方向外力に対する剛性に対して比較にならないほど高
い。したがって、超音波振動による接合強度の向上が効
果的になされて、しかも、桟の長手方向各部位において
同様にかかる効果を得ることができる。In short, the present invention is, in the process of manufacturing a chip-type LED or LED array using a material substrate in which a plurality of bars are formed by providing slits, is bonded on the first conductor pattern in each unit area of the bars. The direction of the bonding wire that connects the formed LED chip and the second conductor pattern is set to the longitudinal direction of the crosspiece. When the ultrasonic bonding as described above is also used in wire bonding, the direction of ultrasonic vibration is the direction in which the wire extends, that is, the longitudinal direction of the bar, but the rigidity of each bar against external force in the longitudinal direction is:
It is incomparably higher than the rigidity against the external force in the width direction. Therefore, the bonding strength can be effectively improved by ultrasonic vibration, and the same effect can be obtained at each part in the longitudinal direction of the crosspiece.

【００１９】その結果、ＬＥＤチップと第２導体パター
ンとの間をつなぐボンディングワイヤの接合強度が向上
するとともに、接合強度のばらつきが抑制される。As a result, the bonding strength of the bonding wire connecting between the LED chip and the second conductor pattern is improved and the fluctuation of the bonding strength is suppressed.

【００２０】また、超音波接合を併用せず、単にキャピ
ラリによる熱圧着によってファーストボンディングおよ
びセカンドボンディングを行う場合においても、キャピ
ラリの移動方向が上記材料基板における桟の長手方向と
なるので、特にキャピラリを第２導体パターンに圧着さ
せるセカンドボンディングにおいて、桟を不当に変形さ
せるといったことなく、効果的な熱圧着を達成し、ワイ
ヤのボンディング強度を高めることができる。Even when the first bonding and the second bonding are simply performed by thermocompression bonding using a capillary without using ultrasonic bonding together, the moving direction of the capillary is the longitudinal direction of the crosspiece in the material substrate. In the second bonding in which the second conductor pattern is pressure-bonded, it is possible to achieve effective thermocompression bonding and increase the wire bonding strength without unduly deforming the crosspiece.

【００２１】本願発明のその他の特徴および利点は、図
面を参照して以下に行う詳細な説明から、より明らかと
なろう。Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the drawings.

【００２２】[0022]

【好ましい実施の形態】以下、本願発明の好ましい実施
形態を、図１ないし図８を参照しつつ、具体的に説明す
る。なお、これらの図において、図９ないし図１５と同
一または同等の部材または部分には、同一の符号を付し
てある。BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be specifically described below with reference to FIGS. In these figures, the same or equivalent members or parts as those in FIGS. 9 to 15 are designated by the same reference numerals.

【００２３】図１および図２は、本願発明にかかるチッ
プ型ＬＥＤ１の構成を示している。1 and 2 show the structure of a chip type LED 1 according to the present invention.

【００２４】これらの図に示すように、このチップ型Ｌ
ＥＤ１は、平面視矩形状に形成されたチップ基板１１上
にＬＥＤチップ１７をボンディングし、所定のワイヤボ
ンディングを行った上で、上記ＬＥＤチップ１７ないし
ボンディングワイヤ１９を透明または半透明の透光性樹
脂２０でモールドした形態をもっている。As shown in these figures, this chip type L
In the ED1, the LED chip 17 is bonded on the chip substrate 11 formed in a rectangular shape in a plan view, and after performing predetermined wire bonding, the LED chip 17 or the bonding wire 19 is transparent or translucent. It has a form molded with resin 20.

【００２５】チップ基板１１の長手方向両端部には、第
１電極被膜１２および第２電極被膜１３が形成されてお
り、各電極被膜１２，１３は、それぞれ、側面二次電極
被膜１２ａ，１３ａを介して、裏面側の三次電極被膜１
２ｂ，１３ｂに導通させられている。A first electrode coating 12 and a second electrode coating 13 are formed on both ends of the chip substrate 11 in the longitudinal direction. The electrode coatings 12 and 13 have side surface secondary electrode coatings 12a and 13a, respectively. Through, the third electrode film 1 on the back side
It is electrically connected to 2b and 13b.

【００２６】第１電極被膜１２に導通するようにして、
第１導体パターン１４が、第２電極被膜１３と導通する
ようにして、第２導体パターン１５が、それぞれチップ
基板１１の表面上を中央に向かうようにして延出形成さ
れている。ただし、本願発明においては、従来例とは異
なり、第１導体パターン１４に設定されるチップボンデ
ィング部１６と、第２導体パターン１５に設定されるワ
イヤボンディング部１８とは、チップ基板１１の幅方向
に隣接させられている。したがって、上記チップボンデ
ィング部１６にボンディングされるＬＥＤチップ１７の
上面パッドと上記第２導体パターン１５上に設定される
ワイヤボンディング部１８との間を結線されるボンディ
ングワイヤ１９は、平面視において、基板幅方向、すな
わち、上記両電極被膜１２，１３間をつなぐ軸線Ｘに対
してほぼ直交する方向に延びることになる。Conducting electrical connection to the first electrode coating 12,
The first conductor pattern 14 is formed so as to be electrically connected to the second electrode coating film 13, and the second conductor patterns 15 are formed so as to extend toward the center on the surface of the chip substrate 11. However, in the present invention, unlike the conventional example, the chip bonding portion 16 set in the first conductor pattern 14 and the wire bonding portion 18 set in the second conductor pattern 15 are arranged in the width direction of the chip substrate 11. Is adjacent to. Therefore, the bonding wire 19 connected between the upper surface pad of the LED chip 17 bonded to the chip bonding portion 16 and the wire bonding portion 18 set on the second conductor pattern 15 is the substrate in plan view. It extends in the width direction, that is, in the direction substantially orthogonal to the axis X connecting the two electrode coatings 12 and 13.

【００２７】上記のチップ型ＬＥＤは、次のようにして
製造することができる。図１０は、上記チップ型ＬＥＤ
１を製造するために用いられる材料基板３０の略示平面
図、図３は、その拡大平面図である。The chip type LED described above can be manufactured as follows. FIG. 10 shows the above chip type LED.
1 is a schematic plan view of a material substrate 30 used for manufacturing 1., and FIG. 3 is an enlarged plan view thereof.

【００２８】図１０に示されるように材料基板３０に
は、複数の平行なスリット３１を形成することにより、
複数の桟３２が形成されている。各桟３２の上面両側縁
には、図３に詳示するように、第１電極被膜１２と第２
電極被膜１３とが互いに対向するように形成されてい
る。そして、第１電極被膜１２から延出する複数の第１
導体パターン１４と第２電極被膜１３から延出する複数
の第２導体パターン１５とがそれぞれ桟３の長手方向に
ついて等間隔に形成されている。このような電極被膜な
いし導体パターンは、たとえば、上記スリット３１を形
成する以前の基板全面に導体被膜を印刷または蒸着等に
よって形成し、不要部分をエッチングによって除去する
ことにより形成することができる。By forming a plurality of parallel slits 31 in the material substrate 30 as shown in FIG.
A plurality of crosspieces 32 are formed. As shown in detail in FIG. 3, the first electrode coating 12 and the second electrode coating 12 are formed on both side edges of the upper surface of each crosspiece 32.
The electrode coating 13 is formed so as to face each other. Then, a plurality of first electrodes extending from the first electrode coating 12 are provided.
The conductor pattern 14 and the plurality of second conductor patterns 15 extending from the second electrode coating film 13 are formed at equal intervals in the longitudinal direction of the crosspiece 3. Such an electrode coating or conductor pattern can be formed, for example, by forming a conductor coating on the entire surface of the substrate before forming the slits 31 by printing or vapor deposition and removing unnecessary portions by etching.

【００２９】上記スリット３１の内壁には、第１電極被
膜１２および第２電極被膜１３とそれぞれ導通する側面
二次電極１２ａ，１３ａが形成されるとともに各桟３２
の裏面には、側面二次電極１２ａ，１３ａと導通する三
次電極１２ｂ，１３ｂが形成されている。この三次電極
１２ｂ，１３ｂの形成もまた、上記スリット３１を形成
する以前の基板の裏面全面に導体被膜を形成するととも
に、不要部分をエッチングによって除去することにより
形成することができる。On the inner wall of the slit 31, side surface secondary electrodes 12a and 13a which are respectively connected to the first electrode coating film 12 and the second electrode coating film 13 are formed and each crosspiece 32 is formed.
On the back surface of, the tertiary electrodes 12b and 13b are formed so as to be electrically connected to the side surface secondary electrodes 12a and 13a. The tertiary electrodes 12b and 13b can also be formed by forming a conductor film on the entire back surface of the substrate before forming the slits 31 and removing unnecessary portions by etching.

【００３０】前述したことから判るように、上記スリッ
ト３１を設けた材料基板３０を用いる理由は、側面二次
電極１２ａ，１３ａを適正に形成するためである。As can be seen from the above, the reason for using the material substrate 30 provided with the slit 31 is to properly form the side surface secondary electrodes 12a and 13a.

【００３１】さて、本願発明においては、上記のような
材料基板を用い、まず、各桟３２上に並ぶ各第１導体パ
ターン１４に設定されたチップボンディング部１６に、
ＬＥＤチップ１７をボンディングする。そうして、各Ｌ
ＥＤチップ１７の上面パッドと対応する第２導体パター
ン１５上に設定されたワイヤボンディング部１８との間
を、ワイヤボンディングにより結線する。In the present invention, the material substrate as described above is used, and first, the chip bonding portions 16 set on the respective first conductor patterns 14 arranged on the crosspieces 32 are
The LED chip 17 is bonded. And each L
The upper surface pad of the ED chip 17 and the wire bonding portion 18 set on the corresponding second conductor pattern 15 are connected by wire bonding.

【００３２】前述したことから明らかなように、本願発
明においては、上記チップボンディング部１６とワイヤ
ボンディング部１８とは、材料基板３０における各桟３
２の長手方向に隣接して設けられている。したがって、
上記のワイヤ１９の延びる方向もまた、各桟３２の長手
方向となる。As is clear from the above description, in the present invention, the chip bonding portion 16 and the wire bonding portion 18 are the bars 3 of the material substrate 30.
2 are provided adjacent to each other in the longitudinal direction. Therefore,
The extending direction of the wire 19 is also the longitudinal direction of each crosspiece 32.

【００３３】上記ワイヤボンディングは、キャピラリ４
０を用いて金線ワイヤ１９をまずＬＥＤチップ１７の上
面パッドにファーストボンディングし、このワイヤ１９
の他端部を第２導体パターン１５上にセカンドボンディ
ングすることによって行われる。The wire bonding is performed by the capillary 4
First, the gold wire 19 is first bonded to the upper surface pad of the LED chip 17 by using 0.
Second bonding is performed on the other end portion of the second conductive pattern 15 on the second conductive pattern 15.

【００３４】ファーストボンディングは、図５に示すよ
うに、キャピラリ４０から導出される金線ワイヤ１９に
熱をかけてボール１９ａを形成し、次いで図６に示すよ
うにキャピラリ４０をＬＥＤチップ１７の上面パッドに
圧しつけることにより行われる。このとき、基板ないし
ＬＥＤチップは所定の温度まで加熱させられており、ま
た、キャピラリ４０を超音波振動させる。キャピラリ４
０には、超音波ホーン４１が接続されており、この超音
波振動の方向は、ワイヤの延びる方向、換言すると、キ
ャピラリ４０をセカンドボンディング地点まで移動させ
る方向と一致させるのが通常である。In the first bonding, as shown in FIG. 5, heat is applied to the gold wire 19 led out from the capillary 40 to form a ball 19a, and then the capillary 40 is attached to the upper surface of the LED chip 17 as shown in FIG. It is performed by pressing on the pad. At this time, the substrate or LED chip is heated to a predetermined temperature, and the capillary 40 is ultrasonically vibrated. Capillary 4
An ultrasonic horn 41 is connected to 0, and the direction of this ultrasonic vibration is usually the same as the direction in which the wire extends, that is, the direction in which the capillary 40 is moved to the second bonding point.

【００３５】本願発明の場合、ワイヤ１９は、桟３２の
長手方向に延ばされるので、上記の超音波振動の方向も
また、桟３２の長手方向と一致した方向となる。In the case of the present invention, since the wire 19 is extended in the longitudinal direction of the crosspiece 32, the direction of the above-mentioned ultrasonic vibration also coincides with the longitudinal direction of the crosspiece 32.

【００３６】こうしてファーストボンディングが行われ
ると、次に、図７に示すように、キャピラリ４０が、第
２導体パターン１５まで移動し、ワイヤ１９の端部を第
２導体パターン１５との間に挟みつけるようにして、こ
のキャピラリ４０が導体パターン１５に押圧させられる
とともに、前述と同様、このキャピラリ４０は超音波振
動させられる。この場合も、キャピラリ４０の超音波振
動の方向は、桟３２の長手方向と一致した方向となる。When the first bonding is performed in this way, the capillary 40 then moves to the second conductor pattern 15 and the end portion of the wire 19 is sandwiched between the second conductor pattern 15 and the second conductor pattern 15, as shown in FIG. As it is attached, the capillary 40 is pressed against the conductor pattern 15, and the capillary 40 is ultrasonically vibrated as described above. Also in this case, the direction of ultrasonic vibration of the capillary 40 coincides with the longitudinal direction of the crosspiece 32.

【００３７】桟３２は、その幅方向の外力に対する剛性
はきわめて低いが、長手方向の外力に対する剛性は高
い。従来においては、ワイヤ１９の方向が上記桟３２の
幅方向であったため、ワイヤボンディング部においてキ
ャピラリによって与えられる超音波振動に追随して桟３
２が振動してしまい、超音波接合の利点を十分に享受す
ることができなかったが、本願発明においては、キャピ
ラリ４０によって与えられる超音波振動の方向が桟の長
手方向であるため、この超音波振動に追随して桟３２が
長手方向に振動するといったことがない。したがって、
超音波接合による利点を十分に享受することができ、し
かも、この超音波振動によるワイヤ接合作用は、桟３２
の長手方向各部位において一定となる。The crosspiece 32 has extremely low rigidity against external force in the width direction, but has high rigidity against external force in the longitudinal direction. In the past, since the direction of the wire 19 was the width direction of the crosspiece 32, the crosspiece 3 follows the ultrasonic vibration given by the capillary in the wire bonding portion.
However, in the present invention, the direction of ultrasonic vibration provided by the capillary 40 is the longitudinal direction of the crosspiece. The crosspiece 32 does not vibrate in the longitudinal direction following the sound wave vibration. Therefore,
The advantages of ultrasonic bonding can be fully enjoyed, and the wire bonding action due to this ultrasonic vibration causes
Is constant in each part in the longitudinal direction.

【００３８】その結果、ワイヤボンディングの強度が、
従来例に比較して高まるとともに、かかるワイヤボンデ
ィングの品質のばらつきがなくなる。このことは、本願
発明方法によって製造されるチップ型ＬＥＤの電気的安
定性にかかる品質が著しく高まること意味する。As a result, the strength of wire bonding is
As compared with the conventional example, the quality of wire bonding will be uniform and will be eliminated. This means that the electrical stability of the chip type LED manufactured by the method of the present invention is significantly improved.

【００３９】上記のようにして、材料基板３０の各桟３
２に設定された各単位領域の全てに対するチップボンデ
ィングおよびワイヤボンディングが終了すると、図８に
示すように、各桟３２の上面は、透明エポキシ樹脂等に
よるモールド樹脂２０によって一連に覆われる。As described above, each bar 3 of the material substrate 30 is
When the chip bonding and the wire bonding for all the unit areas set to 2 are completed, the upper surfaces of the crosspieces 32 are continuously covered with the mold resin 20 such as a transparent epoxy resin as shown in FIG.

【００４０】そうして、各桟３２を図３に破線で示す部
位において分断して、図１および図２に示したような単
位チップ型ＬＥＤ１が得られる。また、上記破線で示す
部位のうち、複数番目の部位ごとに分断すると、複数の
ＬＥＤチップを内蔵するＬＥＤアレイが得られる。In this way, each crosspiece 32 is divided at the portion shown by the broken line in FIG. 3, and the unit chip type LED 1 as shown in FIGS. 1 and 2 is obtained. Further, among the parts indicated by the broken line, by dividing into a plurality of parts, an LED array having a plurality of LED chips built therein is obtained.

【００４１】もちろん、本願発明の範囲は上述した各実
施形態に限定されるものではない。材料基板の材質およ
び各電極被膜ないし導体パターンの形成方法は、前述し
た方法に限定されない。本願発明は、要するに、材料基
板に形成される各桟の長手方向にワイヤボンディングを
行うというものであり、かかる方法を採用する限り、細
部の変更にかかわらず、全て本願発明の範囲に含まれ
る。上記の方法によって製造されたチップ型ＬＥＤまた
はＬＥＤアレイについても同様である。Of course, the scope of the present invention is not limited to the above embodiments. The material of the material substrate and the method of forming each electrode coating film or conductor pattern are not limited to the above-described methods. In short, the invention of the present application is to perform wire bonding in the longitudinal direction of each bar formed on the material substrate, and as long as such a method is adopted, it is all within the scope of the invention of the present application regardless of changes in details. The same applies to the chip type LED or LED array manufactured by the above method.

【図面の簡単な説明】[Brief description of drawings]

【図１】本願発明のチップ型ＬＥＤの一実施形態を示す
斜視図である。FIG. 1 is a perspective view showing an embodiment of a chip-type LED of the present invention.

【図２】図１に示されるチップ型ＬＥＤの平面図であ
る。FIG. 2 is a plan view of the chip type LED shown in FIG.

【図３】(a) は図１に示されるチップ型ＬＥＤまたはこ
のチップ型ＬＥＤの形態を複数一体につなげた形態をも
つＬＥＤアレイを製造するのに用いられる材料基板の部
分拡大平面図、(b) は図３(a) のIII−III線に沿う断面
図である。FIG. 3A is a partially enlarged plan view of a material substrate used for manufacturing an LED array having a chip-type LED shown in FIG. 1 or a form in which a plurality of the chip-type LED's are integrally connected; 3B is a sectional view taken along the line III-III in FIG.

【図４】図３（a)のIV−IV線に沿う断面図である。FIG. 4 is a sectional view taken along line IV-IV of FIG.

【図５】本願発明のチップ型ＬＥＤの製造方法における
ワイヤボンディングの説明図である。FIG. 5 is an explanatory diagram of wire bonding in the method of manufacturing the chip LED of the present invention.

【図６】本願発明のチップ型ＬＥＤの製造方法における
ワイヤボンディングの説明図である。FIG. 6 is an explanatory view of wire bonding in the method of manufacturing the chip LED of the present invention.

【図７】本願発明のチップ型ＬＥＤの製造方法における
ワイヤボンディングの説明図である。FIG. 7 is an explanatory diagram of wire bonding in the method of manufacturing the chip-type LED of the present invention.

【図８】本願発明のチップ型ＬＥＤまたはＬＥＤアレイ
の製造方法において、材料基板の各桟を覆うように樹脂
モールドを施した状態の説明図である。FIG. 8 is an explanatory diagram showing a state in which a resin mold is applied so as to cover each crosspiece of the material substrate in the method of manufacturing a chip LED or LED array of the present invention.

【図９】従来のチップ型ＬＥＤの一例を示す斜視図であ
る。FIG. 9 is a perspective view showing an example of a conventional chip-type LED.

【図１０】この種のチップ型ＬＥＤまたはＬＥＤアレイ
の製造に用いられる材料基板の概略構成を示す部分平面
図である。FIG. 10 is a partial plan view showing a schematic configuration of a material substrate used for manufacturing this type of chip-type LED or LED array.

【図１１】(a) はこの種のチップ型ＬＥＤまたはＬＥＤ
アレイの製造に用いられる材料基板の従来構成を示す部
分拡大平面図、(b) は図１１(a) のXI−XI線に沿う断面
図である。FIG. 11 (a) is a chip-type LED or LED of this type
11B is a partially enlarged plan view showing a conventional structure of a material substrate used for manufacturing an array, and FIG. 11B is a sectional view taken along line XI-XI of FIG. 11A.

【図１２】従来のチップ型ＬＥＤまたはＬＥＤアレイの
製造方法におけるワイヤボンディングの説明図である。FIG. 12 is an explanatory diagram of wire bonding in a conventional method for manufacturing a chip-type LED or LED array.

【図１３】従来のチップ型ＬＥＤまたはＬＥＤアレイの
製造方法におけるワイヤボンディングの説明図である。FIG. 13 is an explanatory diagram of wire bonding in a conventional method for manufacturing a chip-type LED or LED array.

【図１４】従来のチップ型ＬＥＤまたはＬＥＤアレイの
製造方法におけるワイヤボンディングの説明図である。FIG. 14 is an explanatory diagram of wire bonding in a conventional method for manufacturing a chip-type LED or LED array.

【図１５】従来のチップ型ＬＥＤまたはＬＥＤアレイの
製造方法において、材料基板の各桟を覆うように樹脂モ
ールドを施した状態の説明図である。FIG. 15 is an explanatory view showing a state where a resin mold is applied so as to cover each crosspiece of the material substrate in the conventional method for manufacturing a chip-type LED or LED array.

【符号の説明】[Explanation of symbols]

１ チップ型ＬＥＤ １１ チップ基板 １２ 第１電極被膜 １３ 第２電極被膜 １４ 第１導体パターン １５ 第２導体パターン １６ チップボンディング部 １７ ＬＥＤチップ １８ ワイヤボンディング部 １９ ボンディングワイヤ ２０ モールド樹脂 ３０ 材料基板 ３１ スリット ３２ 桟 ４０ キャピラリ ４１ 超音波ホーン DESCRIPTION OF SYMBOLS 1 Chip type LED 11 Chip substrate 12 1st electrode film 13 2nd electrode film 14 1st conductor pattern 15 2nd conductor pattern 16 Chip bonding part 17 LED chip 18 Wire bonding part 19 Bonding wire 20 Mold resin 30 Material substrate 31 Slit 32 Cross 40 Capillary 41 Ultrasonic horn

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 両端に端子部が形成されたチップ基板
と、各端子部にそれぞれ導通するように上記チップ基板
上に形成された第１および第２の導体パターンと、一方
の導体パターン上にボンディングされたＬＥＤチップ
と、このＬＥＤチップの上面パッドと他方の導体パター
ン間をつなぐワイヤと、上記ＬＥＤチップないしワイヤ
を覆う透明または半透明のモールド樹脂とを備えるチッ
プ型ＬＥＤにおいて、 上記ワイヤは、上記チップ基板における両端子部間をつ
なぐ軸線に対してほぼ直交する方向に延ばされているこ
とを特徴とする、チップ型ＬＥＤ。1. A chip substrate having terminal portions formed on both ends, first and second conductor patterns formed on the chip substrate so as to be electrically connected to the respective terminal portions, and one of the conductor patterns. In a chip-type LED comprising a bonded LED chip, a wire connecting between the upper surface pad of the LED chip and the other conductor pattern, and a transparent or translucent mold resin covering the LED chip or the wire, the wire is A chip-type LED, wherein the chip-type LED is extended in a direction substantially orthogonal to an axis connecting the terminal portions of the chip substrate. 【請求項２】 両端に端子部が形成されたチップ基板
と、各端子部にそれぞれ導通するように上記チップ基板
上に形成された第１および第２の導体パターンと、第１
の導体パターン上にボンディングされたＬＥＤチップ
と、このＬＥＤチップの上面パッドと第２の導体パター
ン間をつなぐワイヤと、上記ＬＥＤチップないしワイヤ
を覆う透明または半透明のモールド樹脂とを備えるチッ
プ型ＬＥＤにおいて、 上記第２の導体パターンの一部は、上記ＬＥＤチップに
対して上記チップ基板の幅方向に隣接させられており、
かつ、上記ワイヤは、上記ＬＥＤチップの上面パッドか
ら基板幅方向に延びて上記第２の導体パターンに接続さ
れていることを特徴とする、チップ型ＬＥＤ。2. A chip substrate having terminal portions formed on both ends, first and second conductor patterns formed on the chip substrate so as to be electrically connected to the respective terminal portions, and a first
A chip-type LED comprising: an LED chip bonded on the conductor pattern; a wire connecting between an upper surface pad of the LED chip and a second conductor pattern; and a transparent or semitransparent mold resin covering the LED chip or the wire. In, part of the second conductor pattern is adjacent to the LED chip in the width direction of the chip substrate,
Further, the chip type LED is characterized in that the wire extends from a top surface pad of the LED chip in a board width direction and is connected to the second conductor pattern. 【請求項３】 このＬＥＤアレイは、両側縁にそれぞれ
端子部が形成された基板と、各端子部に導通するように
それぞれ等間隔に形成された複数の第１および第２導体
パターンと、各第１の導体パターン上にボンディングさ
れたＬＥＤチップと、このＬＥＤチップの上面パッド
と、対応する第２導体パターン間をつなぐワイヤと、上
記各ＬＥＤチップないしワイヤを一連に覆う半透明のモ
ールド樹脂とを備えるＬＥＤアレイにおいて、上記ワイ
ヤは、上記基板の長手方向に延ばされていることを特徴
とする、ＬＥＤアレイ。3. This LED array includes a substrate having terminal portions formed on both side edges thereof, a plurality of first and second conductor patterns formed at equal intervals so as to be electrically connected to each terminal portion, and An LED chip bonded on the first conductor pattern, a pad on the upper surface of the LED chip, a wire connecting between the corresponding second conductor patterns, and a semitransparent molding resin that covers the LED chips or the wires in series. An LED array comprising: the wire, the wire extending in a longitudinal direction of the substrate. 【請求項４】 複数の平行なスリットを設けることによ
り、材料基板に複数本の桟を設けるとともに、各桟の両
側縁に第１電極および第２電極を形成し、かつ各桟の表
面に上記各第１電極および第２電極からそれぞれ延出す
る複数の第１導体パターンおよび複数の第２導体パター
ンを形成し、各第１導体パターン上にＬＥＤチップをボ
ンディングし、各ＬＥＤチップの上面パッドと対応する
各第２導体パターンとの間をワイヤボンディングし、各
桟の上面を一連に樹脂モールドし、各桟を一定長さごと
に切断する工程を含むチップ型ＬＥＤまたはＬＥＤアレ
イの製造方法において、 上記第２導体パターンにおけるワイヤボンディング部を
対応する第１導体パターンにおけるチップボンディング
部に対して桟の長手方向に隣接して設け、上記チップボ
ンディング部にボンディングされたＬＥＤチップの上面
に一端をボンディングしたワイヤの他端部を上記第２導
体パターンにおけるワイヤボンディング部にボンディン
グすることを特徴とする、チップ型ＬＥＤまたはＬＥＤ
アレイの製造方法。4. A plurality of bars are provided on the material substrate by providing a plurality of parallel slits, a first electrode and a second electrode are formed on both side edges of each bar, and the above-mentioned is formed on the surface of each bar. A plurality of first conductor patterns and a plurality of second conductor patterns extending from the first electrodes and the second electrodes, respectively, are formed, an LED chip is bonded onto each of the first conductor patterns, and an upper surface pad of each LED chip is formed. In a method of manufacturing a chip-type LED or LED array, including a step of wire-bonding between corresponding second conductor patterns, resin-molding the upper surface of each bar in series, and cutting each bar at a constant length, The wire bonding portion of the second conductor pattern is provided adjacent to the corresponding chip bonding portion of the first conductor pattern in the longitudinal direction of the crosspiece, and The other end portion of the wire bonded at one end to flop bonding portion on the upper surface of the bonded LED chips, characterized in that bonding the wire bonding portion of the second conductor pattern, a chip-type LED or LED
Array manufacturing method. 【請求項５】 請求項４に記載した方法において、上記
ワイヤの他端部を上記第２導体パターンにおけるワイヤ
ボンディング部にボンディングするに際し、ボンディン
グツールを上記桟の長手方向に高周波振動させることを
特徴とする、チップ型ＬＥＤまたはＬＥＤアレイの製造
方法。5. The method according to claim 4, wherein the bonding tool is vibrated at a high frequency in the longitudinal direction of the crosspiece when the other end of the wire is bonded to the wire bonding portion of the second conductor pattern. And a method for manufacturing a chip-type LED or LED array.
JP25310895A 1995-09-29 1995-09-29 Chip type led, led array and manufacture thereof Pending JPH0997929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25310895A JPH0997929A (en) 1995-09-29 1995-09-29 Chip type led, led array and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25310895A JPH0997929A (en) 1995-09-29 1995-09-29 Chip type led, led array and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0997929A true JPH0997929A (en) 1997-04-08

Family

ID=17246615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25310895A Pending JPH0997929A (en) 1995-09-29 1995-09-29 Chip type led, led array and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0997929A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205515A (en) * 2008-05-29 2008-09-04 Sanyo Electric Co Ltd Manufacturing method of semiconductor device
JP2008205516A (en) * 2008-05-29 2008-09-04 Sanyo Electric Co Ltd Semiconductor device
JP2011082310A (en) * 2009-10-06 2011-04-21 Citizen Electronics Co Ltd Light emitting device
JP2012124249A (en) * 2010-12-07 2012-06-28 Toshiba Corp Led package and manufacturing method thereof
JP2013125869A (en) * 2011-12-14 2013-06-24 Ibiden Co Ltd Electronic component mounting substrate, light-emitting device and display device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205515A (en) * 2008-05-29 2008-09-04 Sanyo Electric Co Ltd Manufacturing method of semiconductor device
JP2008205516A (en) * 2008-05-29 2008-09-04 Sanyo Electric Co Ltd Semiconductor device
JP2011082310A (en) * 2009-10-06 2011-04-21 Citizen Electronics Co Ltd Light emitting device
JP2012124249A (en) * 2010-12-07 2012-06-28 Toshiba Corp Led package and manufacturing method thereof
JP2013125869A (en) * 2011-12-14 2013-06-24 Ibiden Co Ltd Electronic component mounting substrate, light-emitting device and display device

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