JPH0992748A - Package for semiconductor element - Google Patents

Package for semiconductor element

Info

Publication number
JPH0992748A
JPH0992748A JP7242673A JP24267395A JPH0992748A JP H0992748 A JPH0992748 A JP H0992748A JP 7242673 A JP7242673 A JP 7242673A JP 24267395 A JP24267395 A JP 24267395A JP H0992748 A JPH0992748 A JP H0992748A
Authority
JP
Japan
Prior art keywords
ceramic substrate
semiconductor element
lid
lid body
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7242673A
Other languages
Japanese (ja)
Inventor
Toshiyuki Nagase
敏之 長瀬
Yoshio Kuromitsu
祥郎 黒光
Yoshio Kanda
義雄 神田
Akifumi Hatsuka
昌文 初鹿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP7242673A priority Critical patent/JPH0992748A/en
Publication of JPH0992748A publication Critical patent/JPH0992748A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a package in which a semiconductor element can be set, while being secured firmly, in a cavity without applying undue force, the number of machining steps of the cover is decreased, and stress due to repeated heating/ cooling the semiconductor element is relaxed at each joint of the ceramic board, the cover, and the semiconductor element. SOLUTION: A semiconductor element 14 is secured through a first solder 11 onto the upper surface of a ceramic board 16 and a cover 17 having a cavity 18 for containing the semiconductor element 14 is bonded to the upper surface of a ceramic board 16 at the circumferential fringe thereof so that the semiconductor element 14 is contained in the cavity. The cover 17 comprises a cover body 19 covering the upper surface of the semiconductor element 14, and a frame member 26 independent from the cover body 19 with the upper surface being bonded through a buffer material 24 to the lower surface of the cover body 19 at the circumferential fringe thereof. The cover body 19, the frame member 26 and the ceramic board 16 have coefficients of thermal expansion α1 , α2 , α3 satisfying a relationship α1 <=α2 <=α3 .

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子を収容す
るためのパッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for housing a semiconductor device.

【0002】[0002]

【従来の技術】従来、この種の半導体素子用パッケージ
として、セラミック基板と蓋からなり、内部に半導体素
子を収容するための空所を有し、セラミック基板がガラ
スセラミック焼結体で形成され、蓋が窒化アルミニウム
焼結体で形成された半導体素子収納用パッケージが開示
されている(特開平6−244295)。このパッケー
ジではセラミック基板が50.0〜90.0体積%のコ
ージェライト及びムライトの少なくとも1種からなる結
晶と、10.0〜50.0体積%のアルミナ、スピネ
ル、アノーサイト及びフォルステライトの少なくとも1
種からなる結晶とが含有される。蓋はAlN粉末を主成
分とする原料粉末をプレス成形により成形体を形成した
後、この成形体を約1800℃の温度で焼成することに
より、伏せ椀状に形成される。また蓋の側壁下面はセラ
ミック基板の上面周縁にガラスや樹脂等の封止材を介し
て接着され、半導体素子の上面はこの半導体素子の発し
た熱を効率良く大気中に放散させるために蓋の内面に接
着される。
2. Description of the Related Art Conventionally, as a semiconductor element package of this type, a ceramic substrate and a lid have a space for accommodating semiconductor elements therein, and the ceramic substrate is formed of a glass ceramic sintered body. There is disclosed a package for accommodating a semiconductor element in which a lid is made of an aluminum nitride sintered body (JP-A-6-244295). In this package, the ceramic substrate contains 50.0 to 90.0% by volume of at least one crystal of cordierite and mullite, and 10.0 to 50.0% by volume of at least alumina, spinel, anorthite and forsterite. 1
And crystals of seeds are included. The lid is formed into a bowl shape by forming a compact by press-molding a raw material powder containing AlN powder as a main component, and then firing the compact at a temperature of about 1800 ° C. Further, the lower surface of the side wall of the lid is adhered to the upper peripheral edge of the ceramic substrate through a sealing material such as glass or resin, and the upper surface of the semiconductor element is covered by the lid in order to efficiently dissipate the heat generated by the semiconductor element into the atmosphere. It is glued to the inner surface.

【0003】このように構成された半導体素子収納用パ
ッケージでは、セラミック基板の熱膨張係数が蓋の熱膨
張係数と半導体素子の構成材料であるシリコンの熱膨張
係数とに近似した値になるので、半導体素子の発熱によ
りセラミック基板、蓋及び半導体素子に熱応力が発生せ
ず、半導体素子を長期間正常にかつ安定して作動させる
ことができるようになっている。
In the semiconductor element housing package thus constructed, the coefficient of thermal expansion of the ceramic substrate is close to the coefficient of thermal expansion of the lid and the coefficient of thermal expansion of silicon which is a constituent material of the semiconductor element. Thermal stress is not generated in the ceramic substrate, the lid, and the semiconductor element due to the heat generated by the semiconductor element, and the semiconductor element can be normally and stably operated for a long period of time.

【0004】[0004]

【発明が解決しようとする課題】しかし、上記従来の半
導体素子収納用パッケージでは、焼結したままの蓋の側
壁の高さにばらつきがあり、この状態で上面に半導体素
子を固定したセラミック基板に蓋を接着すると、半導体
素子に過大な圧縮力が作用したり或いは半導体素子の上
面を蓋の内面に接着できなかったりする不具合があっ
た。この点を解消するために側壁の下面及び蓋の内面を
機械加工して側壁の高さを半導体素子の高さに合わせよ
うとすると、蓋の内面の機械加工が煩わしく加工工数が
大幅に増大する問題点がある。また、上記従来の半導体
素子収納用パッケージでは、セラミック基板の熱膨張係
数が蓋及び半導体素子の熱膨張係数に近似した値になる
とはいっても、完全に一致するわけではないため、セラ
ミック基板、蓋及び半導体素子間の各接着部に、半導体
素子の発熱及び冷却の繰返しによる比較的大きなストレ
スが作用する問題点もあった。
However, in the above-mentioned conventional package for accommodating semiconductor elements, there is variation in the height of the side wall of the as-sintered lid, and in this state, the ceramic substrate having the semiconductor element fixed on the upper surface is When the lid is bonded, there is a problem that an excessive compressive force acts on the semiconductor element or the upper surface of the semiconductor element cannot be bonded to the inner surface of the lid. If the lower surface of the side wall and the inner surface of the lid are machined in order to adjust the height of the side wall to the height of the semiconductor element in order to solve this point, the machining of the inner surface of the lid is troublesome and the number of processing steps is significantly increased. There is a problem. Further, in the conventional package for accommodating semiconductor elements, although the coefficient of thermal expansion of the ceramic substrate is close to the coefficient of thermal expansion of the lid and the semiconductor element, they do not completely match, so the ceramic substrate and the lid are not matched. In addition, there is a problem that a relatively large stress is applied to each bonded portion between the semiconductor elements due to repeated heat generation and cooling of the semiconductor element.

【0005】本発明の目的は、半導体素子に無理な力を
加えずに半導体素子をセラミック基板及び蓋本体に確実
に固定した状態で空所に収容でき、蓋の機械加工工数を
低減することができ、更に半導体素子の発熱及び冷却の
繰返しによるセラミック基板、蓋及び半導体素子間の各
接着部に発生するストレスを緩和することができる半導
体素子用パッケージを提供することにある。本発明の別
の目的は、軽量化を図ることができ、また半導体素子の
温度上昇を低減できる半導体素子用パッケージを提供す
ることにある。
An object of the present invention is to allow the semiconductor element to be securely fixed to the ceramic substrate and the lid main body without being forcedly applied to the semiconductor element, and to accommodate the semiconductor element in the empty space, thereby reducing the man-hour for machining the lid. Another object of the present invention is to provide a semiconductor device package that can alleviate the stress generated in the ceramic substrate, the lid, and the bonding portions between the semiconductor devices due to repeated heat generation and cooling of the semiconductor device. Another object of the present invention is to provide a semiconductor device package that can be made lighter and can reduce the temperature rise of the semiconductor device.

【0006】[0006]

【課題を解決するための手段】請求項1に係る発明は、
図1に示すように上面に半導体素子14が第1はんだ1
1を介して固定されたセラミック基板16と、半導体素
子14を収容可能な空所18を有する蓋17とを備え、
蓋17をセラミック基板16の上面周縁に接着すること
により半導体素子14を収容するように構成された半導
体素子用パッケージの改良である。その特徴ある構成
は、蓋17が半導体素子14の上面を覆う蓋本体19
と、蓋本体19とは別部材により形成され上面が蓋本体
19の下面周縁に緩衝材24を介して接着されかつ半導
体素子14の側面を覆う枠材26とを有し、蓋本体19
と枠材26とセラミック基板16の熱膨張係数をそれぞ
れα1とα2とα3とするときα1≦α2≦α3の関係を満た
すところにある。請求項4に係る発明は、請求項1ない
し3いずれかに係る発明であって、更にセラミック基板
16の上面周縁に第1メタライズ層21が形成され、枠
材26の下面に第2メタライズ層22が形成され、枠材
26が第2メタライズ層22と第3はんだ13と第1メ
タライズ層21とを介してセラミック基板16の上面周
縁に接着されたことを特徴とする半導体素子用セラミッ
クパッケージである。請求項5に係る発明は、請求項1
ないし4いずれかに係る発明であって、更にセラミック
基板16の上面に第1はんだ11を介して半導体素子1
4が固定され、半導体素子14に対向する蓋本体19の
下面に第3メタライズ層23が形成され、半導体素子1
4の上面が蓋本体19の下面に第3はんだ13及び第3
メタライズ層23を介して接着されたことを特徴とする
半導体素子用パッケージである。
The invention according to claim 1 is
As shown in FIG. 1, the semiconductor element 14 has the first solder 1 on the upper surface.
1, a ceramic substrate 16 fixed via 1 and a lid 17 having a cavity 18 capable of accommodating the semiconductor element 14,
This is an improvement of the semiconductor device package configured to accommodate the semiconductor device 14 by adhering the lid 17 to the peripheral edge of the upper surface of the ceramic substrate 16. The characteristic configuration is that the lid 17 covers the upper surface of the semiconductor element 14 and the lid main body 19
And a frame member 26, which is formed as a separate member from the lid main body 19 and whose upper surface is adhered to the lower peripheral edge of the lid main body 19 via the cushioning material 24 and covers the side surface of the semiconductor element 14,
When the thermal expansion coefficients of the frame member 26 and the ceramic substrate 16 are α 1 , α 2 and α 3 , respectively, the relationship of α 1 ≦ α 2 ≦ α 3 is satisfied. The invention according to claim 4 is the invention according to any one of claims 1 to 3, further comprising a first metallization layer 21 formed on a peripheral edge of an upper surface of the ceramic substrate 16 and a second metallization layer 22 on a lower surface of the frame member 26. Is formed, and the frame member 26 is adhered to the peripheral edge of the upper surface of the ceramic substrate 16 via the second metallization layer 22, the third solder 13, and the first metallization layer 21. . The invention according to claim 5 is the invention according to claim 1.
1 to 4, the semiconductor element 1 is further provided on the upper surface of the ceramic substrate 16 via the first solder 11.
4 is fixed and a third metallization layer 23 is formed on the lower surface of the lid body 19 facing the semiconductor element 14.
The upper surface of 4 is on the lower surface of the lid body 19 and the third solder 13 and the third solder 13
The semiconductor element package is characterized in that it is adhered via a metallized layer 23.

【0007】このように構成された半導体素子用パッケ
ージでは、蓋17の側壁をなす枠材26を蓋本体19と
は別部材としたので、半導体素子14に無理な力を加え
ずに半導体素子14をセラミック基板16及び蓋本体1
9に確実に固定した状態で空所18に収容できる。また
蓋本体19及び枠材26は比較的単純な形状であるの
で、半導体素子14との高さを合わせるために枠材26
を機械加工したとしても僅かな工数で済む。更に蓋本体
19、枠材26及びセラミック基板16がこれらの熱膨
張係数の間のα1≦α2≦α3という関係を満たすことに
より、半導体素子14の発熱及び冷却の繰返しによるセ
ラミック基板16、蓋17及び半導体素子14間の各接
着部、即ち第1〜第3はんだ11〜13に発生するスト
レスを緩和することができ、上記各熱膨張係数の僅かな
相違により第1〜第3はんだ11〜13に発生するスト
レスも縦弾性係数の小さい緩衝材24が伸縮することに
より低減することができる。
In the semiconductor element package thus constructed, the frame member 26 forming the side wall of the lid 17 is a separate member from the lid body 19, so that the semiconductor element 14 is not forced. The ceramic substrate 16 and the lid body 1
It can be accommodated in the empty space 18 in a state of being securely fixed to the space 9. Further, since the lid main body 19 and the frame member 26 have a relatively simple shape, the frame member 26 is formed in order to match the height with the semiconductor element 14.
Even if it is machined, it requires only a few steps. Further, the lid body 19, the frame member 26, and the ceramic substrate 16 satisfy the relationship of α 1 ≦ α 2 ≦ α 3 among these thermal expansion coefficients, whereby the ceramic substrate 16 due to repeated heat generation and cooling of the semiconductor element 14, It is possible to relieve the stress generated in each bonding portion between the lid 17 and the semiconductor element 14, that is, in the first to third solders 11 to 13, and the first to third solders 11 can be formed due to the slight difference in the thermal expansion coefficient. The stresses generated in the parts 13 to 13 can also be reduced by expanding and contracting the cushioning material 24 having a small longitudinal elastic coefficient.

【0008】請求項6に係る発明は、請求項1ないし5
いずれかに係る発明であって、更に図2に示すように蓋
本体19の上面にAl又はAgにより形成されたヒート
シンク45が積層接着されたことを特徴とする半導体素
子用パッケージである。このように構成されたパッケー
ジでは、半導体素子14の発した熱が第3はんだ13及
び蓋本体19を介してヒートシンク45からスムーズに
放散されるので、半導体素子14の温度上昇を低減する
ことができる。
The invention according to claim 6 relates to claims 1 to 5.
The invention according to any one of the aspects, further comprising a heat sink 45 made of Al or Ag laminated and adhered on the upper surface of the lid body 19 as shown in FIG. In the package configured as described above, the heat generated by the semiconductor element 14 is smoothly dissipated from the heat sink 45 via the third solder 13 and the lid body 19, so that the temperature rise of the semiconductor element 14 can be reduced. .

【0009】[0009]

【発明の実施の形態】蓋本体はセラミックスにより板状
に形成され、枠材はセラミックスにより矩形等の多角形
又は円形の枠状に形成される。セラミック基板はセラミ
ック層と回路層とが交互に積層されたセラミック多層配
線基板であり、板状に形成される。またセラミック基板
の下面には回路層と電気的に接続される多数のI/Oピ
ンが突設される。蓋本体はSiC,AlN,低温焼結材
料又はAl23により形成され、枠材はSiC,Al
N,低温焼結材料又はAl23により形成され、更にセ
ラミック基板はAlN,低温焼結材料又はAl23によ
り形成されることが好ましい。低温焼結材料としてはガ
ラス−セラミック系焼結材料やBaSn(BO32系焼
結材料等を用いることができる。上記SiC,AlN,
低温焼結材料及びAl23の熱膨張係数はSiCが最も
小さく、AlN,低温焼結材料,Al23の順に大きく
なる。従って、上記蓋本体、枠材及びセラミック基板を
それぞれ形成する材料は、蓋本体、枠材及びセラミック
基板の各熱膨張係数α1,α2及びα3がα1≦α2≦α3
関係を満たすように選択される。緩衝材はAl又はAg
により形成される。緩衝材をAlにより形成するときに
は、この厚さを0.1〜0.5mmの範囲にすることが
好ましい。これは緩衝材の厚さが0.1mm未満ではろ
う材中のSi成分が緩衝材のAl中に侵入して多くなり
Alが硬くなる不具合があり、0.5mmを越えるとセ
ラミックスが割れる不具合があるからである。また緩衝
材をAgにより形成するときには、この厚さを5〜20
μmの範囲にすることが好ましい。これは緩衝材の厚さ
が5μm未満では接合不良が発生する恐れがあり、20
μmを越えるとセラミックスが割れる不具合があるから
である。
BEST MODE FOR CARRYING OUT THE INVENTION The lid body is formed of ceramics in a plate shape, and the frame member is formed of ceramics in a polygonal shape such as a rectangle or a circular frame shape. The ceramic substrate is a ceramic multilayer wiring substrate in which ceramic layers and circuit layers are alternately laminated and is formed in a plate shape. Further, a large number of I / O pins that are electrically connected to the circuit layer are provided on the lower surface of the ceramic substrate. The lid body is made of SiC, AlN, low temperature sintering material or Al 2 O 3 , and the frame material is SiC, Al
It is preferable that the ceramic substrate is made of N, a low temperature sintered material or Al 2 O 3 , and the ceramic substrate is made of AlN, a low temperature sintered material or Al 2 O 3 . The low-temperature sintered materials glass - can be a ceramic-based sintered material and BaSn (BO 3) 2 sintered materials. SiC, AlN,
The coefficient of thermal expansion of the low temperature sintered material and Al 2 O 3 is the smallest in SiC, and increases in the order of AlN, low temperature sintered material, and Al 2 O 3 . Therefore, the materials for forming the lid main body, the frame member and the ceramic substrate are such that the thermal expansion coefficients α 1 , α 2 and α 3 of the lid main body, the frame member and the ceramic substrate are α 1 ≦ α 2 ≦ α 3 respectively . Selected to meet. Buffer material is Al or Ag
Is formed by. When the cushioning material is made of Al, it is preferable that the thickness is in the range of 0.1 to 0.5 mm. This is because when the thickness of the cushioning material is less than 0.1 mm, the Si component in the brazing filler metal penetrates into the Al of the cushioning material to increase the amount of Al and the Al becomes hard, and when it exceeds 0.5 mm, the ceramics cracks. Because there is. When the cushioning material is made of Ag, the thickness should be 5 to 20.
It is preferable to set it in the range of μm. This is because if the thickness of the cushioning material is less than 5 μm, there is a risk of defective bonding.
This is because if the thickness exceeds μm, there is a problem that the ceramic will crack.

【0010】(a) セラミック基板の上面周縁への第1メ
タライズ層の形成 セラミック基板が低温焼結材料により形成される場合 セラミック基板はグリーンシートに導体ペーストを印刷
し積層した後、焼成することにより作製され、多層配線
基板となる。セラミック基板を低温焼結材料により形成
する場合は、導体ペーストとしてAgを用い、120℃
で10分間乾燥し積層した後、375℃で40分間脱脂
し、更に875℃で20〜30分間焼成することにより
セラミック基板を得る。このとき第1メタライズ層もA
gにて同時に形成される。 セラミック基板がAlN,Al23又はSiCにより
形成される場合 セラミック基板をAlN,Al23又はSiCにより形
成する場合は、Wペーストを用い、多層配線基板を形成
する。第1メタライズ層もWにて同時に形成されるが、
はんだ付けをするため表面にNiめっきを施す。
(A) Formation of the first metallized layer on the peripheral edge of the upper surface of the ceramic substrate When the ceramic substrate is made of a low-temperature sintering material: The ceramic substrate is formed by printing a conductor paste on a green sheet, stacking the paste, and then firing the paste. It is produced and becomes a multilayer wiring board. When the ceramic substrate is made of low temperature sintering material, Ag is used as the conductor paste and the temperature is 120 ° C.
After 10 minutes of drying and stacking, degreasing is performed at 375 ° C. for 40 minutes, and then firing is performed at 875 ° C. for 20 to 30 minutes to obtain a ceramic substrate. At this time, the first metallization layer is also A
g at the same time. When the ceramic substrate is made of AlN, Al 2 O 3 or SiC When the ceramic substrate is made of AlN, Al 2 O 3 or SiC, W paste is used to form a multilayer wiring substrate. The first metallization layer is also formed of W at the same time,
Ni plating is applied to the surface for soldering.

【0011】(b) 枠材の下面への第2メタライズ層の形
成 第2メタライズ層がAlの場合 枠材が単体の状態で又は枠材及び蓋本体の接着時に枠材
の下面にAl−Si系ろう材を挟んで厚さ0.1〜0.
5mmのAl板を置き、これらに荷重0.5〜2kg/
cm2を加え、真空中で600〜630℃に5〜30分
間加熱することにより、Al板が枠材の下面に接着さ
れ、このAl板が第2メタライズ層となる。枠材に接着
された第2メタライズ層の下面にはNiめっきを施すこ
とが好ましい。 第2メタライズ層がAgの場合 枠材が単体の状態で又は枠材及び蓋本体の接着時に枠材
の下面にAgペーストを塗布して100〜150℃に5
〜30分間加熱して乾燥させ、大気中で800〜900
℃に5〜30分間加熱することにより、上記Agペース
トが厚さ5〜20μmの第2メタライズ層となる。Ag
ペーストが塗布される枠材がAlNにより形成される場
合には、Agペースト中のガラス成分の反応を抑えるた
めに、Agペーストを塗布する前にAgペーストを塗布
する面を酸化処理し更にSiO2がコーティングされる
ことが好ましい。
(B) Formation of the second metallized layer on the lower surface of the frame material When the second metallized layer is Al When the frame material is alone or when the frame material and the lid main body are bonded, Al-Si is formed on the lower surface of the frame material. The thickness is 0.1 to 0.
Place an Al plate of 5 mm and load 0.5-2 kg /
By adding cm 2 and heating in vacuum at 600 to 630 ° C. for 5 to 30 minutes, the Al plate is bonded to the lower surface of the frame material, and this Al plate becomes the second metallized layer. The lower surface of the second metallization layer bonded to the frame material is preferably plated with Ni. When the second metallization layer is Ag When the frame material is used alone or when the frame material and the lid body are adhered, the Ag paste is applied to the lower surface of the frame material to 100 to 150 ° C.
~ 30 minutes heating to dry, 800 ~ 900 in air
By heating at 5 ° C. for 5 to 30 minutes, the Ag paste becomes a second metallized layer having a thickness of 5 to 20 μm. Ag
When the frame material to which the paste is applied is formed of AlN, in order to suppress the reaction of the glass component in the Ag paste, the surface on which the Ag paste is applied is subjected to an oxidation treatment before applying the Ag paste and further SiO 2 Are preferably coated.

【0012】(c) 蓋本体の下面への第3メタライズ層の
形成 第3メタライズ層がAlの場合 蓋本体が単体の状態で又は蓋本体及び枠材の接着時に蓋
本体下面の所定の位置にAl−Si系ろう材を挟んで厚
さ0.1〜0.5mmAl板を置き、これらに荷重0.
5〜2kg/cm2を加え、真空中で600〜630℃
に5〜30分間加熱することにより、Al板が蓋本体下
面の所定の位置に接着され、このAl板が第3メタライ
ズ層となる。蓋本体に接着された第2メタライズ層の下
面にはNiめっきを施すことが好ましい。 第3メタライズ層がAgの場合 蓋本体が単体の状態で又は蓋本体及び枠材の接着時に蓋
本体下面の所定の位置にAgペーストを塗布して100
〜150℃に5〜30分間加熱して乾燥させ、大気中で
800〜900℃に5〜30分間加熱することにより、
上記Agペーストが厚さ5〜20μmの第3メタライズ
層となる。Agペーストが塗布される蓋本体がAlNに
より形成される場合には、Agペースト中のガラス成分
の反応を抑えるために、Agペーストを塗布する前にA
gペーストを塗布する面を酸化処理し更にSiO2がコ
ーティングされることが好ましい。
(C) Formation of the third metallized layer on the lower surface of the lid body When the third metallized layer is Al, the lid body is in a single state or at a predetermined position on the lower surface of the lid body when the lid body and the frame material are bonded. An Al-Si brazing material is sandwiched between Al plates having a thickness of 0.1 to 0.5 mm, and a load of 0.
5 ~ 2kg / cm 2 added, 600 ~ 630 ℃ in vacuum
By heating for 5 to 30 minutes, the Al plate is bonded to a predetermined position on the lower surface of the lid body, and this Al plate becomes the third metallized layer. The lower surface of the second metallization layer bonded to the lid body is preferably plated with Ni. When the third metallized layer is Ag: The Ag paste is applied to a predetermined position on the lower surface of the lid body when the lid body is a single body or when the lid body and the frame material are adhered.
By heating to ~ 150 ° C for 5 to 30 minutes to dry, and heating in air to 800 to 900 ° C for 5 to 30 minutes,
The Ag paste serves as a third metallized layer having a thickness of 5 to 20 μm. If the lid body to which the Ag paste is applied is made of AlN, in order to suppress the reaction of the glass component in the Ag paste, A before applying the Ag paste
It is preferable that the surface on which the g paste is applied is oxidized and further coated with SiO 2 .

【0013】(d) 蓋本体に枠材を接着することによる蓋
の形成 緩衝材がAlの場合 枠材、Al−Si系ろう材、緩衝材、Al−Si系ろう
材及び蓋本体を順に重ね、これらに荷重0.5〜2kg
/cm2を加え、真空中で600〜630℃に5〜30
分間加熱することにより、蓋本体に枠材が接着されて蓋
が形成される。 緩衝材がAgの場合 蓋本体の下面のうち枠材に対向する位置にAgペースト
を塗布して100〜150℃に5〜30分間加熱して乾
燥させ、枠材の上面にAgペーストを塗布して5〜30
℃に5〜30分間加熱して乾燥させる。蓋本体と枠材と
を重ね、大気中で800〜900℃に5〜30分間加熱
することにより、蓋本体に枠材が接着されて蓋が形成さ
れる。上記Agペーストは厚さ5〜20μmの緩衝材と
なる。Agペーストが塗布される蓋本体又は枠材がAl
Nにより形成される場合には、Agペースト中のガラス
成分の反応を抑えるために、Agペーストを塗布する前
にAgペーストを塗布する面を酸化処理し更にSiO2
がコーティングされることが好ましい。
(D) Forming a lid by adhering a frame material to the lid body When the cushioning material is Al A frame material, an Al-Si type brazing material, a cushioning material, an Al-Si type brazing material and a lid body are stacked in this order. , 0.5 to 2kg load on these
/ Cm 2 was added, 5-30 to six hundred to six hundred and thirty ° C. in vacuo
By heating for a minute, the frame material is bonded to the lid body to form the lid. When the cushioning material is Ag: The Ag paste is applied to a position facing the frame material on the lower surface of the lid body, heated to 100 to 150 ° C. for 5 to 30 minutes and dried, and the Ag paste is applied to the upper surface of the frame material. 5-30
Heat to 5 ° C for 5-30 minutes to dry. The lid body and the frame material are overlapped and heated in the atmosphere at 800 to 900 ° C. for 5 to 30 minutes to bond the frame material to the lid body to form the lid. The Ag paste serves as a buffer material having a thickness of 5 to 20 μm. The lid body or frame material to which Ag paste is applied is Al
In the case of being formed by N, in order to suppress the reaction of the glass component in the Ag paste, the surface on which the Ag paste is applied is subjected to an oxidation treatment before applying the Ag paste and further SiO 2
Are preferably coated.

【0014】(e) 半導体素子のセラミック基板への固定 セラミック基板に蓋を接着する前にセラミック基板上面
の回路層に半導体素子が第1はんだであるはんだバンプ
を介して固定される。具体的には半導体素子下面の電極
に盛り上げられた第1はんだをセラミック基板上面の回
路層の端子にフラックスの粘着力で仮固定し、この状態
で330〜360℃に5〜10秒間加熱して第1はんだ
を溶融することにより、半導体素子がセラミック基板に
固定される。
(E) Fixing of Semiconductor Element to Ceramic Substrate Before adhering the lid to the ceramic substrate, the semiconductor element is fixed to the circuit layer on the upper surface of the ceramic substrate via the solder bump which is the first solder. Specifically, the first solder that is raised on the electrode on the lower surface of the semiconductor element is temporarily fixed to the terminal of the circuit layer on the upper surface of the ceramic substrate by the adhesive force of flux, and in this state, it is heated to 330 to 360 ° C. for 5 to 10 seconds. The semiconductor element is fixed to the ceramic substrate by melting the first solder.

【0015】(f) 蓋のセラミック基板及び半導体素子へ
の接着 半導体素子が固定されたセラミック基板上面の第1メタ
ライズ層に第2はんだを載せ、半導体素子の上面に第3
はんだを載せた状態で、枠材下面の第2メタライズ層が
第2はんだに対向し、蓋本体の下面の第3メタライズ層
が第3はんだに対向するように蓋をセラミック基板に被
せ、更にこの状態でリフロー炉で220〜250℃に5
〜10秒間加熱することにより、蓋がセラミック基板及
び半導体素子に接着される。
(F) Adhesion of Lid to Ceramic Substrate and Semiconductor Element The second solder is placed on the first metallization layer on the upper surface of the ceramic substrate on which the semiconductor element is fixed, and the third solder is placed on the upper surface of the semiconductor element.
With the solder placed, the lid is placed on the ceramic substrate so that the second metallized layer on the lower surface of the frame member faces the second solder and the third metallized layer on the lower surface of the lid body faces the third solder. In a reflow oven at 220-250 ° C for 5
The lid is bonded to the ceramic substrate and the semiconductor element by heating for 10 seconds.

【0016】(g) ヒートシンク ヒートシンクがAlの場合 蓋本体が単体の状態でこの蓋本体の上面にAl−Si系
ろう材を挟んでヒートシンクを重ね、これらに荷重0.
5〜2kg/cm2を加え、真空中で600〜630℃
に5〜30分間加熱することにより、蓋本体にヒートシ
ンクが接着される。ヒートシンクとしては、板状のヒー
トシンク、Al板をプレス成形することにより蜂の巣状
に形成されたコルゲートハニカムフィンを有するヒート
シンク、Al板をプレス成形することにより多数の窓が
形成されたコルゲートルーバフィンを有するヒートシン
ク、アルミダイカスト鋳造法等により形成され多数の板
状又はピン状のフィンを有するヒートシンク等が挙げら
れる。 ヒートシンクがAgの場合 蓋本体の上面にAgペーストを塗布して100〜150
℃に5〜30分間加熱して乾燥させ、大気中で800〜
900℃に5〜30分間加熱することにより、上記Ag
ペーストが厚さ5〜20μmのヒートシンクとなる。A
gペーストが塗布される蓋本体がAlNにより形成され
る場合には、Agペースト中のガラス成分の反応を抑え
るために、Agペーストを塗布する前にAgペーストを
塗布する面を酸化処理し更にSiO2がコーティングさ
れることが好ましい。
(G) Heat sink When the heat sink is made of Al In the state where the lid body is a single body, the heat sink is placed on the upper surface of the lid body with the Al-Si brazing material sandwiched therebetween, and a load of 0.
5 ~ 2kg / cm 2 added, 600 ~ 630 ℃ in vacuum
The heat sink is adhered to the lid body by heating for 5 to 30 minutes. The heat sink includes a plate-shaped heat sink, a heat sink having corrugated honeycomb fins formed in a honeycomb shape by press-molding an Al plate, and a corrugated louver fin having a large number of windows formed by press-molding an Al plate. Examples thereof include a heat sink and a heat sink having a large number of plate-shaped or pin-shaped fins formed by an aluminum die casting method or the like. When the heat sink is Ag 100 to 150 by applying Ag paste on the top surface of the lid body
800 ~ in the air by heating to ℃ 5-30 minutes to dry
By heating to 900 ° C. for 5 to 30 minutes, the above Ag
The paste becomes a heat sink having a thickness of 5 to 20 μm. A
When the lid body to which the g paste is applied is made of AlN, the surface to which the ag paste is applied is oxidized before applying the ag paste in order to suppress the reaction of the glass components in the ag paste. 2 is preferably coated.

【0017】上記Al−Si系ろう材としては、Al−
7.5%Si箔(重量%、以下同じ)、Al−13%S
i箔、Al−9.5%Si−1.0%Mg箔、Al−
7.5%Si−10%Ge箔等のろう材が例示される。
また上記第1はんだとしては、95%Pb−5%Sn
箔,90%Pb−10%Sn箔等のはんだが例示され、
第2及び第3はんだとしては、Sn−3.5%Ag箔,
Pb−50%In箔,37%Pb−63%Sn箔、40
%Pb−60%Sn箔,36%Pb−62%Sn−2%
Ag箔等のはんだが例示される。
As the Al-Si type brazing material, Al-
7.5% Si foil (weight%, the same below), Al-13% S
i foil, Al-9.5% Si-1.0% Mg foil, Al-
A brazing material such as 7.5% Si-10% Ge foil is exemplified.
As the first solder, 95% Pb-5% Sn
Examples of solder include foil and 90% Pb-10% Sn foil.
As the second and third solders, Sn-3.5% Ag foil,
Pb-50% In foil, 37% Pb-63% Sn foil, 40
% Pb-60% Sn foil, 36% Pb-62% Sn-2%
An example of the solder is Ag foil.

【0018】[0018]

【実施例】次に本発明の実施例を図面に基づいて詳しく
説明する。 <実施例1〜9>図1に示すように、半導体素子用パッ
ケージ10は上面に半導体素子14が第1はんだ11を
介して固定されたセラミック基板16と、半導体素子1
4を収容可能な空所18を有する蓋17とを備え、蓋1
7は半導体素子14の上面を覆う蓋本体19と、蓋本体
19とは別部材により形成され上面が蓋本体19の下面
周縁に緩衝材24を介して接着されかつ半導体素子14
の側面を覆う枠材26とを有する。表1に示すように蓋
本体19としてはAlN,SiCを、緩衝材18として
はAlを、枠材26としてはAlN,Al23,低温焼
結材料,SiCを、セラミック基板16としてはAl2
3,低温焼結材料,AlNを、それぞれ用い、蓋本体
19と枠材26とセラミック基板16の熱膨張係数をそ
れぞれα1とα2とα3とするときα1≦α2≦α3の関係を
満たすように蓋本体19と枠材26とセラミック基板1
6とを組合せた。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. <Examples 1 to 9> As shown in FIG. 1, a semiconductor element package 10 includes a ceramic substrate 16 having a semiconductor element 14 fixed to the upper surface thereof via first solder 11, and a semiconductor element 1
And a lid 17 having an empty space 18 capable of accommodating the
Reference numeral 7 denotes a lid main body 19 which covers the upper surface of the semiconductor element 14, and a member separate from the lid main body 19, and the upper surface is adhered to the lower peripheral edge of the lid main body 19 via a cushioning material 24.
And a frame member 26 that covers the side surface of the. As shown in Table 1, AlN and SiC are used as the lid body 19, Al is used as the buffer material 18, AlN, Al 2 O 3 , low temperature sintering material and SiC are used as the frame material 26, and Al is used as the ceramic substrate 16. 2
When O 3 , the low temperature sintering material, and AlN are used, and the thermal expansion coefficients of the lid body 19, the frame member 26, and the ceramic substrate 16 are α 1 , α 2, and α 3 , respectively, α 1 ≦ α 2 ≦ α 3 So as to satisfy the above relationship, the lid body 19, the frame member 26, and the ceramic substrate 1
6 was combined.

【0019】上記低温焼結材としてはDuPont社製
の商品名「低温焼結材料951」を使用した。SiC,
AlN,低温焼結材料及びAl23の熱膨張係数はそれ
ぞれ4.2×10-6/℃,4.6×10-6/℃,5.8
×10-6/℃及び6.7×10-6/℃であった。蓋本体
19は縦横がそれぞれ40mmで高さが0.38mmの
板であり、緩衝材24は厚さが0.2mmでありかつ内
部に縦横がそれぞれ18mmの矩形の空所18を有し、
枠材26は高さが0.38mmでありかつ上記緩衝材2
4と同一形状の空所を有した。またセラミック基板16
は縦横がそれぞれ40mmで高さが1.5mmであり、
半導体素子14は縦横がそれぞれ10mmで高さが0.
5mmであった。これらの半導体素子用パッケージ10
を次のように製造した。
As the low-temperature sintered material, "Low-temperature sintered material 951" manufactured by DuPont was used. SiC,
AlN, low temperature sintering material and Al 2 O 3 is the thermal expansion coefficient of each 4.2 × 10 -6 /℃,4.6×10 -6 /℃,5.8
It was x10 -6 / ° C and 6.7 x 10 -6 / ° C. The lid body 19 is a plate having a length and width of 40 mm and a height of 0.38 mm, and the cushioning member 24 has a thickness of 0.2 mm and has a rectangular void 18 having a length and width of 18 mm.
The frame member 26 has a height of 0.38 mm and the cushioning member 2
4 had a void of the same shape. Also, the ceramic substrate 16
Is 40 mm in length and width and 1.5 mm in height,
The semiconductor element 14 has a length and width of 10 mm and a height of 0.
It was 5 mm. These semiconductor device packages 10
Was manufactured as follows.

【0020】先ずセラミック基板16、枠材26及び蓋
本体19がそれぞれ単体の状態でセラミック基板16の
上面周縁に第1メタライズ層21を、枠材26の下面に
第2メタライズ層22を、更に蓋本体19の下面中央に
第3メタライズ層23をそれぞれ形成した。第1メタラ
イズ層21はセラミック基板16の作製と同時にこの基
板16の上面周縁に位置するように形成した。第2メタ
ライズ層22は枠材26の下面にAl−7.5%Si箔
ろう材27を挟んで厚さ0.2mmのAl板を置き、こ
れらに荷重2kg/cm2を加え、真空中で630℃に
10分間加熱することにより形成した。第3メタライズ
層23は蓋本体19の下面中央にAl−7.5%Si箔
ろう材27を挟んで厚さ0.2mmAl板を置き、これ
らに荷重2kg/cm2を加え、真空中で630℃に1
0分間加熱することにより形成した。蓋17と枠材26
とを接合した後に、第2及び第3メタライズ層22,2
3の表面にはNiめっき(図示せず)を施した。
First, the ceramic substrate 16, the frame member 26, and the lid main body 19 are in a single state, and the first metallization layer 21 is provided on the upper surface of the ceramic substrate 16, the second metallization layer 22 is provided on the lower surface of the frame member 26, and the lid is further provided. Third metallized layers 23 were formed in the center of the lower surface of the main body 19. The first metallization layer 21 was formed so as to be located on the peripheral edge of the upper surface of the ceramic substrate 16 at the same time when the ceramic substrate 16 was manufactured. For the second metallization layer 22, an Al plate having a thickness of 0.2 mm is placed on the lower surface of the frame member 26 with an Al-7.5% Si foil brazing material 27 interposed therebetween, and a load of 2 kg / cm 2 is applied to these, and the vacuum is applied in a vacuum. It was formed by heating to 630 ° C. for 10 minutes. For the third metallized layer 23, an Al-7.5% Si foil brazing material 27 is sandwiched between Al plates having a thickness of 0.2 mm and a load of 2 kg / cm 2 is applied to the third metallized layer 23 at 630 in vacuum. 1 to ℃
It was formed by heating for 0 minutes. Lid 17 and frame material 26
And the second and third metallization layers 22, 2 are joined.
The surface of 3 was plated with Ni (not shown).

【0021】次に枠材26、Al−7.5%Si箔ろう
材27、緩衝材24、Al−7.5%Si箔ろう材27
及び蓋本体19を下から順に重ね、これらに荷重2kg
/cm2を加え、真空中で630℃に10分間加熱する
ことにより、蓋本体19に枠材26を接着して蓋17を
形成した。またセラミック基板16上面の回路層16a
には半導体素子14を第1はんだ11であるはんだバン
プを介して固定した。具体的には半導体素子14下面の
電極(図示せず)に盛り上げられた第1はんだ11をセ
ラミック基板16上面の回路層16aの端子にフラック
スの粘着力で仮固定し、この状態で350℃に10秒間
加熱して第1はんだ11を溶融することにより、半導体
素子14をセラミック基板16に固定した。
Next, the frame material 26, the Al-7.5% Si foil brazing material 27, the cushioning material 24, and the Al-7.5% Si foil brazing material 27.
And the lid body 19 are stacked in order from the bottom, and a load of 2 kg is applied to them.
/ Cm 2 was added and heated at 630 ° C. for 10 minutes in vacuum to bond the frame member 26 to the lid body 19 to form the lid 17. The circuit layer 16a on the upper surface of the ceramic substrate 16
The semiconductor element 14 is fixed to the semiconductor chip via the solder bump which is the first solder 11. Specifically, the first solder 11 raised on the electrode (not shown) on the lower surface of the semiconductor element 14 is temporarily fixed to the terminal of the circuit layer 16a on the upper surface of the ceramic substrate 16 by the adhesive force of flux, and in this state, the temperature is raised to 350 ° C. The semiconductor element 14 was fixed to the ceramic substrate 16 by heating for 10 seconds to melt the first solder 11.

【0022】更にセラミック基板16上面の第1メタラ
イズ層21に第2はんだ12を載せ、半導体素子14の
上面に第3はんだ13を載せた状態で、枠材26下面の
第2メタライズ層22が第2はんだ12に対向し、蓋本
体19の下面の第3メタライズ層23が第3はんだ13
に対向するように蓋17をセラミック基板16に被せ、
この状態でリフロー炉で250℃に5秒間加熱すること
により、蓋17をセラミック基板16及び半導体素子1
4に接着してパッケージ10を作製した。第1はんだ1
1としては95%Pb−5%Sn箔を用い、第2及び第
3はんだ12,13としてはSn−3.5%Ag箔をそ
れぞれ用いた。また29はセラミック基板16の下面に
突設されたI/Oピンである。
Further, with the second solder 12 placed on the first metallization layer 21 on the upper surface of the ceramic substrate 16 and the third solder 13 placed on the upper surface of the semiconductor element 14, the second metallization layer 22 on the lower surface of the frame member 26 is The third metallization layer 23 on the lower surface of the lid body 19 faces the second solder 12 and the third solder 13
Cover the ceramic substrate 16 so as to face the
In this state, the lid 17 is heated at 250 ° C. for 5 seconds in the reflow furnace to cover the lid 17 with the ceramic substrate 16 and the semiconductor element 1.
4 was adhered to make a package 10. 1st solder 1
95% Pb-5% Sn foil was used as No. 1, and Sn-3.5% Ag foil was used as each of the second and third solders 12 and 13. Reference numeral 29 is an I / O pin provided on the lower surface of the ceramic substrate 16.

【0023】<実施例10〜19>図2及び表1に示す
ように、蓋本体19としてはAlN,SiC,Al23
を、緩衝材24としてはAlを、枠材26としてはAl
N,Al23,低温焼結材料,SiCを、セラミック基
板16としてはAl23,低温焼結材料,AlNを、そ
れぞれ用い、蓋本体19と枠材26とセラミック基板1
6の熱膨張係数をそれぞれα1とα2とα3とするときα1
≦α2≦α3の関係を満たすように蓋本体19と枠材26
とセラミック基板16とを組合せ、かつ蓋本体19の上
面にヒートシンク45を積層接着して半導体素子用パッ
ケージ40を作製した。ヒートシンク45の蓋本体19
への積層接着方法としては、蓋本体19が単体の状態で
この蓋本体19の上面にAl−7.5%Si箔ろう材2
7を挟んでヒートシンク45となる厚さ0.2mmのA
l板を重ね、これらに荷重2kg/cm2を加え、真空
中で630℃に10分間加熱することにより行った。上
記以外は実施例1〜9と略同様に構成した。
<Examples 10 to 19> As shown in FIG. 2 and Table 1, the lid body 19 is made of AlN, SiC, Al 2 O 3.
As the buffer material 24 and Al as the frame material 26
N, Al 2 O 3 , low-temperature sintering material and SiC are used as the ceramic substrate 16, and Al 2 O 3 , low-temperature sintering material and AlN are used as the ceramic substrate 16, respectively, and the lid body 19, the frame member 26 and the ceramic substrate 1 are used.
When the thermal expansion coefficients of 6 are α 1 , α 2 and α 3 , respectively, α 1
The lid main body 19 and the frame member 26 are made to satisfy the relationship of ≦ α 2 ≦ α 3.
And the ceramic substrate 16 are combined, and the heat sink 45 is laminated and adhered on the upper surface of the lid body 19 to manufacture the semiconductor element package 40. Lid body 19 of heat sink 45
As a method of laminating and adhering the same to the upper surface of the lid main body 19 with the lid main body 19 as a single body, Al-7.5% Si foil brazing material 2
A with a thickness of 0.2 mm that becomes the heat sink 45 by sandwiching 7
1 plates were overlapped, a load of 2 kg / cm 2 was applied to these, and heating was performed at 630 ° C. for 10 minutes in vacuum. Except for the above, the configuration was substantially the same as in Examples 1-9.

【0024】<実施例20〜24>図3及び表1に示す
ように、蓋本体59としてはAlNを、緩衝材64とし
てはAgを、枠材66としてはAlN,Al23,低温
焼結材料を、セラミック基板16としてはAl23,低
温焼結材料を、それぞれ用い、蓋本体59と枠材66と
セラミック基板16の熱膨張係数をそれぞれα1とα2
α3とするときα1≦α2≦α3の関係を満たすように蓋本
体59と枠材66とセラミック基板16とを組合せて半
導体素子用パッケージ50を作製した。蓋本体59、セ
ラミック基板16及び半導体素子14の寸法は実施例1
〜9のものとそれぞれ同一であった。枠材66は高さが
0.635mmでありかつ内部に縦横がそれぞれ18m
mの矩形の空所58を有した。これらの半導体素子用パ
ッケージ50を次のように製造した。
<Examples 20 to 24> As shown in FIG. 3 and Table 1, AlN is used as the lid main body 59, Ag is used as the buffer material 64, AlN, Al 2 O 3 is used as the frame material 66, and low temperature firing is performed. The binder material is Al 2 O 3 for the ceramic substrate 16 and the low temperature sintering material is used, and the thermal expansion coefficients of the lid main body 59, the frame member 66 and the ceramic substrate 16 are α 1 , α 2 and α 3 , respectively. At this time, the lid body 59, the frame member 66, and the ceramic substrate 16 were combined so as to satisfy the relationship of α 1 ≦ α 2 ≦ α 3 to manufacture the semiconductor element package 50. The dimensions of the lid body 59, the ceramic substrate 16 and the semiconductor element 14 are the same as those in the first embodiment.
~ 9 respectively. The frame material 66 has a height of 0.635 mm and has a length and width of 18 m inside.
It had a rectangular void 58 of m. These semiconductor device packages 50 were manufactured as follows.

【0025】先ずセラミック基板16、枠材66及び蓋
本体59がそれぞれ単体の状態でセラミック基板16の
上面周縁に第1メタライズ層61を、枠材66の下面に
第2メタライズ層62を、更に蓋本体59の下面中央に
第3メタライズ層63をそれぞれ形成した。第1メタラ
イズ層61はセラミック基板16の作製と同時にこの基
板16の上面周縁に位置するように形成した。第2メタ
ライズ層62は枠材66の下面にAgペーストを塗布し
て150℃に10分間加熱して乾燥させ、大気中で85
0℃に10分間加熱することにより形成した。第3メタ
ライズ層63は蓋本体59の下面中央にAgペーストを
塗布して150℃に10分間加熱して乾燥させ、大気中
で850℃に10分間加熱することにより形成した。第
2及び第3メタライズ層の厚さは同一の10μmであっ
た。Agペーストが塗布されるセラミック基板16、枠
材66又は蓋本体59がAlNにより形成される場合に
は、Agペーストを塗布する前にAgペーストを塗布す
る面を酸化処理し更にSiO2をコーティングした(図
示せず)。
First, the ceramic substrate 16, the frame member 66, and the lid main body 59 are in the state of a single body, the first metallization layer 61 is provided on the periphery of the upper surface of the ceramic substrate 16, the second metallization layer 62 is provided on the lower surface of the frame member 66, and the lid is further provided. Third metallized layers 63 were formed in the center of the lower surface of the main body 59. The first metallized layer 61 was formed so as to be located on the peripheral edge of the upper surface of the ceramic substrate 16 at the same time when the ceramic substrate 16 was manufactured. The second metallized layer 62 is formed by applying Ag paste on the lower surface of the frame material 66, heating it at 150 ° C. for 10 minutes and drying it, and then 85
It was formed by heating to 0 ° C. for 10 minutes. The third metallized layer 63 was formed by applying Ag paste to the center of the lower surface of the lid body 59, heating it to 150 ° C. for 10 minutes to dry it, and then heating it to 850 ° C. for 10 minutes in the atmosphere. The second and third metallized layers had the same thickness of 10 μm. When the ceramic substrate 16, the frame member 66, or the lid main body 59 to which the Ag paste is applied is formed of AlN, the surface on which the Ag paste is applied is subjected to an oxidation treatment and further coated with SiO 2 before applying the Ag paste. (Not shown).

【0026】次に蓋本体59の下面のうち枠材66に対
向する位置にAgペーストを塗布して150℃に10分
間加熱して乾燥させ、枠材66の上面にAgペーストを
塗布して150℃に10分間加熱して乾燥させ、蓋本体
59と枠材66とを重ね、大気中で850℃に10分間
加熱することにより、蓋本体59に枠材66を接着して
蓋57を形成した。上記Agペーストは厚さ20μmの
緩衝材64となる。Agペーストが塗布される蓋本体5
9又は枠材66がAlNにより形成される場合には、A
gペーストを塗布する前にAgペーストを塗布する面を
酸化処理した後SiO2をコーティングした(図示せ
ず)。またセラミック基板16上面の回路層16aには
半導体素子14を第1はんだ11であるはんだバンプを
介して固定した。
Next, the Ag paste is applied to the position on the lower surface of the lid main body 59 facing the frame material 66, heated at 150 ° C. for 10 minutes and dried, and the Ag paste is applied to the upper surface of the frame material 66 and applied 150 The lid body 59 and the frame material 66 are overlapped with each other by heating at 850 ° C. for 10 minutes, and the frame material 66 is adhered to the lid body 59 to form the lid 57 by heating at 850 ° C. for 10 minutes in the atmosphere. . The Ag paste serves as the buffer material 64 having a thickness of 20 μm. Lid body 5 to which Ag paste is applied
9 or when the frame material 66 is made of AlN, A
Before applying the g paste, the surface on which the Ag paste is applied was oxidized and then coated with SiO 2 (not shown). Further, the semiconductor element 14 was fixed to the circuit layer 16a on the upper surface of the ceramic substrate 16 via solder bumps which were the first solders 11.

【0027】更にセラミック基板16上面の第1メタラ
イズ層61に第2はんだ12を載せ、半導体素子14の
上面に第3はんだ13を載せた状態で、枠材66下面の
第2メタライズ層62が第2はんだ12に対向し、蓋本
体59の下面の第3メタライズ層63が第3はんだ13
に対向するように蓋57をセラミック基板16に被せ、
この状態でリフロー炉で250℃に10秒間加熱するこ
とにより、蓋57をセラミック基板16及び半導体素子
14に接着してパッケージ50を作製した。28はセラ
ミック基板16の下面に突設されたI/Oピンである。
Further, with the second solder 12 placed on the first metallization layer 61 on the upper surface of the ceramic substrate 16 and the third solder 13 placed on the upper surface of the semiconductor element 14, the second metallization layer 62 on the lower surface of the frame member 66 is The third metallization layer 63 on the lower surface of the lid body 59 faces the second solder 12 and the third solder 13
Cover 57 on the ceramic substrate 16 so as to face
In this state, the lid 57 was adhered to the ceramic substrate 16 and the semiconductor element 14 by heating at 250 ° C. for 10 seconds in a reflow furnace to manufacture the package 50. Reference numeral 28 is an I / O pin projectingly provided on the lower surface of the ceramic substrate 16.

【0028】<実施例25〜29>図4及び表1に示す
ように、蓋本体59としてはAlNを、緩衝材64とし
てはAgを、枠材66としてはAlN,Al23,低温
焼結材料を、セラミック基板16としてはAl23,低
温焼結材料を、それぞれ用い、蓋本体59と枠材66と
セラミック基板16の熱膨張係数をそれぞれα1とα2
α3とするときα1≦α2≦α3の関係を満たすように蓋本
体59と枠材66とセラミック基板16とを組合せ、か
つ蓋本体59の上面にヒートシンク85を積層接着して
半導体素子用パッケージ80を作製した。ヒートシンク
85の蓋本体59への積層接着方法としては、蓋本体5
9の上面にAgペーストを塗布して150℃に10分間
加熱して乾燥させ、大気中で850℃に10分間加熱す
ることにより行った。ヒートシンク85の厚さは20μ
mであった。またAgペーストを塗布する前に、蓋本体
59のAgペーストを塗布する面を酸化処理し、更にS
iO2をコーティングした(図示せず)。上記以外は実
施例20〜24と略同様に構成した。
<Examples 25 to 29> As shown in FIG. 4 and Table 1, AlN is used as the lid main body 59, Ag is used as the cushioning material 64, and AlN, Al 2 O 3 is used as the frame material 66, and low temperature baking is performed. The binder material is Al 2 O 3 for the ceramic substrate 16 and the low temperature sintering material is used, and the thermal expansion coefficients of the lid main body 59, the frame member 66 and the ceramic substrate 16 are α 1 , α 2 and α 3 , respectively. At this time, the lid main body 59, the frame member 66, and the ceramic substrate 16 are combined so as to satisfy the relationship of α 1 ≦ α 2 ≦ α 3 , and the heat sink 85 is laminated and adhered to the upper surface of the lid main body 59 to form the semiconductor element package 80. It was made. As a method for laminating the heat sink 85 to the lid body 59, the lid body 5
The Ag paste was applied to the upper surface of No. 9, heated to 150 ° C. for 10 minutes to be dried, and then heated to 850 ° C. for 10 minutes in the atmosphere. The thickness of the heat sink 85 is 20μ
m. Before applying the Ag paste, the surface of the lid main body 59 to which the Ag paste is applied is subjected to an oxidation treatment, and further S
The iO 2 was coated (not shown). Except for the above, the configuration was substantially the same as in Examples 20-24.

【0029】<比較例1及び4>図5及び表1に示すよ
うに、蓋7aをAlNにより一体的に形成し、セラミッ
ク基板6を低温焼結材料又はAl23により形成した。
第1メタライズ層3aはセラミック基板6の作製と同時
にこの基板6の上面周縁に位置するように形成した。第
1メタライズ層3aに対向する蓋7aの下面には第2メ
タライズ層3bを形成し、セラミック基板6に第1はん
だ2aを介して固定された半導体素子4の上面に対向す
る蓋7aの下面中央には第3メタライズ層3cを形成し
た。第2及び第3メタライズ層3a〜3cは、塗布され
たAgペーストを150℃に10分間加熱して乾燥さ
せ、大気中で850℃に10分間加熱することにより形
成した。またAlNにより形成された蓋7aのうちAg
ペーストを塗布する面には、Agペーストを塗布する前
に、酸化処理し更にSiO2をコーティングした(図示
せず)。セラミック基板6上面の第1メタライズ層3a
に第2はんだ2bを載せ、半導体素子4の上面に第3は
んだ2cを載せた状態で、第2メタライズ層3bが第2
はんだ2bに対向しかつ第3メタライズ層3cが第3は
んだ2cに対向するように蓋7aをセラミック基板6に
被せ、この状態でリフロー炉で250℃に10秒間加熱
することにより、蓋7aをセラミック基板6及び半導体
素子4に接着してパッケージ1aを作製した。蓋7aは
縦横がそれぞれ40mmで高さが1.2mmであり、空
所8は縦横がそれぞれ18mmで深さが0.8mmであ
り、セラミック基板6は縦横がそれぞれ40mmで高さ
が1.5mmであり、半導体素子4は縦横がそれぞれ1
0mmで高さが0.5mmであった。
<Comparative Examples 1 and 4> As shown in FIG. 5 and Table 1, the lid 7a was integrally formed of AlN, and the ceramic substrate 6 was formed of a low temperature sintering material or Al 2 O 3 .
The first metallization layer 3a was formed so as to be located on the peripheral edge of the upper surface of the ceramic substrate 6 at the same time as the production of the ceramic substrate 6. The second metallization layer 3b is formed on the lower surface of the lid 7a facing the first metallization layer 3a, and the lower surface center of the lid 7a facing the upper surface of the semiconductor element 4 fixed to the ceramic substrate 6 via the first solder 2a. A third metallization layer 3c was formed on the substrate. The second and third metallized layers 3a to 3c were formed by heating the applied Ag paste at 150 ° C. for 10 minutes to dry it and then heating it at 850 ° C. for 10 minutes in the atmosphere. Also, of the lid 7a formed of AlN, Ag
Before the Ag paste was applied, the surface to which the paste was applied was oxidized and further coated with SiO 2 (not shown). The first metallization layer 3a on the upper surface of the ceramic substrate 6
The second solder 2b is placed on the second metallization layer 3b and the third solder 2c is placed on the upper surface of the semiconductor element 4,
The lid 7a is covered on the ceramic substrate 6 so as to face the solder 2b and the third metallization layer 3c faces the third solder 2c, and in this state, the lid 7a is heated to 250 ° C. for 10 seconds to make the lid 7a ceramic. The package 1a was manufactured by adhering it to the substrate 6 and the semiconductor element 4. The lid 7a has a length and width of 40 mm and a height of 1.2 mm, the cavity 8 has a length and width of 18 mm and a depth of 0.8 mm, and the ceramic substrate 6 has a length and width of 40 mm and a height of 1.5 mm. And the semiconductor element 4 is 1 in each of the vertical and horizontal directions.
The height was 0 mm at 0 mm.

【0030】<比較例2、3、5及び6>図6及び表1
に示すように、蓋7bをコバール(Kovar)又はC
u/W合金により一体的に形成し、セラミック基板6を
低温焼結材料又はAl23により形成し、上記材料を組
合せて4種類の半導体素子用パッケージ1bを作製し
た。第1メタライズ層3aはセラミック基板6の作製と
同時にこの基板6の上面周縁に位置するように形成し、
第1メタライズ層3aに対向する蓋7bの下面には第2
メタライズ層(図示せず)を形成し、セラミック基板6
に第1はんだ2aを介して固定された半導体素子4の上
面に対向する蓋7bの下面中央には第3メタライズ層
(図示せず)を形成した。第2及び第3メタライズ層は
それぞれ所定の位置に施されたNiめっきである。セラ
ミック基板6上面の第1メタライズ層3aに第2はんだ
2bを載せ、半導体素子4の上面に第3はんだ2cを載
せた状態で、第2メタライズ層が第2はんだ2bに対向
しかつ第3メタライズ層が第3はんだ2cに対向するよ
うに蓋7bをセラミック基板6に被せ、この状態でリフ
ロー炉で250℃に10秒間加熱することにより、蓋7
bをセラミック基板6及び半導体素子4に接着してパッ
ケージ1bを作製した。蓋7b、空所8、セラミック基
板6及び半導体素子4の寸法は上記比較例1と略同一で
あった。
<Comparative Examples 2, 3, 5 and 6> FIG. 6 and Table 1
As shown in Fig. 7, cover 7b with Kovar or C.
The ceramic substrate 6 was integrally formed of a u / W alloy, the ceramic substrate 6 was formed of a low temperature sintering material or Al 2 O 3 , and the above materials were combined to produce four types of semiconductor element packages 1b. The first metallization layer 3a is formed so as to be located on the peripheral edge of the upper surface of the ceramic substrate 6 at the same time as the production of the ceramic substrate 6,
On the lower surface of the lid 7b facing the first metallization layer 3a, a second
A metallization layer (not shown) is formed, and a ceramic substrate 6 is formed.
A third metallization layer (not shown) was formed at the center of the lower surface of the lid 7b facing the upper surface of the semiconductor element 4 fixed via the first solder 2a. The second and third metallized layers are Ni plating applied at predetermined positions. With the second solder 2b placed on the first metallization layer 3a on the upper surface of the ceramic substrate 6 and the third solder 2c placed on the upper surface of the semiconductor element 4, the second metallization layer faces the second solder 2b and the third metallization is performed. The lid 7b is covered on the ceramic substrate 6 so that the layer faces the third solder 2c, and in this state, the lid 7b is heated to 250 ° C. for 10 seconds to remove the lid 7b.
b was adhered to the ceramic substrate 6 and the semiconductor element 4 to prepare a package 1b. The dimensions of the lid 7b, the void 8, the ceramic substrate 6 and the semiconductor element 4 were substantially the same as those of the comparative example 1.

【0031】<比較試験と評価>実施例1〜29及び比
較例1〜6の半導体素子用パッケージの各構成部品の材
料と、実施例1〜29の半導体素子用パッケージの蓋本
体及び枠材の接着温度とを表1に示した。また実施例1
〜29及び比較例1〜6の半導体素子用パッケージの蓋
の反り(長さ40mmでの反りの平均値)、−40℃〜
125℃の温度サイクルをパッケージに1000回印加
した後の蓋とセラミック基板との接合強度、半導体素子
を3W発熱させたときの熱抵抗、及びパッケージの重量
(半導体素子を含む。)をそれぞれ測定し、その結果を
表2に示した。表2の温度サイクル後のパッケージ強度
において、Aは接合強度が良好であり、Bは接合強度が
普通であり、Cは接合強度が不良であることを示す。
<Comparative Test and Evaluation> The materials of the components of the semiconductor element packages of Examples 1 to 29 and Comparative Examples 1 to 6 and the lid body and the frame material of the semiconductor element packages of Examples 1 to 29 were evaluated. The adhesion temperature is shown in Table 1. Example 1
29, and the warpage of the lids of the semiconductor device packages of Comparative Examples 1 to 6 (average warpage at a length of 40 mm), −40 ° C.
The bonding strength between the lid and the ceramic substrate after 1000 cycles of the temperature of 125 ° C. was applied to the package, the thermal resistance when the semiconductor element was heated by 3 W, and the weight of the package (including the semiconductor element) were measured. The results are shown in Table 2. In the package strength after the temperature cycle in Table 2, A indicates that the joint strength is good, B indicates that the joint strength is normal, and C indicates that the joint strength is poor.

【0032】[0032]

【表1】 [Table 1]

【0033】[0033]

【表2】 [Table 2]

【0034】表1及び表2より明らかなように、実施例
1〜29のパッケージでは比較例1〜6のパッケージよ
り軽量であり、反りが少ないことが判った。蓋とセラミ
ック基板との接合強度もはんだへのストレスが少ないた
め良好であった。
As is clear from Tables 1 and 2, it was found that the packages of Examples 1 to 29 were lighter in weight and less warped than the packages of Comparative Examples 1 to 6. The joint strength between the lid and the ceramic substrate was also good because there was little stress on the solder.

【0035】[0035]

【発明の効果】以上述べたように、本発明によれば、蓋
本体が半導体素子の上面を覆い、蓋本体とは別部材によ
り形成されかつ上面が蓋本体の下面周縁に緩衝材を介し
て接着された枠材が半導体素子の側面を覆い、蓋本体と
枠材とセラミック基板蓋本体の熱膨張係数をそれぞれα
1とα2とα3とするとき、上記蓋本体と枠材とセラミッ
ク基板とをα1≦α2≦α3の関係を満たすように構成し
たので、半導体素子の高さに合わせるための蓋の内面の
機械加工が煩わしく加工工数が大幅に増大する従来の半
導体素子収納用パッケージと比較して、半導体素子との
高さを合わせるために枠材を機械加工したとしても僅か
な加工工数で済む。また蓋の側壁をなす枠材を蓋本体と
は別部材としたので、半導体素子に無理な力を加えずに
半導体素子をセラミック基板及び蓋本体に確実に固定し
た状態で空所に収容できる。
As described above, according to the present invention, the lid main body covers the upper surface of the semiconductor element, is formed of a member separate from the lid main body, and the upper surface of the lid main body is provided with a cushioning material on the lower peripheral edge thereof. The bonded frame material covers the side surface of the semiconductor element, and the thermal expansion coefficients of the lid body, the frame material, and the ceramic substrate lid body are respectively α
1 and α 2 and α 3 , the lid body, the frame member, and the ceramic substrate are configured to satisfy the relationship α 1 ≤α 2 ≤α 3 , so that the lid for adjusting to the height of the semiconductor element is used. Compared with the conventional package for semiconductor element storage, which requires complicated machining, the machining of the inner surface is complicated and the frame material can be machined to match the height of the semiconductor element. . Further, since the frame material forming the side wall of the lid is a member separate from the lid main body, the semiconductor element can be housed in the empty space in a state of being securely fixed to the ceramic substrate and the lid main body without applying an unreasonable force to the semiconductor element.

【0036】また蓋本体、枠材及びセラミック基板がこ
れらの熱膨張係数の間のα1≦α2≦α3という関係を満
たすことにより、半導体素子の発熱及び冷却の繰返しに
よるセラミック基板、蓋及び半導体素子間の各接着部に
発生するストレスを緩和することができ、上記各熱膨張
係数の僅かな相違により各接着部に発生するストレスも
縦弾性係数の小さい緩衝材が伸縮することにより低減す
ることができる。また緩衝材として比重の比較的小さい
Alを用いれば、本発明のパッケージを従来のパッケー
ジより軽くすることができる。更に蓋本体の上面にAl
又はAgにより形成されたヒートシンクを積層接着すれ
ば、半導体素子の発した熱が第3はんだ及び蓋本体を介
してヒートシンクからスムーズに放散されるので、半導
体素子の温度上昇を低減することができる。
Further, since the lid body, the frame material and the ceramic substrate satisfy the relationship of α 1 ≦ α 2 ≦ α 3 among these thermal expansion coefficients, the ceramic substrate, the lid and the ceramic substrate are repeatedly heated and cooled by the semiconductor element. The stress generated in each adhesive portion between semiconductor elements can be relieved, and the stress generated in each adhesive portion due to the slight difference in each thermal expansion coefficient is also reduced by expansion and contraction of the cushioning material having a small longitudinal elastic coefficient. be able to. Further, if Al having a relatively small specific gravity is used as the buffer material, the package of the present invention can be made lighter than the conventional package. On top of the lid body, Al
Alternatively, if a heat sink formed of Ag is laminated and adhered, the heat generated by the semiconductor element is smoothly dissipated from the heat sink via the third solder and the lid body, so that the temperature rise of the semiconductor element can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1〜6の半導体素子用パッケー
ジの要部断面図。
FIG. 1 is a cross-sectional view of essential parts of a semiconductor device package according to first to sixth embodiments of the present invention.

【図2】本発明の実施例7〜13の半導体素子用パッケ
ージの要部断面図。
FIG. 2 is a cross-sectional view of essential parts of semiconductor device packages of Examples 7 to 13 of the present invention.

【図3】本発明の実施例14〜16の半導体素子用パッ
ケージの要部断面図。
FIG. 3 is a cross-sectional view of essential parts of semiconductor device packages of Examples 14 to 16 of the present invention.

【図4】本発明の実施例17〜19の半導体素子用パッ
ケージの要部断面図。
FIG. 4 is a cross-sectional view of essential parts of semiconductor device packages of Examples 17 to 19 of the present invention.

【図5】比較例1の半導体素子用パッケージの要部断面
図。
5 is a cross-sectional view of a main part of a semiconductor device package of Comparative Example 1. FIG.

【図6】比較例2及び3の半導体素子用パッケージの要
部断面図。
FIG. 6 is a cross-sectional view of essential parts of semiconductor device packages of Comparative Examples 2 and 3.

【符号の説明】[Explanation of symbols]

10,40,50,80 半導体素子用パッケージ 11 第1はんだ 13 第3はんだ 14 半導体素子 16 セラミック基板 17,57 蓋 18,58 空所 19,59 蓋本体 21,61 第1メタライズ層 22,62 第2メタライズ層 23,63 第3メタライズ層 24,64 緩衝材 26,66 枠材 45,85 ヒートシンク 10, 40, 50, 80 Package for semiconductor element 11 First solder 13 Third solder 14 Semiconductor element 16 Ceramic substrate 17, 57 Lid 18, 58 Cavity 19, 59 Lid body 21, 61 First metallized layer 22, 62 2 metallized layer 23,63 third metallized layer 24,64 buffer material 26,66 frame material 45,85 heat sink

───────────────────────────────────────────────────── フロントページの続き (72)発明者 初鹿 昌文 埼玉県大宮市北袋町1丁目297番地 三菱 マテリアル株式会社総合研究所内 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masafumi Hatsuka 1-297 Kitabukurocho, Omiya City, Saitama Prefecture Mitsubishi Materials Research Institute

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 上面に半導体素子(14)が第1はんだ(11)
を介して固定されたセラミック基板(16)と、前記半導体
素子(14)を収容可能な空所(18,58)を有する蓋(17,57)と
を備え、前記蓋(17,57)を前記セラミック基板(16)の上
面周縁に接着することにより前記半導体素子(14)を収容
するように構成された半導体素子用パッケージにおい
て、 前記蓋(17,57)が前記半導体素子(14)の上面を覆う蓋本
体(19,59)と、 前記蓋本体(19,59)とは別部材により形成され上面が前
記蓋本体(19,59)の下面周縁に緩衝材(24,64)を介して接
着されかつ前記半導体素子(14)の側面を覆う枠材(26,6
6)とを有し、 前記蓋本体(19,59)と前記枠材(26,66)と前記セラミック
基板(16)の熱膨張係数をそれぞれα1とα2とα3とする
ときα1≦α2≦α3の関係を満たすことを特徴とする半
導体素子用パッケージ。
1. A semiconductor element (14) having a first solder (11) on the upper surface thereof.
A ceramic substrate (16) fixed via, and a lid (17,57) having a cavity (18,58) capable of accommodating the semiconductor element (14), the lid (17,57) In a semiconductor device package configured to accommodate the semiconductor device (14) by adhering to a peripheral edge of an upper surface of the ceramic substrate (16), the lids (17, 57) have an upper surface of the semiconductor device (14). And a lid body (19,59) for covering the lid body (19,59) and a top surface formed by a member separate from the lid body (19,59) via a cushioning material (24,64) around the lower edge of the lid body (19,59). A frame member (26, 6) which is adhered and covers the side surface of the semiconductor element (14).
6), and the coefficient of thermal expansion of the lid body (19, 59), the frame material (26, 66) and the ceramic substrate (16) are α 1 and α 2 and α 3 , respectively, α 1 A semiconductor device package characterized by satisfying a relationship of ≦ α 2 ≦ α 3 .
【請求項2】 熱膨張係数α1の蓋本体(19,59)がSi
C,AlN,低温焼結材料又はAl23により形成さ
れ、 熱膨張係数α2の枠材(26,66)がSiC,AlN,低温焼
結材料又はAl23により形成され、 熱膨張係数α3のセラミック基板(16)がAlN,低温焼
結材料又はAl23により形成され、 α1≦α2≦α3の関係を満たすように前記蓋本体(19,59)
と前記枠材(26,66)と前記セラミック基板(16)とが選択
された請求項1記載の半導体素子用パッケージ。
2. The lid body (19, 59) having a thermal expansion coefficient α 1 is made of Si.
C, AlN, low-temperature sintering material or Al 2 O 3 , frame material (26, 66) having a thermal expansion coefficient α 2 is formed of SiC, AlN, low-temperature sintering material or Al 2 O 3 , A ceramic substrate (16) having a coefficient α 3 is formed of AlN, a low temperature sintered material or Al 2 O 3, and the lid body (19, 59) is formed so as to satisfy the relationship of α 1 ≦ α 2 ≦ α 3.
The semiconductor device package according to claim 1, wherein the frame material (26, 66) and the ceramic substrate (16) are selected.
【請求項3】 緩衝材(24,64)がAl又はAgにより形
成された請求項1又は2記載の半導体素子用パッケー
ジ。
3. The semiconductor device package according to claim 1, wherein the buffer material (24, 64) is made of Al or Ag.
【請求項4】 セラミック基板(16)の上面周縁に第1メ
タライズ層(21,61)が形成され、 枠材(26,66)の下面に第2メタライズ層(22,62)が形成さ
れ、 前記枠材(26,66)が前記第2メタライズ層(22,62)と第3
はんだ(13)と前記第1メタライズ層(21,61)とを介して
前記セラミック基板(16)の上面周縁に接着された請求項
1ないし3いずれか記載の半導体素子用パッケージ。
4. A first metallization layer (21,61) is formed on a peripheral edge of an upper surface of the ceramic substrate (16), and a second metallization layer (22,62) is formed on a lower surface of the frame member (26,66). The frame material (26, 66) and the second metallization layer (22, 62) and the third
The semiconductor device package according to any one of claims 1 to 3, which is bonded to a peripheral edge of an upper surface of the ceramic substrate (16) via a solder (13) and the first metallized layer (21, 61).
【請求項5】 セラミック基板(16)の上面に第1はんだ
(11)を介して半導体素子(14)が固定され、 前記半導体素子(14)に対向する蓋本体(19,59)の下面に
第3メタライズ層(23,63)が形成され、 前記半導体素子(14)の上面が前記蓋本体(19,59)の下面
に第3はんだ(13)及び前記第3メタライズ層(23,63)を
介して接着された請求項1ないし4いずれか記載の半導
体素子用パッケージ。
5. The first solder on the upper surface of the ceramic substrate (16).
The semiconductor element (14) is fixed via (11), and a third metallization layer (23, 63) is formed on the lower surface of the lid body (19, 59) facing the semiconductor element (14). 5. The semiconductor according to claim 1, wherein an upper surface of the (14) is bonded to a lower surface of the lid body (19, 59) via a third solder (13) and the third metallized layer (23, 63). Device package.
【請求項6】 蓋本体(19,59)の上面にAl又はAgに
より形成されたヒートシンク(45,85)が積層接着された
請求項1ないし5いずれか記載の半導体素子用パッケー
ジ。
6. The package for a semiconductor device according to claim 1, wherein a heat sink (45, 85) formed of Al or Ag is laminated and adhered on the upper surface of the lid body (19, 59).
JP7242673A 1995-09-21 1995-09-21 Package for semiconductor element Withdrawn JPH0992748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7242673A JPH0992748A (en) 1995-09-21 1995-09-21 Package for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7242673A JPH0992748A (en) 1995-09-21 1995-09-21 Package for semiconductor element

Publications (1)

Publication Number Publication Date
JPH0992748A true JPH0992748A (en) 1997-04-04

Family

ID=17092544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7242673A Withdrawn JPH0992748A (en) 1995-09-21 1995-09-21 Package for semiconductor element

Country Status (1)

Country Link
JP (1) JPH0992748A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003243565A (en) * 2002-02-07 2003-08-29 Motorola Inc Packaged semiconductor device and its manufacturing method
GB2359927B (en) * 1998-12-21 2003-11-26 Intel Corp Windowed non-ceramic package having embedded frame
US6692993B2 (en) 1998-10-13 2004-02-17 Intel Corporation Windowed non-ceramic package having embedded frame
JP2018088443A (en) * 2016-11-28 2018-06-07 京セラ株式会社 Electronic element mount substrate and electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6692993B2 (en) 1998-10-13 2004-02-17 Intel Corporation Windowed non-ceramic package having embedded frame
US7026707B2 (en) 1998-10-13 2006-04-11 Intel Corporation Windowed package having embedded frame
US7223631B2 (en) 1998-10-13 2007-05-29 Intel Corporation Windowed package having embedded frame
GB2359927B (en) * 1998-12-21 2003-11-26 Intel Corp Windowed non-ceramic package having embedded frame
JP2003243565A (en) * 2002-02-07 2003-08-29 Motorola Inc Packaged semiconductor device and its manufacturing method
JP4653383B2 (en) * 2002-02-07 2011-03-16 フリースケール セミコンダクター インコーポレイテッド Packaged semiconductor device and manufacturing method thereof
JP2018088443A (en) * 2016-11-28 2018-06-07 京セラ株式会社 Electronic element mount substrate and electronic device

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