JPH0992572A - Chip capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip capacitor which is contrived in capacitance increase and lessened in size. SOLUTION: A pair of comb-shaped electrodes 13a and 13b are formed on an alumina board 11 making their teeth engage with each other, a dielectric layer 14 is formed on the comb-shaped electrodes 13a and 13b, and a pair of comb-shaped electrodes 15a and 15b possessed of teeth which are formed engaging with each other and overlapping those of the comb-shaped electrodes 13a and 13b are formed on the dielectric layer 14.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a high-capacity chip capacitor.

[0002]

2. Description of the Related Art Conventionally, for example, a chip capacitor manufactured by a screen printing method similar to a thick film chip resistor is known. FIG. 4 is a diagram showing a manufacturing process of a conventional chip capacitor. First, a conductive paste is printed on the alumina substrate 41 shown in FIG. 4A by a screen printing method and baked to form a rectangular lower electrode 42. Next, as shown in FIG. 4B, a dielectric paste is printed on the lower electrode 42 by a screen printing method and baked to form a dielectric layer 43. Next, as shown in FIG. 4C, a conductive paste is printed on the dielectric layer 43 by a screen printing method and baked to form a rectangular upper electrode 44. Next, as shown in FIG. 4D, a glass paste is printed so as to cover the upper electrode 44 and the like and baked to form an overcoat glass layer 45. In this way, the chip capacitor is manufactured. Here, in order to increase the capacitance of this chip capacitor, the lower electrode 42 and the upper electrode 43 are
By increasing the shape of the shape to increase the facing area between the lower electrode 42 and the upper electrode 43, or by forming the dielectric layer 43 thin to decrease the distance between the lower electrode 42 and the upper electrode 43. Has been done.

FIG. 5 is a diagram showing a conventional manufacturing process of a chip capacitor different from that of FIG. First, FIG.
As shown in FIG. 4, a pair of electrodes 52 and 53 are printed on the alumina substrate 55 with the inter-electrode gap 54 interposed therebetween by the screen printing method and fired in the same manner as described with reference to FIG. next,
As shown in FIG. 5B, a dielectric layer 55 is printed on the pair of electrodes 52, 53 and baked. Next, as shown in FIG. 5C, the overcoat glass layer 5 is formed on the dielectric layer 55.
Print 6 and fire. In this way, the chip capacitor is manufactured. Here, in order to increase the capacity of the chip capacitor in the process of manufacturing the chip capacitor, as shown in FIG.
By printing the pair of electrodes 52 and 53 a number of times in (a), the portion of the dielectric layer 55 formed inside the inter-electrode gap 54 may be thickened. In addition, the width of the inter-electrode gap 54 may be reduced, or the inter-electrode gap 5 may be reduced.
The length of 4 may be increased to increase the capacity.

The chip capacitor manufactured by the screen printing method described above is, for example, compared with a multilayer capacitor in which a plurality of green sheets are prepared, electrodes are formed on each green sheet, and these green sheets are laminated and integrated with each other. There are advantages that the process is simple and the manufacturing time is short.

[0005]

However, the above-mentioned FIG.
In the structure of the chip capacitor shown in (1), if the lower electrode 42 and the upper electrode 44 are formed in a large shape to increase the capacitance of the capacitor, the shape of the chip capacitor becomes large. Further, when the dielectric layer 43 is formed thin to increase the capacitance, the withstand voltage of the capacitor decreases.

When trimming is performed to adjust the capacity of the chip capacitor, the lower electrode 4
2. Since the area of the upper electrode 44 is rectangular and large, it is not suitable for capacitance adjustment. On the other hand, in the structure of the chip capacitor shown in FIG. 5, the electrodes 52 and 54 can be printed many times to increase the capacitor capacity, but the capacity does not increase much in spite of printing many times, and when printing many times, the electrode capacity is increased. There is a problem that the conductor resistance value of 52, 54 becomes large, and therefore the queue (Q) becomes worse. Further, if the width of the interelectrode gap 54 is narrowed to increase the capacitance, the characteristics of the capacitor may become unstable and the withstand voltage of the capacitor also decreases. On the other hand, if the length of the interelectrode gap 54 is increased to increase the capacitance, there is a problem that the shape of the chip capacitor becomes large.

In view of the above circumstances, it is an object of the present invention to provide a chip capacitor having an increased capacity and a reduced size.

[0008]

A first chip capacitor according to the present invention which achieves the above object, comprises: (1) a pair of first comb-shaped electrodes formed on a first plane and having indented teeth. 2) Teeth formed on the second plane where the dielectric layer is sandwiched between the pair of first comb-shaped electrodes are formed at positions where the teeth overlap the teeth of the pair of first comb-shaped electrodes. It is characterized in that it is provided with a pair of second comb-shaped electrodes which are mutually intricate.

Further, the second chip capacitor of the present invention which achieves the above object is (1) a pair of comb-shaped electrodes formed on the first plane and having intricate teeth. (2) The pair of comb-shaped electrodes. And a pair of flat plate electrodes facing each other with a predetermined inter-electrode gap interposed therebetween, which is formed on a second plane having a dielectric layer sandwiched therebetween.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a cross-sectional view (a) of an embodiment of a first chip capacitor of the present invention, and a plan view (b) of a comb-shaped electrode formed on the first layer of the chip capacitor,
It is a figure which shows the top view (c) of the comb-shaped electrode formed in the 2nd layer.

A dielectric layer 12 is formed on an alumina substrate 11 of the chip capacitor shown in FIG. 1 (a). On the dielectric layer 12, a pair of comb-shaped electrodes 13a and 13b of the first layer shown in FIG. 1B having teeth are formed with an interelectrode gap 13c interposed therebetween. A dielectric layer 14 is formed on the pair of comb electrodes 13a and 13b. Further, the pair of comb-shaped electrodes 15a of the second layer shown in FIG. 1C, in which the teeth are intertwined with each other, are formed on the dielectric layer 14 at the positions where the teeth overlap the teeth of the pair of comb-shaped electrodes 13a and 13b. , 15b are formed so as to sandwich the interelectrode gap 15c. Furthermore, a pair of comb-shaped electrodes 15a and 15b
A dielectric layer 16 is formed on top. A trimming groove 17 is formed from the dielectric layer 16 of the chip capacitor thus formed to a part of the alumina substrate 11. By trimming the trimming groove 17, the capacitance of the chip capacitor is adjusted to a desired value.

In the chip capacitor of this embodiment, the teeth of the pair of comb-shaped electrodes 13a and 13b of the first layer are sandwiched between the teeth of the second-layer comb-shaped electrode 15a,
Since the teeth of 15b are overlapped, the portions of the comb-shaped electrodes 13a, 13b and the comb-shaped electrodes 15a, 15b that face each other are large, and thus the capacitance of the capacitor is large. Furthermore, the capacitance of the inter-electrode gap 13c of the comb-shaped electrodes 13a and 13b and the capacitance of the inter-electrode gap 15c of the comb-shaped electrodes 15a and 15b are also added, so that the capacitance of the chip capacitor of this embodiment is extremely large.

In addition, a pair of comb-shaped electrodes 13a,
13b, a pair of comb-shaped electrodes 15a and 15b are formed on the second layer, and therefore the chip has the same shape as the shape of the chip capacitor of the present embodiment, and the pair of comb-shaped electrodes is formed only on the same layer. Compared with a capacitor, the electrode width (conductor width) of each of the comb-shaped electrodes 13a and 13b and the comb-shaped electrodes 15a and 15b is large, so that the resistance value of the conductor is small and the queue of the capacitor is improved. Further, since the inter-electrode gap formed by sandwiching the pair of comb-shaped electrodes is large, the characteristics are stable and the withstand voltage is increased.

Further, by trimming the tooth portions of the comb electrodes 13a, 13b and the comb electrodes 15a, 15b, a large electrode portion can be easily cut, and quick adjustment can be performed over a wide capacitance range. In the present embodiment,
Since a part of the alumina substrate 11 is trimmed, for example, compared to a case where the upper electrode and the lower electrode are laminated and only the upper electrode is trimmed, complicated adjustment for trimming is not necessary and the capacitor capacity is easy. Moreover, it can be changed quickly.

FIG. 2 is a diagram showing a manufacturing process of the chip capacitor shown in FIG. First, a dielectric paste is printed on the alumina substrate 11 shown in FIG. 2A by screen printing and baked to form a dielectric layer 12. Next, FIG.
As shown in (b), the alumina substrate 11 and the dielectric layer 12
A conductor paste is printed thereon by a screen printing method and baked to form the first-layer comb-shaped electrodes 13a and 13b.

Next, as shown in FIG. 2C, a dielectric paste is printed on the comb electrodes 13a and 13b by a screen printing method and baked to form a dielectric layer 14. Next, as shown in FIG. 2D, the comb-shaped electrodes 13a, 13
b, the second layer comb-shaped electrode 15 having teeth that overlap the teeth of the comb-shaped electrodes 13a and 13b by printing a conductive paste on the dielectric layer 14 by screen printing and baking.
a and 15b are formed.

Next, as shown in FIG. 2E, a dielectric paste is printed on the comb-shaped electrodes 15a and 15b and the dielectric layer 14 by a screen printing method and baked to form a dielectric layer 16. Further, trimming is performed for fine adjustment of the capacitor capacity. Here, the trimming groove 17 is formed from the dielectric layer 16 to a part of the alumina substrate 11 as shown in FIG. In this way, the chip capacitor is manufactured.

FIG. 3 is a plan view of the parallel electrodes formed on the second layer of one embodiment of the second chip capacitor of the present invention. The chip capacitor of this embodiment is different from the chip capacitor shown in FIG. 1 in that the pair of comb-shaped electrodes 1 shown in FIG.
5a and 15b are a pair of parallel electrodes 35a and 3 shown in FIG.
The difference is that it is replaced with 5b.

A pair of parallel electrodes 35a and 35b shown in FIG.
Are formed to face each other with a predetermined interelectrode gap 35c interposed therebetween. In this way, since the pair of parallel electrodes 35a and 35b of the second layer are formed so as to sandwich the dielectric layer 14 so as to overlap the comb electrodes 13a and 13b of the first layer,
The electrode areas of the comb electrodes 13a, 13b and the parallel electrodes 35a, 35b facing each other are large, and therefore the capacitance of the capacitor is large. Furthermore, the comb-shaped electrodes 13a and 13b
Since the capacitance of the inter-electrode gap 13c and the capacitance of the parallel electrodes 35a and 35b between the electrodes 35c are also added, the capacitance of the chip capacitor is further increased.

[0020]

As described above, according to the chip capacitor of the present invention, (1) a large capacitor capacity can be easily obtained. (2) Since the number of times of printing is small and the process is simplified, the production time is short, mass productivity is excellent, and cost is reduced. (3) A chip capacitor having a small outer dimension including the thickness dimension can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view (a) of an embodiment of a first chip capacitor of the present invention, a plan view (b) of a comb-shaped electrode formed on the first layer of the chip capacitor, and a second layer. It is a figure which shows the top view (c) of the comb-shaped electrode formed in the eye.

FIG. 2 is a diagram showing a manufacturing process of the chip capacitor shown in FIG.

FIG. 3 is a plan view of parallel electrodes formed on a second layer of one embodiment of the second chip capacitor of the present invention.

FIG. 4 is a diagram showing a manufacturing process of a conventional chip capacitor.

FIG. 5 is a diagram showing a conventional manufacturing process of a chip capacitor different from that of FIG. 4;

[Explanation of symbols]

 11 Alumina substrate 12, 14, 16 Dielectric layer 13a, 13b, 15a, 15b Comb-shaped electrode 13c, 15c, 35c Inter-electrode gap 17 Trimming groove 35a, 35b Parallel electrode

Claims (2)

[Claims] 1. A second plane formed on a first plane and having a dielectric layer sandwiched between a pair of first comb-shaped electrodes having indented teeth and a pair of the first comb-shaped electrodes. A chip capacitor, comprising: a pair of second comb-shaped electrodes in which the teeth are intertwined with each other, the teeth being formed at positions where the teeth overlap the teeth of the pair of first comb-shaped electrodes. 2. A pair of comb-shaped electrodes formed on a first plane and having teeth intertwined with each other, and a pair of comb-shaped electrodes formed on a second plane with a dielectric layer sandwiched between the pair of comb-shaped electrodes. And a pair of flat plate electrodes facing each other with a predetermined gap between the electrodes interposed therebetween.