JPH0991974A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure the operation over a wide potential range by providing a clock gate type CMOS logic gate on a concerned bit line in a current detection read circuit. SOLUTION: An NMOS transistor NM1 feeds a current from a current supply means through a resistor means 18 to the node BB0 of bit lines Bit0-Bit31 in a memory cell array 10. A clock gate type CMOS logic circuit 17 applies a precharge voltage to the bit line. The clock signal of clock gate type CMOS logic circuit 17 can deal with both 'H' and 'L'. When several inverters are provided additionally for the clock signal to constitute a delay circuit, the operating interval of CMOS logic circuit can be set arbitrarily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a read-only memory or a non-volatile semiconductor memory device suitable for operating a wide range of power supply voltage, for example, 0.9 to 6.0V.

[0002]

2. Description of the Related Art As a read circuit for a read-only or non-volatile semiconductor memory device, a discharge-type read circuit, a differential-type comparison circuit, a current detection type circuit, etc. are used.

[0003]

In the discharge type read circuit, the bit line is charged to the precharge period limit voltage (clamp voltage) and the threshold value of the memory MOS transistor selected in the non-precharge (data output) period. Depending on the level of the voltage, whether to discharge or hold the charge charged in the parasitic capacitance of the bit line is determined. The read operation is performed by converting the bit line voltage into a logic level (the above clamp voltage and ground potential) by a logic gate circuit. The conventional voltage level conversion circuit for converting the output of the logic gate circuit into the power supply voltage level is not sufficient in terms of constant voltage operation and circuit scale.

The differential comparison circuit controls a bit line with respect to a reference voltage by using a differential amplifier, and the current detection circuit changes a voltage level due to a bit line current flowing through a MOS transistor resistance to a voltage level. These are converted to logic levels by a conversion circuit. However, in the low power supply voltage range, these are designed operating points (bias voltage, current, Logic threshold voltage etc.)
It cannot be said that the circuit system is suitable for lowering the voltage because stable operation and characteristics cannot be satisfied. For example, in a differential amplifier, at least three load, drive, and current source MOS transistors are connected in series between a power supply and ground.
It is difficult to secure the design operating point over a wide power supply voltage range. In particular, in the low voltage range of 1.5 V or less, since the MOS operates in the tailing region, it is difficult to control the circuit design constants such as the logical threshold voltage depending on the channel ratio of the PMOS and NMOS, so that the design tuning is difficult. There's a problem. Further, in the differential type comparison circuit and the current detection type circuit system, the operation speed is high because of current driving, but in general, there is a problem that the bias current flows and the current consumption is large.
Further, in the current detection type circuit system, it is necessary to increase the current drive capability of the current supply and the resistance means from the viewpoint of speeding up, but when the voltage becomes low, the drain current of the memory MOS becomes small (memory MOS. Is equivalent to a large equivalent resistance), so "1" is read (threshold voltage MVth of memory MOS MVth
(Low), the voltage level of the output terminal increased and there was a problem that normal reading operation could not be performed. That is, the memory M
Since the resistance value of OS increases, the output voltage determined by the voltage dividing ratio of the equivalent resistance of the current supply and resistance means and the memory MOS equivalent resistance increases. Therefore, if the current supply and the current capability of the resistance means are reduced, this time, when reading "0" (the threshold voltage MVth of the memory MOS is high), the reading time is obtained by the charge sharing of the charges between the bit line and the output terminal capacitance. However, there was a problem of increasing the number of readings and causing misreading.

The present invention solves the above problems and provides a read-only or non-volatile semiconductor memory that can operate over a wide power supply voltage range and is suitable for low power consumption and size reduction. .

[0006]

As means for solving the above problems, in a memory device including at least a current detecting circuit including a constant current circuit means and a current applying switch means, and a level converting means, a memory MOS has a "1". In the read state (low threshold voltage MVth of the memory MOS), in order to operate as low a voltage as possible, the precharge voltage of the bit line is at least higher than the threshold voltage MVth of the memory MOS. It is necessary to make it as low as possible. For this purpose, the resistance value of the constant current circuit may be increased. However, if the resistance value is too large, the bit line precharge capability is lowered, so that the memory MOS reads "0" (the threshold voltage MVth of the memory MOS. High), the charge sharing of the charge between the bit line and the output terminal lowers the potential of the precharged bit line, which causes a problem of increased read time and erroneous read operation. According to the present invention, a CMOS logic gate having a clocked gate structure is provided on a bit line, and the charge share can be reduced by precharging the bit line during the operation of the CMOS logic gate, which enables low voltage operation and high speed operation. It becomes possible to operate. Further, the period during which the CMOS logic gate having the clocked gate structure operates can be set arbitrarily, and the memory MO
S reads out "1" (threshold voltage MV of memory MOS
Needless to say, low voltage operation and high-speed operation are possible even when (th is low). Further, conventionally, a DMOS is often used in a signal line precharge circuit to clamp and precharge a power supply voltage.
When using DMOS, there is a problem that it is difficult to control the characteristics. In the present invention, since the Vlt characteristic of the CMOS logic circuit having the clocked gate structure is used for the precharge method, stable operation can be expected, and the photomask for DMOS and ion implantation are unnecessary. In producing a product, there are merits such as cost reduction and manufacturing process reduction.

The threshold voltage MVth (hereinafter referred to as MVth) of the memory MOS is a voltage required to turn on the memory MOS. The read circuit status is MVth
When is low, it is in the "1" read state, and when MVth is high, it is in the "0" read state. The "1" read state is a case where the memory MOS is ON, and the "0" read state is a state where the memory MOS is OFF. When reading "1", low voltage operation,
Also, in order to operate at high speed, the resistance of the constant current circuit may be increased. However, increasing the resistance of the constant current circuit, conversely, reduces the ability to precharge the bit line at the time of reading "0". For this reason, there is a problem that low voltage operation and high speed operation become difficult due to the influence of charge sharing generated by the difference between the output terminal charge of the voltage level conversion circuit and the charge of the bit line, resulting in erroneous reading. In the current detection type read circuit according to the present invention, not only the output terminal of the voltage level conversion circuit is precharged but also the bit line is provided with a clocked gate type CMOS logic gate,
Since the bit line is also precharged, the memory MOS
The charge share at the time of reading "0" (MVth = high) can be reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows an overall block configuration of a 4 k word.times.8 bit capacity nonvolatile memory (hereinafter referred to as ROM) of the present invention. In FIG. 5, the ROM is composed of a memory cell array 10, a word address (X) decoder 11, a bit line address (Y) decoder 12, a Y selector circuit block 13, a sense amplifier circuit block 14, and a data buffer block 15. The lower address signal lines AD0 to AD4 of the 12 address signal lines AD0 to AD11 are input to the Y decoder 12, and the upper address signal lines AD5 to AD11 are input to the X decoder 11. The 8-bit data output lines DB0 to DB7 are connected to the output clock PIL from the data buffer block 15.
Is output at the timing of. Further, the X decoder 11 outputs 128 word line signals WS0 to WS127 in synchronization with the rise of the basic clock PI2. A memory element group connected to the active word line signal WSn is selected, and the stored data of the memory element group is selected from 32 to 1 for each data output by the Y decoder 12 and the Y selector circuit block 13. Is selected and the data output line D
The memory cell array 10 output to Bn has 128 rows (W
S0 to WS127) × 8 columns (# 1 to # 8) of memory cell blocks 16. As shown in FIG. 6, each memory cell block 16 is composed of 32 memory MOS transistors FM0 to FM31. The memory cell block 16 has a horizontal ROM configuration. Memory MOS
In FM0 to FM31, the source is grounded to the electrodes, the drain electrodes are connected to the bit lines Bit0 to Bit31, the gate electrodes are commonly connected, and the word line signal WSn is at the active level (“H” level when the memory MOS is NMOS). Will be selected. Memory MOS FM0
Since the data of "0" and "1" is programmed in the FM 31, the threshold voltage MVth of the memory MOS is set high (high enough not to turn on even when the word line is at "H" level) depending on whether or not normal ion implantation is performed. Or, make it low (low enough to turn on even when the word line is at “H” level).

FIG. 1 shows an embodiment of a ROM current detection type read circuit. In this embodiment, in addition to the memory cell array 10 and the Y selector circuit block 13, a current supply unit and a resistance unit (hereinafter referred to as a current source) 18, a current from the current source 18 is supplied to the bit lines Bit0 to Bit31 and a node BB0. NMOS transistor NM forming means for
1, a voltage level conversion circuit 19 for converting a voltage change at the output terminal SO into a logic level, and a CMOS logic circuit 17 having a clocked gate structure which constitutes a means for applying a precharge voltage to a bit line.

Next, the operation of the read circuit will be described with reference to the time chart of FIG. First, during the precharge period (PI2 = "H", PI2N = "L"), NM
The OSNM1 is turned off, and the node BB0 and the output terminal SO are charged to the power supply voltage Vcc. At this time, the CMOS logic circuit 17 having the clocked gate structure has PI2N =
It is turned on only during the "L" period, and the bit line is set to the logic threshold value of the CMOS logic circuit 17 of the clocked gate structure (hereinafter referred to as Vl
Precharge up to t). After the end of the precharge period (PI2 = “L”, PI2N = “H”), the NMOS transistor NM1 is turned on, the CMOS logic circuit having the clocked gate structure is turned off, and the threshold value of the selected memory MOS is turned on. Whether the current flows through the bit line or not depends on the level of the voltage MVth. M above
When Vth is low (when "1" is read), the current source 18 to the NMOS switch in the Y selector circuit block 13 and the memory M
A direct current path is formed through the OS to the ground potential, and the current at the current source 18 causes the potential at the output terminal SO to drop. This voltage change is converted into a logic level by the voltage level conversion circuit 19. In this case, since it is driven by a load current, it has a feature of high-speed reading. On the other hand, when the MVth is high (when "0" is read), a DC path cannot be made and the potential of the output terminal SO is finally held at "H" level, but the precharge period ends (PI2 = "L"). Immediately after (switching), the parasitic capacitance C2 of the output terminal, the equivalent parasitic capacitance C1 of the node BB0
Charge sharing occurs between the two, and the potential drops temporarily. In this embodiment, a CMOS having a clocked gate structure is used.
The precharge function of the logic gate 17 can reduce the potential drop due to the charge sharing. Also, the period during which this precharge function works is only the period of PI2N = L, and there is an effect of accelerating the discharge time at the time of "1" read.

FIG. 2 shows the structure of a CMOS logic circuit 1 having a clocked gate structure. C of this clocked gate structure
In the MOS logic circuit, the input terminal and the output terminal are connected to the bit line (BB0), and the inverter 2 is provided between the clock signal lines PI2 and PI2N input to the NMOS side. Therefore, while the PI2N is "L", the CMOS circuit 1 having the clocked gate structure is turned on, so that the input terminal and the output terminal are short-circuited and the "H" period is turned off.
Therefore, the input terminal and the output terminal are opened. FIG. 3 shows another embodiment of a CMOS logic circuit having a clocked gate structure, which is a signal PI2 opposite to the input signal PI2N shown in FIG.
Shows the case of using. At this time, since the clock signal input to the NMOS side of the CMOS logic circuit 1 having the clocked gate structure is PI2 “H”, the polarity is reversed between the clock signals PI2N and PI2 input to the PMOS side. Inverter 2 is provided.

As described above, as shown in FIGS. 2 and 3, the clock signal of the CMOS logic circuit having the clocked gate structure can correspond to either "H" or "L".

FIG. 4 is a diagram in which several inverters are added to the clock signal of the CMOS logic circuit 1 having the clocked gate structure. Clocked gate structure CMOS circuit 1
Clock signal lines PI2 and PI2 input to the NMOS side of the
An odd number of inverters are provided between N and PMOS
The delay circuit is configured by providing an even number of inverters between the clock signal lines PI2N and PI2 input to the side, and the operation period of the CMOS logic circuit 1 having the clocked gate structure can be set arbitrarily.

By incorporating the semiconductor memory device having the above configuration in a microcomputer, a microcomputer capable of low-voltage operation and high-speed operation can be realized.

[0015]

As described above, according to the present invention,
In the current detection type circuit system, a precharge voltage applying circuit is provided, and a CMOS logic circuit having a clocked gate structure can be used to arbitrarily set the period during which the precharge function operates, thereby reducing the influence of charge sharing. Of course, low voltage operation and high speed operation are possible. Also, since the clamp DMOS that is often used in the conventional precharge circuit is not used, stable precharge can be performed, and there are advantages such as cost reduction and product manufacturing process reduction. is there.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a read circuit in a semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a configuration of a CMOS logic circuit having a clocked gate structure.

FIG. 3 is a diagram showing another configuration of a CMOS logic circuit having a clocked gate structure.

FIG. 4 is a diagram showing another configuration of a CMOS logic circuit having a clocked gate structure.

FIG. 5 is a diagram showing an overall configuration of a semiconductor memory device of the present invention.

6 is a diagram showing a configuration of a memory cell block 16 in FIG.

FIG. 7 is a time chart explaining the operation of the read circuit in the semiconductor memory device of the present invention.

[Explanation of symbols]

10 ... Memory cell array, 11 ... Word address (X)
Decoder, 12 ... Bit line address (Y) decoder, 13
... Y selector circuit block, 14 ... Sense amplifier circuit block, 15 ... Data buffer block, 16 ... Memory cell block, 17 ... CMOS logic circuit, Vcc ... Logic power supply voltage, FM0-FM31 ... Memory MOS, PM1-
PM6, PM30 to PM37 ... PMOS transistor,
NM1 to NM10 ... NMOS transistors.

Claims (3)

[Claims] 1. A current source for supplying a current to a bit line of a memory cell array, a switching element for switching a current supply from the current source to the bit line, and a voltage at an output point on a current path by the bit line current. A read circuit comprising a voltage level conversion circuit for converting a change into a logic level and a logic gate circuit having an input terminal and an output terminal connected to the bit line and having means for short-circuiting and opening the input terminal and the output terminal. Equipped semiconductor memory device. 2. The CMO having a clocked gate structure according to claim 1, wherein the logic gate circuit is a CMO having a clocked gate structure.
A semiconductor memory device comprising an S logic gate. 3. A microcomputer incorporating the semiconductor memory device according to claim 1.