JPH098666A - Encoder/decoder circuit - Google Patents

Abstract

PURPOSE: To provide an encoder/decoder circuit which can be applied at the time of n-phase PSK(phase shift keying) with small scale circuit configuration. CONSTITUTION: This encoder circuit is composed of a line selector 2 of four bits as a multi-bit line selective adding means for outputting an output data signal, for which one of data signals to be inputted at the time of n-phase PSK and a signal switching and selecting any one of delayed data signals delaying the other one of these data signals are synthetically added, as an output encoded signal and a one-bit delay circuit 1 as a delay means for delaying the other output data signal and generating plural delayed data signals. When this encoder circuit is provided with a subtracting means (not shown in the figure) for subtracting any one of respective delayed data signals selected by the line selector 2 from the output data signal, it can be constituted as the decoder circuit (the encoder/decoder circuit).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding / decoding circuit used at the time of n-phase PSK (Phase Shift Keying).
The present invention relates to an encoding / decoding circuit used to remove phase uncertainty when demodulating K.

[0002]

2. Description of the Related Art Conventionally, as a class of encoding / decoding circuits used in this type of n-phase PSK, for example, Japanese Patent Laid-Open No. 60-
The decoding circuit disclosed in Japanese Patent No. 51048 is disclosed in QPSK.
(1/4 phase shift keying / Quaternary-PS
When used for K), there is an uncertainty of 90 degrees in the phase at the time of demodulation. Therefore, in such a case, an encoding / decoding circuit is used to remove the phase uncertainty during demodulation of QPSK.

FIG. 7 shows a basic structure of a decoding circuit having a Gray code differential conversion function disclosed in Japanese Patent Laid-Open No. 60-51048 as a related technology of such an encoding / decoding circuit. It is a block diagram. In this decoding circuit, the I signal and the Q signal are input to a gray conversion circuit 7 composed of an EX-OR circuit, and then one of them is delayed by a delay flip-flop (F / F) 8 _I , 8 _Q. , The other is directly input to the differential conversion circuit 9. The differential conversion circuit 9 subtracts the data of the flip-flops 8 _I and 8 _{Q from} the data of the gray conversion circuit 7, encodes the data, and transmits the data to the gray conversion circuit 10 having the same configuration as the gray conversion circuit 7.
The data decoded by the gray conversion circuit 10 is output as a conversion output.

More specifically, the I and Q signals to be decoded here are converted from gray code to pure binary code by a gray conversion circuit 7 composed of one EX-OR circuit 11 as shown in FIG. Is converted to. The converted data is input to the delay flip-flops 8 _I and 8 _Q and delayed by 1 bit. The data converted into the pure binary code and the data delayed by 1 bit are input to the differential conversion circuit 9, where the delay binary flip-flop 8 _{I is} converted from the pure binary code data obtained by the gray conversion circuit 7. , 8 _Q output data is subtracted and encoded. Since the encoded data is a pure binary code, it needs to be replaced with a Gray code depending on the characteristics of the bit error rate. Therefore, the gray conversion circuit 10 again converts the pure binary code into the gray code to obtain the converted output.

Incidentally, FIG. 9 is a table exemplifying the correspondence of data processing in this decoding circuit. Here, 1
0 in the decimal number is 00 for the pure binary code, 00 for the Gray code, 1 for the decimal number is 01 for the pure binary code, 01 for Gray code, and 2 for the decimal number is 10 for the pure binary code. , The Gray code is 11, and the decimal number 3 is 11, which is the pure binary code 11 and the Gray code is 10.

On the other hand, FIG. 10 is a block diagram showing a basic configuration of a conventional coding circuit having a Gray code full addition function as a related technology of the coding / decoding circuit.

The encoding circuit here is obtained by replacing the subtraction function in the decoding circuit shown in FIG. 7 with an addition function, and the operation is basically the same. That is, the data I and the data Q to be encoded are the gray code / pure binary code conversion circuit 3
The Gray code is converted to a pure binary code. However, the correspondence between the pure binary code and the Gray code here is similarly performed according to the relationship shown in FIG. Converted data I ₂ , Q
₂ (X element) is a binary full adder circuit 5 between the data A _m-1 and B _m-1 (Y element) delayed by the 1-bit delay circuit 1.
Is added by the binary full adder circuit 5 to obtain the data A2,
B2 is generated and output. Data A2 and B2 here
One of them is delayed by the 1-bit delay circuit 1 and the previous data A
_m-1 and B _m-1 .

FIG. 12 shows a pure binary code truth table in the code generation circuit 4 including the binary full addition circuit 5 and the loop of the 1-bit delay circuit 1.

Further, a pure binary code / Gray code conversion circuit 6
Then, the other of the data A2 and B2 from the binary full adder circuit 5 is converted from a pure binary code to a Gray code and used as the conversion output of the data A and B. By this conversion, the gray code truth table in the gray code / pure binary code conversion circuit 3 and the binary full addition circuit 5 shown in FIG. 11 can be obtained from the pure binary code truth table shown in FIG. Become.

[0010]

When the above-mentioned encoding / decoding circuit is used at the time of n-phase PSK, gray code / pure 2
Binary code conversion circuit, pure binary code / Gray code conversion circuit, 2
Since a full adder circuit, a delay circuit, an adder / subtractor circuit, etc. are required, there is a problem that the circuit scale becomes large and complicated.

The present invention has been made to solve such a problem, and its technical problem is to provide an encoding / decoding circuit applicable to n-phase PSK with a small circuit configuration. It is in.

[0012]

According to the present invention, n-phase P
In many cases, one of the data signals input at the time of SK and the one obtained by selectively switching and selecting a plurality of delayed data signals in which the other of the data signals is delayed and distributed are output as an output coded signal. An encoding circuit including a bit line selective addition means and a delay means for generating a plurality of delayed data signals can be obtained.

In this encoding circuit, the delay means delays one of the output data signals to generate a plurality of delayed data signals, or the delay means delays the other of the data signals to generate a plurality of delayed data signals. Producing is preferred.

On the other hand, according to the present invention, any one of the encoding circuits described above, and subtraction means for subtracting, from the output data signal, one of the plurality of delayed data signals selected by the multi-bit line selective addition means. A decoding circuit comprising is obtained.

On the other hand, according to the present invention, in the above decoding circuit, the multi-bit line selective addition means and the delay means are operated during encoding and decoding, and the subtraction means is operated only during the decoding. A decoding / decoding circuit is obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The coding / decoding circuit of the present invention will be described in detail below with reference to the accompanying drawings.

First, the basic structure of the encoding / decoding circuit of the present invention will be briefly described. This encoding / decoding circuit
An output data signal obtained by combining and adding one of the data signals input at the time of n-phase PSK and a signal obtained by selectively switching and selecting a plurality of delayed data signals in which the other of the data signals is delayed is output as an output coded signal. The multi-bit line selective addition means, the delay means for generating a plurality of delayed data signals, and the subtraction means for subtracting the output data signal from the plurality of delayed data signals selected by the multi-bit line selective addition means. The multi-bit line selecting / adding means and the delay means are operated at the time of encoding and decoding, and the subtracting means is operated only at the time of decoding.

Here, the plurality of delayed data signals obtained by the delay means can be generated by delaying one of the output data signals or delaying the other of the data signals.

That is, this encoding / decoding circuit can be regarded as a configuration including an encoding circuit and a decoding circuit independently, and the encoding circuit is a portion composed of multi-bit line selective addition means and delay means. The decoding circuit is the whole part in which the delay means is added to the multi-bit line selective addition means and the delay means.

Therefore, first, with reference to the block diagram shown in FIG. 1, an encoding circuit according to an embodiment of the present invention will be described.

This encoding circuit comprises a 1-bit delay circuit 1 as a delay means for delaying one of the output data signals to generate each delayed data signal, and a 4-bit type line selector as a multi-bit line selection / addition means. 2 and. The 1-bit delay circuit 1 is the same as the delay flip-flop described in the prior art, and the line selector 2 is a 4-bit line selector and is a power of 2 0,
The output data can be determined by switching control based on the power of 2.

Therefore, in the following, refer to the gray code truth table shown in FIG. 11 for the process until the truth table as shown in FIG. 2 showing the correspondence between the input and the output in this coding circuit is created. And explain.

First, the input data (I, Q) is (0,0).
Suppose that. As the first mode, the output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (0, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (0, 0). As a second mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-1, Bn-1) =
If (0, 1), the output data (An, Bn) is (An, Bn) = (0, 1) from the Gray code truth table. In a third mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-
1, Bn−1) = (1,1), the output data (An, Bn) is (An, Bn) = from the Gray code truth table.
It becomes (1,1). As the fourth mode, output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (1, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (1,0).

Accordingly, the output data An, Bn and the output data An-1, Bn one bit before are output from these four patterns.
-1 has a relationship of (An, Bn) = (An-1, Bn-1).

Next, the input data (I, Q) is (0,1).
Suppose that. As the first mode, the output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (0, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (0, 1). As a second mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-1, Bn-1) =
If (0, 1), the output data (An, Bn) is (An, Bn) = (1, 1) from the gray code truth table. In a third mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-
1, Bn−1) = (1,1), the output data (An, Bn) is (An, Bn) = from the Gray code truth table.
It becomes (1, 0). As the fourth mode, output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (1, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (0, 0).

Therefore, the output data An, Bn and the output data An-1, Bn one bit before are output from these four patterns.
-1 means (An, Bn) = (Bn-1, A'n-1)
Relationship.

Further, the input data (I, Q) is (1,0).
Suppose that. As the first mode, the output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (0, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (1,0). As a second mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-1, Bn-1) =
If (0, 1), the output data (An, Bn) is (An, Bn) = (0, 0) from the gray code truth table. In a third mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-
1, Bn−1) = (1,1), the output data (An, Bn) is (An, Bn) = from the Gray code truth table.
It becomes (0, 1). As the fourth mode, output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (1, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (1,1).

Therefore, the output data An, Bn and the output data An-1, Bn one bit before are output from these four patterns.
-1 means (An, Bn) = (B'n-1, An-1)
Relationship.

In addition, the input data (I, Q) is (1,
Assume the case of 1). As a first mode, output data (An-1, Bn 1 bit before output data An, Bn
-1) is (An-1, Bn-1) = (0, 0), output data (An, Bn) from the gray code truth table.
Is (An, Bn) = (1,1). As a second mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-1, Bn-1) =
If (0, 1), the output data (An, Bn) becomes (An, Bn) = (1, 0) from the gray code truth table. In a third mode, the output data (An-1, Bn-1) 1 bit before the output data An, Bn is (An-
1, Bn−1) = (1,1), the output data (An, Bn) is (An, Bn) = from the Gray code truth table.
It becomes (0, 0). As the fourth mode, output data A
Output data (An-1, Bn- 1 bit before n, Bn
1) is (An-1, Bn-1) = (1, 0),
From the Gray code truth table, the output data (An, Bn) is (An, Bn) = (0, 1).

Therefore, the output data An, Bn and the output data An-1, Bn one bit before are output from these four patterns.
-1 means (An, Bn) = (A'n-1, B'n-
1).

As described above, the four relations [(A
n, Bn) = (An-1, Bn-1), (An, Bn)
= (Bn-1, A'n-1), (An, Bn) = (B '
n-1, An-1), (An, Bn) = (A'n-1,
B'n-1)], the truth table shown in FIG. 2 can be obtained.

By the way, when the truth table of FIG. 2 is embodied as an encoding circuit, since the 1-bit delay circuit 1 is composed of a flip-flop, its output is Q, Q.
There are two types. These Q and Q'are An-1, A'n-1, Bn-1, B'n- shown in the truth table of FIG.
It can be used as it is as the data of 1. The relationship between these data and the input data I and Q is 4 as described above.
According to one assumption, the following four correspondences are established.

That is, first, if the input data (I, Q) is (I, Q) = (0,0), the output data (An,
Bn) is (An, Bn) = (An-1, Bn-1), and secondly, the input data (I, Q) is (I, Q) =
If (0, 1), the output data (An, Bn) is (A
n, Bn) = (Bn-1, A'n-1),
Thirdly, the input data (I, Q) is (I, Q) = (1,0)
If so, the output data (An, Bn) is (An, Bn)
= (B'n-1, An-1) and fourthly, if the input data (I, Q) is (I, Q) = (1,1),
The output data (An, Bn) is (An, Bn) = (A'n
-1, B'n-1).

Considering these four patterns of operation, 4
Since it corresponds to the bit line selector 2, the line inputs A0 to A3 and B0 to B3 of the line selector 2 are set to A0.
Is An-1, B0 is Bn-1, A1 is Bn-1,
A'n-1 for B1, B'n-1 for A2, A for B2
The input pattern of the line selector 2 is obtained by connecting A'n-1 to n-1, A3 and B'n-1 to B3, respectively.

From the above, since the output data An and Bn match the truth table shown in FIG. 2 depending on the pattern of the input data I and Q, the encoding circuit having the configuration shown in FIG. 1 is implemented. To be done.

The operation of the encoding circuit shown in FIG. 1 will be briefly described below. When the data I and Q to be encoded are input to the power of 2 0 and the power of 2 of the line selection control of the line selector 2, the line selector 2 selects one of the four lines according to the input pattern of the line selection control data. Just choose.

On the other hand, the output data of 1 bit before is An-1, A'n-1, B output from the 1-bit delay circuit 1.
n-1 and B'n-1 are line inputs A of the line selector 2.
0 to A3, B0 to B3 are input.

Line selection as shown in the truth table of FIG. 2 is performed corresponding to four patterns of data I and Q to be encoded.
By this selection, the encoded data An and Bn are fixed. From these facts, the configuration shown in FIG. 1 operates exactly the same as the gray code truth table shown in FIG. 11 as the prior art.

The case where the 1-bit delay circuit 1 functions as a delay means for delaying one of the output data signals to generate a plurality of delayed data signals has been described above. However, the 1-bit delay circuit 1 is shown in FIG. As is clear from the basic configuration of the encoding circuit according to the other embodiment shown in FIG. 5, it is possible to delay the other of the data signals and function as a delay unit for generating a plurality of delayed data signals. Incidentally, the truth table in this case is as shown in FIG.

That is, by the encoding of the encoding circuit here, the gray code truth value table as shown in FIG. 5 is established in the embodiment, and the gray code truth value as shown in FIG. 6 is further established. A pure binary code truth table corresponding to the table is obtained. The gray code truth table of FIG. 5 is replaced with the truth table shown in FIG. 4 as another embodiment, and the truth table of FIG. 4 embodied as a circuit has the configuration shown in FIG. However, the configuration and operation of the encoding circuit shown in FIG. 3 are basically the same as those of the configuration shown in FIG.

In any case, the configuration of each part as shown in FIG. 10, that is, the Gray code / pure binary code conversion circuit 3 and the pure 2 code is used.
Dramatically simplified by using one 4-bit line selector 2 instead of the circuit configuration requiring the code generation circuit 4 including the binary code / Gray code conversion circuit 6 or the 1-bit delay circuit 1 and the binary full addition circuit 5. An equivalent function can be obtained with a small scaled circuit.

Further, although the encoding circuit has been described above,
If the encoding circuit of each embodiment is provided with subtraction means (not shown) for subtracting the one selected from the plurality of delayed data signals from the output data signal by the line selector 2, FIG.
It can be used as a decoding circuit as shown in or a coding / decoding circuit.

Also in this case, a circuit which requires the respective parts configuration as shown in FIG. 7, that is, the gray conversion circuits 7 and 10, the flip-flops (F / F) 8 _I and 8 _Q, and the differential conversion circuit 9. Instead of the configuration, one 4-bit line selector 2
By using the subtraction means and the subtraction means, an equivalent function can be obtained in a greatly simplified small-scale circuit.

By the way, in the decoding circuit (encoding / decoding circuit) here, decoding can be performed by using one 4-bit line selector 2, but for the data to be coded at the time of modulation. Since the data of one bit before is added, it is necessary to subtract the added data from the data encoded by the subtracting means for demodulation.

In each of the above-described encoding circuit and decoding circuit (encoding / decoding circuit), the case where the 4-bit line selector 2 is used has been described, but the line selector 2 has other bits. May be

[0046]

As described above, according to the present invention, the configuration of each part in the conventional circuit configuration required when the encoding / decoding circuit is used at the time of n-phase PSK, that is,
Gray code / pure binary code conversion circuit, pure binary code / gray code conversion circuit, binary full addition circuit, delay circuit, and addition / subtraction circuit instead of a large-scale circuit configuration, delay means and multi-bit line selective addition Since the same function can be obtained by using the means and the subtraction means, the correspondence at the time of n-phase PSK can be realized by a greatly simplified small-scale circuit which has never been provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an encoding circuit according to an embodiment of the present invention.

FIG. 2 is a truth table showing a correspondence relationship between inputs and outputs in the encoding circuit shown in FIG.

FIG. 3 is a block diagram showing a basic configuration of an encoding circuit according to another embodiment of the present invention.

FIG. 4 is a truth table showing a correspondence relationship between inputs and outputs in the encoding circuit shown in FIG.

5 is a Gray code truth table in the encoding circuit shown in FIG. 1;

6 shows a pure binary code truth table in the encoding circuit shown in FIG.

FIG. 7 is a related technology of a conventional encoding / decoding circuit,
It is a block diagram showing a basic configuration of a decoding circuit having a Gray code differential conversion function.

8 illustrates the configuration of a gray conversion circuit included in the decoding circuit illustrated in FIG.

9 is a table exemplifying a correspondence relationship of data processing in the decoding circuit shown in FIG.

FIG. 10 is a block diagram showing a basic configuration of an encoding circuit having a Gray code full addition function as a related technique of a conventional encoding / decoding circuit.

11 shows a Gray code truth table in a Gray code / pure binary code conversion circuit and a binary full addition circuit provided in the encoding circuit shown in FIG.

12 shows a pure binary code truth table in the code generation circuit provided in the encoding circuit shown in FIG.

[Explanation of symbols]

1 1-bit delay circuit 2 Line selector 3 Gray code / pure binary code conversion circuit 4 Code generation circuit 5 Binary full adder circuit 6 Pure binary code / Gray code conversion circuit 7, 10 Gray conversion circuit 8 _I , 8 _Q flip-flop (F / F) 9 Differential conversion circuit 11 EX-OR circuit

Claims (5)

[Claims] 1. An output data signal obtained by combining and adding one of data signals input at the time of n-phase PSK and a signal obtained by selectively switching and selecting a plurality of delayed data signals in which the other of the data signals is delayed and distributed. An encoding circuit comprising: a multi-bit line selective addition means for outputting as an output encoded signal; and a delay means for generating the plurality of delayed data signals. 2. The encoding circuit according to claim 1, wherein the delay means delays one of the output data signals to generate the plurality of delayed data signals. 3. The encoding circuit according to claim 1, wherein the delay means delays the other of the data signals to generate the plurality of delayed data signals. 4. The encoding circuit according to any one of claims 1 to 3, and the one selected from the output data signals by the multi-bit line selective addition means among the plurality of delayed data signals. A decoding circuit comprising: subtraction means for subtracting. 5. The decoding circuit according to claim 4, wherein the multi-bit line selective addition means and the delay means are operated during encoding and decoding, and the subtraction means is operated only during the decoding. An encoding / decoding circuit characterized by the above.