JPH0983314A - Pulse expansion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily correspond to an input pulse signal and to secure sufficient delay time by providing a pulse stretching apart stretching the input pulse signal and a delay part stretching a signal outputted from the pulse stretching part. SOLUTION: The pulse stretching part 100 and the delay part 200 are provided. Signals outputted from the pulse stretchers 110 and 120 of the pulse stretching part 100 are stabilized in the inverter 131 and 132 of an inverter part 130 and are outputted as signals P2 having prescribed pulse width. The pulse output signals outputted from the inverter 131 are delayed in the general delay circuit 210 of the delay part 200 and they are NORed with pulse output signals P2 outputted from the inverter 132 in a NOR gate 220. The signals outputted from the NOR gate 220 are delayed in a delay circuit 230 again and are NORed with the pulse output signals P2 and are stretched. The signals outputted from the NOR gate 240 are inverted in an invertor 250 and are finally outputted as stretched pulse output signals P3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a pulse expansion circuit for expanding a pulse width by using a delay circuit, and particularly, when a signal having a short pulse width is inputted, it is effectively expanded. The present invention relates to a pulse expansion circuit that prevents malfunction of a semiconductor memory circuit.

[0002]

2. Description of the Related Art Normally, a pulse expansion circuit uses a delay circuit to expand the pulse width, and therefore the function of the delay circuit is important. As shown in FIG. 1A, a general form of a delay circuit used in the pulse expansion circuit is an input pulse signal PI.
Is input to the gate and the source is connected to the power supply VCC.
The MOS transistor P101 and the input pulse signal PI are input to the gate, and the drain is the PMOS transistor P1.
An NMOS transistor N101 connected to the drain of 01 and a source connected to the ground VSS, and a resistor R101 having one end connected to the drain of the PMOS transistor P101 and the other end connected to the pulse signal output end PO1-1.
And a capacitor C101 connected to the other end of the resistor R101 and the ground VSS.

Another common form of delay circuit is shown in FIG.
As shown in (b), the input pulse signal PI is input to the gate, the source is connected to the power supply VCC, and the drain is connected to the pulse signal output end PO1-2, and the PMOS transistor P102 is connected to the gate. NMO whose drain is connected to the drain of the PMOS transistor P102 and whose source is connected to the ground VSS.
It is composed of an S transistor N102 and a capacitor C102 connected to the drain of the PMOS transistor P102 and the ground VSS.

As shown in FIG. 2A, the delay circuit of a general form constructed as shown in FIGS. 1A and 1B has an input pulse signal PI of an inverter, that is, PMOS transistors P101 and P102. NMOS transistor N10
1, R102 and capacitor C1 at the output end of N102
01 and C102 appear at the pulse output terminals PO1-1 and PO1-2 with a delay due to the time constant. Here, FIG.
The pulse output signal PO1-1 of (a) has a delay due to the resistance R101 component as compared with the pulse output signal PO1-2 of FIG. 1 (b). In the general delay circuits of FIGS. 1A and 1B, the response to the input pulse signal that is input is delayed, or the delay time is not sufficient.

The conventional delay circuit (US Pat. No. 5,319,607) filed in the US patent, as shown in FIG. 1C, inputs the input pulse signal PI into the gate and supplies the power supply VC.
A PMOS transistor P103 whose source is connected to C
And a resistor R102 whose one end is connected to the drain of the PMOS transistor P103 and whose other end is connected to the pulse signal output end PO3, and an input pulse signal PI are input to the gate, and the drain is connected to the other end of the resistor R102. Ground V
NMOS transistor N10 whose source is connected to SS
3, the capacitor C103 connected to the other end of the resistor R102 and the ground VSS, and the pulse output signal PO2 output from the other end of the resistor R102 are input to the gate, and the power supply VCC
A PMOS transistor P104 having a source connected to the last pulse signal output terminal and a drain connected to the final pulse signal output terminal;
The drain of the S-transistor P104 and the capacitor C104 connected to the ground VSS, and the PMOS transistor P
A resistor R103 whose one end is connected to the drain of 104,
And the pulse output signal PO2 output from the other end of the resistor R102 is input to the gate, the drain is connected to the other end of the resistor R103, and the source is connected to the ground VSS.
It is composed of an S transistor N104.

In this delay circuit constructed as shown in FIG. 1C, when the input pulse signal PI transits from the low level to the high level as shown in FIG. 2B, the delay component becomes the capacitor C103, When the input pulse signal PI transits from the high level to the low level, the delay component becomes the resistance R10.
2 and the capacitor C103, a difference occurs in delay time. That is, the pulse output signal PO2 has a shorter delay time at the transition from the low level to the high level than at the transition from the high level to the low level. That is, FIG. 1 (c)
The delay circuit of Fig. 1 shows the response to the input pulse signal.
Although faster than in (a), the delay of the input pulse signal can be made longer than in (b) by the capacitor at the output end.

The conventional delay circuit (US Pat. No. 4,947,374) filed in the US patent inputs the input pulse signal PI to the gate as shown in FIG.
PMOS transistor P105 whose source is connected to
And the input pulse signal PI is input to the gate, and the source is connected to the drain of the PMOS transistor P105.
A MOS transistor P106 and a PMOS transistor P10 having a gate connected to the input pulse signal PI and a source connected to the drain of the PMOS transistor P106.
7 and the input pulse signal PI are input to the gate, and the PMOS
The source is connected to the drain of the transistor P107,
PMO having a drain connected to the pulse signal output terminal PO3
The S-transistor P108 and the input pulse signal PI are input to the gate, and the drain is the PMOS transistor P108.
The NMOS transistor N105 connected to the drain of the NMOS transistor N105, the source of which is connected to the ground VSS, the drain of the PMOS transistor P108, the capacitor C105 connected to the ground VSS, and the pulse output signal PO3 are input to the gate of the power supply VCC. A PMOS transistor P10 which is connected and outputs a final pulse output signal to the drain
9 and the pulse output signal PO3 are input to the gate, and P
The drain is connected to the drain of the MOS transistor P109, and the NMOS transistor N106 is connected to the ground VSS at the source.

In the conventional delay circuit constructed as shown in FIG. 1D, a large number of PMOS transistors P are used instead of resistors.
106, P107, and P108 are used. The delay state of this circuit is shown in FIG. That is, when the input pulse signal PI changes from the low level to the high level, the delay component becomes the capacitor C105, and when the input pulse signal PI changes from the high level to the low level, the delay component has a large number of PMOS transistors P106, P107, P10.
8 and the capacitor C105, a difference occurs in the delay time. Therefore, the pulse output signal PO3 has a delay time for transition from the high level to the low level longer than a delay time for transition from the low level to the high level. That is, FIG.
Although the delay circuit of (d) has a faster response to the input pulse signal than that of FIG. 1 (a), the delay of the input pulse signal becomes longer than that of (b) due to the capacitor at the output end, so that the delay circuit of FIG.
The characteristics are as shown in (c).

In the conventional delay circuit (US Pat. No. 4,931,998) filed in the US patent, as shown in FIG. 1E, the input pulse signal PI is input to the gate and the power supply VC is supplied.
PMOS transistor P110 whose source is connected to C
And a resistor R104 having one end connected to the drain of the PMOS transistor P110 and the other end connected to the pulse signal output end P104, and the input pulse signal PI input to the gate, and the drain connected to the other end of the resistor R104. Ground V
NMOS transistor N10 whose source is connected to SS
6 and the pulse output signal PO4 are input to the gate, and the power supply V
A PMOS transistor P111 having a source connected to CC and outputting a final pulse output signal to a drain;
A resistor R105 whose one end is connected to the drain of the S-transistor P111 and a pulse output signal PO4 are input to the gate, the drain is connected to the other end of the resistor R105, and the NMOS transistor N whose source is connected to the ground VSS.
And 107.

Since the conventional delay circuit configured as shown in FIG. 1 (e) has a form in which the capacitor is removed,
The transition from the low level to the high level as shown in (d) has almost no delay, and the transition from the high level to the low level is delayed because it depends only on the delay due to the resistance component. 2) The delay effect is less than that of the delay circuit. That is, the delay circuit of FIG. 1 (e) has a fast response to the input pulse signal, but the delay component is only the resistance, so the delay time is short.

[0011]

Therefore, since the conventional delay circuit uses the resistor and the capacitor for delaying the input pulse signal, only the delay is increased by the influence of the resistor and the capacitor at the output end. There is a disadvantage that the response to the pulse signal becomes slower or the delay becomes shorter when the response becomes faster.

It is an object of the present invention to solve the above drawbacks by providing a pulse expansion circuit capable of responding quickly to an input pulse signal and taking a sufficient delay time.

[0013]

In order to achieve the above object, a pulse expansion circuit of the present invention comprises a pulse expansion unit for expanding an input pulse signal by a constant width, and a signal output from the pulse expansion unit. It is characterized by comprising a delay unit for expanding.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 3 is an overall configuration diagram of a semiconductor memory circuit to which the present invention is applied. As shown in FIG. 3, a semiconductor memory circuit to which the present invention is applied receives an address input buffer 1 for receiving an input address AI and converting it from a TTL level to a CMOS level, and a signal output from the address input buffer 1. A row address decoder 2 and a column address decoder 3 for decoding, a word line driver 5 and a column selector 6 for receiving one of the signals output from the row address decoder 2 and the column address decoder 3 and selecting one cell of the main cell array 4. , ATD (Address) that detects a change in the address input buffer 1 and generates a pulse to be used as an internal clock.
Transition Detection) circuit 1
0, an ATD summing unit 11 that sums the pulses generated from a large number of ATD circuits 10, an ATD summing expansion circuit 12 that expands the signal output from the ATD summing unit 11, and A
A sense amplifier 7 that amplifies a signal output from the column selector 6 based on a signal output from the TD sum expansion circuit 12, and a sense amplifier 7 outputs a signal output from the ATD sum expansion circuit 12. And a data output buffer 9 for finally transmitting the data output from the data output unit 8. Here, the pulse expansion circuit according to the present invention corresponds to the ATD sum expansion circuit 12, and the signal generated from the ATD sum expansion circuit 12 is pulsed through the word line driver 5, the sense amplifier unit 7, and the data output unit 8. By operating only in, it plays the role of reducing the power consumption in the long term.

FIG. 4 is a block diagram of a pulse expansion circuit according to the present invention. The pulse expansion circuit according to the present invention comprises a pulse expansion unit 100 and a delay unit 200 as shown in FIG.

The pulse expansion unit 100 expands an input pulse signal by a constant width, and includes a plurality of pulse expanders 110 and 120, each of which expands the input pulse signal by a constant width. Pulse stretchers 110, 1
An inverter unit 130 that stabilizes the signal output from 20 is provided.

Here, the pulse stretchers 110 and 120 are
When the input pulse signal is a positive signal, it is composed of a positive pulse expansion pulse expansion inverter 111 which expands it by a constant width, and when the input signal is a negative signal, a negative pulse expansion inverter 112 which expands it by a constant width. Or a positive pulse expansion inverter 111 that expands the input pulse signal by a fixed width and a negative pulse expansion inverter 112 that expands the signal output from the positive pulse expansion inverter 111 by a fixed width. At this time, the positions of the positive pulse expansion inverter 111 and the negative pulse expansion inverter 112 may be changed such that the input pulse signal is first expanded by the negative pulse expansion inverter 112 and then expanded by the positive pulse expansion inverter 111 later. it can.

Here, the positive pulse expansion inverter 111
Is an input pulse signal or negative pulse expansion inverter 11
The inverted output signal of 2 is input to the gate, and the PMOS transistor P1 whose source is connected to the power supply VCC and the PMOS transistor P1
A resistor R connected in series to the drain of the transistor P1
1, R2, resistors R1 and R2, a capacitor C1 connected to the ground VSS, an input pulse signal or an inverted output signal of the negative pulse expansion inverter 112 is input to the gate, and the source is connected to the resistor R2.
And the input pulse signal or the output signal of the negative pulse expansion inverter 112 is input to the gate, the drain is connected to the drain of the PMOS transistor P2, and the ground VSS
And an NMOS transistor N1 whose source is connected to.

The negative pulse expansion inverter 112 inputs the input pulse signal or the inverted output signal of the positive pulse expansion inverter 111 to the gate, and the PMOS transistor P3 whose source is connected to the power supply VCC and the input pulse signal or the positive pulse expansion inverter. The output signal of the input terminal 111 is input to the gate, and the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N2 and NMO.
A resistor R connected in series to the source of the S transistor N2
3, R4, resistors R3, R4 and a capacitor C2 connected to the ground VSS, and the input pulse signal or the output signal of the positive pulse expansion inverter 111 are input to the gate, and the drain is connected to the resistor P4 to the ground VSS. It is composed of an NMOS transistor N3 whose sources are connected.

The inverter unit 130 is a pulse stretcher 11
The inverter 131 inverts the signal output from the last stage of 0 and 120 and outputs the inverted signal to the delay unit 200, and the inverter 132 that inverts the signal output from the inverter 131 and outputs the inverted signal to the delay unit 200. It

The delay unit 200 expands the signal output from the pulse expansion unit 100. The delay unit 200 delays the signal output from the inverter 131 of the pulse expansion unit 100, and the delay circuit 210 outputs the delay circuit 210. NOR gate 220 that performs a NOR operation on the output signal and the signal output from the inverter 132 of the pulse expansion unit 100.
A delay circuit 230 that delays the signal output from the NOR gate 220, a NOR gate 240 that performs a NOR operation on the signal output from the delay circuit 230 and the signal output from the inverter 132 of the pulse expansion unit 100, and The inverter 250 is configured to invert the signal output from the NOR gate 240 and finally output the inverted signal.

The operation of the pulse expansion circuit according to the present invention constructed as above will be described in detail with reference to FIGS. 5, 6 and 7. 5A and 5B show the positive pulse expansion inverter 111 and the negative pulse expansion inverter 112, respectively, and FIGS. 6A, 6B, 6C and 6D show the positive pulse expansion inverter 111 and the negative pulse, respectively. FIG. 6 is a signal waveform diagram showing an operation of the decompression inverter 112.

Positive pulse expansion inverter 1 of FIG. 5 (a)
11 is an NMO for the input pulse signal PI11 which is a positive signal.
Enable quickly according to S-transistor N1, PM
The OS transistors P1 and P2, the resistors R1 and R2, and the capacitor C1 are slowly disabled.

That is, as shown in FIG. 6A, the pulse output signal PO11 is output when the input pulse signal PI11, which is a positive signal, transits from the low level to the high level.
Shifts to the low level quickly and the input pulse signal PI11 shifts from the high level to the low level, the output pulse output signal PO11 slowly shifts to the high level so that the input pulse signal is expanded and output. .
Even when the input pulse signal PI11 is a short pulse signal as shown in FIG. 6C, when the input pulse signal PI11 makes a transition from the low level to the high level, the pulse output signal PO11 that is output is quickly at the low level. When the input pulse signal PI11 changes from the high level to the low level, the output pulse output signal PO11 slowly changes to the high level, and the expanded pulse output signal PO11 is output.

The negative pulse expansion inverter 112 of FIG. 5 (b) enables the input pulse signal PI12, which is a negative signal, in the opposite phase of the input pulse signal PI11 quickly according to the PMOS transistor P3, and the NMOS transistors N2 and N3. Slowly disable according to the resistors R3, R4 and the capacitor C2.

That is, as shown in FIG. 6 (b), when the input pulse signal PI12, which is a negative signal, changes from the high level to the low level, the pulse output signal PO12 is output.
Shifts to the high level quickly and the input pulse signal PI12 shifts from the low level to the high level, the output pulse output signal PO12 slowly shifts to the low level so that the input pulse signal is extended and output. .
Even when the input pulse signal PI12 is a short pulse signal as shown in FIG. 6D, when the input pulse signal PI12 makes a transition from the high level to the low level, the pulse output signal PO12 that is output is quickly at the high level. When the input pulse signal PI12 changes from low level to high level, the output pulse output signal PO12 slowly changes to low level, and the expanded pulse output signal PO12 is output.

Therefore, the pulse stretcher 1 of the pulse stretcher circuit
If only the positive pulse expansion inverter 111 shown in FIG.
11 is expanded and output, and when only the negative pulse expansion inverter 112 of FIG. 5B is used, the negative input pulse signal PI12 is expanded and output.

As shown in FIG. 4, the pulse stretcher 110,
When 120 is composed of the positive pulse expansion inverter 111 and the negative pulse expansion inverter 112, the input pulse signal may be a positive pulse signal or a negative pulse signal, and the input pulse signal is expanded to double the delay effect. . By connecting a plurality of pulse expanders 110 and 120 in series, the input pulse signal to be input can be expanded longer.

As shown in FIG. 4, pulse stretchers 110 and 120 are provided.
The operation in the case where is composed of the positive pulse expansion inverter 111 and the negative pulse expansion inverter 112 will be described in detail with reference to FIG. The input pulse signal PI is expanded as a negative pulse signal by the positive pulse expansion inverter 111 as shown in FIG. 6A, and the negative pulse signal is converted into a positive pulse signal by the negative pulse expansion inverter 112 as shown in FIG. 6B. It is extended while being returned. The delay effect can be doubled by further adding this to the pulse stretcher 120 for processing.

The signals output from the pulse stretchers 110 and 120 are output to the inverter 13 of the inverter unit 130.
Signal P2 stabilized at 1, 132 and having a constant pulse width
Is output as The pulse output signal output from the inverter 131 of the inverter unit 130 is delayed by the general delay circuit 210, and then NORed with the pulse output signal P2 output from the inverter 132 by the NOR gate 220, and the NOR gate 220 is again used. The signal output from the NOR gate 24 is delayed by the delay circuit 230.
When it is 0, the logical sum of the pulse output signal P2 output from the inverter 132 and the desired pulse width is extended. The signal output from the NOR gate 240 is further inverted by the inverter 250 and finally output as the pulse output signal P3 expanded by a desired pulse width.

Therefore, when the pulse stretchers 110 and 120 according to the present invention are used as shown in FIG. 7A, the resistance and the capacitor at the output end do not act as a load at the time of enabling, so that the conventional delay circuit of FIG. It is enabled faster than it is used, and when it is disabled, the resistor and the capacitor both act as a load and are disabled later, so that a signal having a long pulse width can be generated with respect to the input signal. As shown in FIG. 7B, when the pulse expanders 110 and 120 according to the present invention are used, a signal having a general pulse width can be output even if a short pulse signal is input.

[0032]

The pulse stretcher circuit according to the present invention responds to an input signal faster than the conventional pulse stretcher circuit using a delay circuit, and has the effect of increasing the delay effect. And, in the conventional circuit, the circuit for expanding this signal is used in the ATD block, but the present invention uses the automatic power down block (Auto Power Down Bl).
oc)).

[Brief description of drawings]

1A, 1B, 1C, 1D, and 1E are configuration diagrams of a conventional delay circuit.

2 (a), (b), (c), and (d) are shown in FIG. 1 (a).
It is a signal waveform diagram of each part of (b) (c) (d) (e).

FIG. 3 is an overall configuration diagram of a semiconductor memory circuit to which the present invention is applied.

FIG. 4 is a configuration diagram of a pulse expansion circuit according to the present invention.

5A is a block diagram of the positive pulse expansion inverter shown in FIG. 4, and FIG. 5B is a block diagram of the negative pulse expansion inverter shown in FIG.

6 (a), (b), (c), and (d) are shown in FIG. 5 (a).
It is a signal waveform diagram of each part of (b).

7 (a) and 7 (b) are signal waveform diagrams as a result of applying FIGS. 1 and 5 to FIG.

[Explanation of symbols]

1 ... Address input buffer, 2 ... Row address decoder,
3 ... Column address decoder, 4 ... Main cell array, 5 ...
Word line driver, 6 ... Column selector, 7 ... Sense amplification section, 8 ... Data output section, 9 ... Data output buffer, 10
... ATD circuit, 11 ... ATD summing unit, 12 ... ATD summing expansion circuit, 100 ... Pulse expanding unit, 110, 120 ... Pulse expander, 111, 121 ... Positive pulse expanding inverter, 112, 122 ... Negative pulse expanding inverter, 13
0 ... Inverter section, 131, 132, 250 ... Inverter, 200 ... Delay section, 210, 230 ... Delay circuit,
220, 240 ... NOR gates, P1-P3 ... PMOS
Transistors, N1 to N3 ... NMOS transistors, R
1 to R4 ... Resistors, C1, C2 ... Capacitors.

Claims (5)

[Claims] 1. A pulse expansion unit (100) for expanding an input pulse signal by a constant width, and a delay unit (2) for expanding a signal output from the pulse expansion unit (100).
00) and a pulse expansion circuit. 2. The pulse expander (100) outputs a plurality of pulse expanders (110, 120) for expanding an input pulse signal by a constant width, and the pulse expanders (110, 120). 2. The pulse expansion circuit according to claim 1, further comprising an inverter unit (130) for stabilizing the signal. 3. The pulse stretcher (110, 120).
Is a positive pulse expansion inverter (111) that inverts and expands an input pulse signal by a certain width, and an inverted signal output from the positive pulse expansion inverter (111) by a certain width. 3. The pulse expansion circuit according to claim 2, comprising a negative pulse expansion inverter (112) for expanding. 4. The pulse stretcher (110, 120).
Is a negative pulse expansion inverter (112) for inverting and expanding the input pulse signal by a constant width, and inverting and expanding the inverted signal output from the negative pulse expansion inverter (112) by a constant width. The pulse expansion circuit according to claim 2, wherein the pulse expansion circuit comprises a positive pulse expansion inverter (111). 5. The delay unit (200) includes a first delay circuit (210) for delaying a signal output from the pulse expansion unit (100), and a signal output from the first delay circuit (210). A first NOR gate (220) that performs a NOR operation on the signal output from the pulse stretcher (100), and a second delay circuit (230) that delays the signal output from the first NOR gate (220), A second NOR gate (240) that performs a NOR operation on the signal output from the second delay circuit (230) and the signal output from the pulse expansion unit (100); and the second N gate.
The pulse expansion circuit according to claim 1, comprising an inverter (250) for inverting and outputting a signal output from the OR gate (240).