JP2789318B2 - Pulse expansion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse extending circuit for extending a pulse width by using a delay circuit in a semiconductor memory circuit, and particularly to a pulse extending circuit for effectively extending a signal having a short pulse width. The present invention relates to a pulse expansion circuit for preventing a malfunction of a semiconductor memory circuit.

[0002]

2. Description of the Related Art Normally, a pulse stretching circuit uses a delay circuit to extend a pulse width, so that the function of the delay circuit is important. As shown in FIG. 1A, a general form of delay circuit used in a pulse expansion circuit is an input pulse signal PI.
Is input to the gate, and the source connected to the power supply VCC
The MOS transistor P101 and the input pulse signal PI are input to the gate, and the drain is the PMOS transistor P1.
And a resistor R101 having one end connected to the drain of the PMOS transistor P101 and the other end connected to the pulse signal output terminal PO1-1.
And a capacitor C101 connected to the other end of the resistor R101 and the ground VSS.

[0003] Another common form of delay circuit is shown in FIG.
As shown in (b), the input pulse signal PI is inputted to the gate, the source is connected to the power supply VCC, and the drain is connected to the pulse signal output terminal PO1-2. , The drain of which is connected to the drain of the PMOS transistor P102, and the source of which is connected to the ground VSS.
It comprises an S transistor N102 and a capacitor C102 connected to the drain of the PMOS transistor P102 and the ground VSS.

In a general delay circuit configured as shown in FIGS. 1A and 1B, as shown in FIG. 2A, an input pulse signal PI is supplied to an inverter, that is, PMOS transistors P101 and P102. NMOS transistor N10
1, a resistor R101 at the output terminal of N102 and a capacitor C1.
01 and appear at the pulse output terminals PO1-1 and PO1-2 with a delay due to the time constant of C102. Here, FIG.
The pulse output signal PO1-1 of FIG. 1A has a delay due to the resistance R101 component as compared with the pulse output signal PO1-2 of FIG. In the general delay circuits shown in FIGS. 1A and 1B, the response to the input pulse signal is delayed or the delay time is not sufficient.

[0005] A conventional delay circuit (US Pat. No. 5,319,607) filed by the US patent applies an input pulse signal PI to a gate as shown in FIG.
PMOS transistor P103 whose source is connected to C
And a resistor R102 having one end connected to the drain of the PMOS transistor P103 and the other end connected to the pulse signal output terminal PO3, and an input pulse signal PI input to the gate, and the drain connected to the other end of the resistor R102. Ground V
NMOS transistor N10 whose source is connected to SS
3, a capacitor C103 connected to the other end of the resistor R102 and the ground VSS, and a pulse output signal PO2 output from the other end of the resistor R102 to the gate.
A PMOS transistor P104 having a source connected to the source and a drain connected to the final pulse signal output terminal;
A capacitor C104 connected to the drain of the S transistor P104 and the ground VSS;
A resistor R103 having one end connected to the drain of 104;
And the pulse output signal PO2 output from the other end of the resistor R102 is input to the gate, the drain is connected to the other end of the resistor R103, and the source is connected to the ground VSS.
And an S transistor N104.

In this delay circuit configured as shown in FIG. 1C, when the input pulse signal PI changes from the low level to the high level as shown in FIG. 2B, the delay component becomes the capacitor C103, When the input pulse signal PI transitions from the high level to the low level, the delay component
2 and the capacitor C103, causing a difference in delay time. That is, the delay time of the pulse output signal PO2 in the transition from the low level to the high level is shorter than that in the transition from the high level to the low level. That is, FIG.
The response of the delay circuit of FIG.
Although faster than (a), the delay of the input pulse signal can be made longer than (b) by the capacitor at the output end.

A conventional delay circuit (US Pat. No. 4,947,374) filed by the US patent applies an input pulse signal PI to a gate as shown in FIG.
PMOS transistor P105 whose source is connected to
And the input pulse signal PI is input to the gate, and the source of the PMOS transistor P105 is connected to the drain of the PMOS transistor P105.
A MOS transistor P106 and a PMOS transistor P10 having an input pulse signal PI input to its gate and a source connected to the drain of the PMOS transistor P106
7 and the input pulse signal PI are input to the gate, and the PMOS
The source is connected to the drain of the transistor P107,
PMO with drain connected to pulse signal output PO3
The S transistor P108 and the input pulse signal PI are input to the gate, and the drain is the PMOS transistor P108
The NMOS transistor N105 connected to the drain of the PMOS transistor P108, the source of which is connected to the ground VSS, the capacitor C105 connected to the drain of the PMOS transistor P108 and the ground VSS, and the pulse output signal PO3 are input to the gate, and the source is connected to the power supply VCC PMOS transistor P10 connected to output the final pulse output signal to the drain
9 and the pulse output signal PO3 are input to the gate,
An NMOS transistor N106 has a drain connected to the drain of the MOS transistor P109 and a source connected to the ground VSS.

A conventional delay circuit configured as shown in FIG. 1D has a large number of PMOS transistors P instead of resistors.
106, P107 and P108 are used. FIG. 2C shows the delay state of this circuit. That is, when the input pulse signal PI changes from the low level to the high level, the delay component becomes the capacitor C105, and when the input pulse signal PI changes from the high level to the low level, the delay component has a large number of PMOS transistors P106, P107, P10.
8 and the capacitor C105, causing a difference in delay time. Accordingly, the pulse output signal PO3 has a longer delay time from the high level to the low level than the delay time from the low level to the high level. That is, FIG.
In the delay circuit of FIG. 2D, the response to the input pulse signal is faster than that of FIG. 1A, but the delay of the input pulse signal is longer than that of FIG.
The characteristics are as shown in FIG.

A conventional delay circuit (US Pat. No. 4,931,998) filed in the United States patent application, as shown in FIG. 1E, inputs an input pulse signal PI to a gate and supplies a power supply VC.
PMOS transistor P110 whose source is connected to C
And a resistor R104 having one end connected to the drain of the PMOS transistor P110 and the other end connected to the pulse signal output terminal P104, and an input pulse signal PI input to the gate, and the drain connected to the other end of the resistor R104; Ground V
NMOS transistor N10 whose source is connected to SS
6 and the pulse output signal PO4 are input to the gate, and the power supply V
A PMOS transistor P111 having a source connected to CC and outputting a final pulse output signal to a drain;
A resistor R105 having one end connected to the drain of the S transistor P111 and a pulse output signal PO4 are input to the gate, and an NMOS transistor N having a drain connected to the other end of the resistor R105 and a source connected to the ground VSS.
107.

The conventional delay circuit configured as shown in FIG. 1E has a form in which a capacitor is removed.
The transition from the low level to the high level as in (d) has almost no delay, and the transition from the high level to the low level is delayed because it depends only on the delay due to the resistance component. The delay effect is less than that of the delay circuit of (1). That is, the delay circuit of FIG. 1E has a fast response to an input pulse signal, but has a short delay time because the delay component is only a resistor.

[0011]

Therefore, the conventional delay circuit uses a resistor and a capacitor to delay the input pulse signal. Therefore, as the delay is increased by the influence of the resistor and the capacitor at the output terminal, the input is increased as much as possible. There is a disadvantage in that the response to a given pulse signal is slow or the response time is fast, the delay time is reduced.

It is an object of the present invention to improve such disadvantages to provide a pulse decompression circuit which can quickly respond to an input pulse signal and can take a sufficient delay time.

[0013]

In order to achieve the above object, a pulse expansion circuit according to the present invention comprises a pulse expansion section for expanding an input pulse signal by a predetermined width, and a signal output from the pulse expansion section. And a delay section for extending.

[0014]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 3 is an overall configuration diagram of a semiconductor memory circuit to which the present invention is applied. As shown in FIG. 3, a semiconductor memory circuit to which the present invention is applied receives an address AI and converts the TTL level to a CMOS level upon receiving an input address AI, and receives a signal output from the address input buffer 1. A row address decoder 2 and a column address decoder 3 for decoding; a word line driver 5 and a column selector 6 for receiving a signal output from the row address decoder 2 and the column address decoder 3 and selecting one cell of the main cell array 4; ATD (Address) which detects a change in the address input buffer 1 and generates a pulse used as an internal clock.
(Transition Detection) circuit 1
0, an ATD summing unit 11 for summing up the pulses generated from the many ATD circuits 10, an ATD summing / expanding circuit 12 for expanding the signal output from the ATD summing unit 11, and A
The sense amplifier 7 amplifies the signal output from the column selector 6 based on the signal output from the TD summing / expansion circuit 12, and outputs from the sense amplifier 7 based on the signal output from the ATD summing / expansion circuit 12. And a data output buffer 9 for finally transmitting data output from the data output unit 8. Here, the pulse expansion circuit according to the present invention corresponds to the ATD summing / expansion circuit 12, and the signal generated from the ATD summing / expansion circuit 12 transmits the word line driver 5, the sense amplifier 7, and the data output unit 8 for a pulse period. By acting only on the power supply, it plays a role of reducing long-term power consumption.

FIG. 4 is a block diagram of a pulse decompression circuit according to the present invention. The pulse expansion circuit according to the present invention includes a pulse expansion unit 100 and a delay unit 200 as shown in FIG.

The pulse extender 100 extends the input pulse signal by a predetermined width. The pulse expander 100 includes one or more pulse expanders 110 and 120 each configured to extend the input pulse signal by a predetermined width. Pulse expander 110, 1
And an inverter unit 130 for stabilizing the signal output from the inverter 20.

Here, the pulse extenders 110 and 120 are
When the input pulse signal is a positive signal, it is constituted by a positive pulse expansion pulse expansion inverter 111 which expands by a certain width, and when the input signal is a negative signal, it is formed by a negative pulse expansion inverter 112 which expands by a certain width. Or a positive pulse expansion inverter 111 for expanding the input pulse signal by a certain width and a negative pulse expansion inverter 112 for expanding the signal output from the positive pulse expansion inverter 111 by a certain width. At this time, the positions of the positive pulse expansion inverter 111 and the negative pulse expansion inverter 112 may be changed so that the input pulse signal is first expanded by the negative pulse expansion inverter 112 and then expanded by the positive pulse expansion inverter 111. it can.

Here, the positive pulse extension inverter 111
Is an input pulse signal or a negative pulse extension inverter 11
And a PMOS transistor P1 having a source connected to the power supply VCC,
A resistor R connected in series with the drain of the transistor P1
1 and R2, a capacitor C1 connected to the resistors R1 and R2 and the ground VSS, and an input pulse signal or an inverted output signal of the negative pulse extension inverter 112 input to the gate, and a PMOS transistor P2 having a source connected to the resistor R2
And the input pulse signal or the output signal of the negative pulse extension inverter 112 are input to the gate, the drain is connected to the drain of the PMOS transistor P2, and the ground VSS
And an NMOS transistor N1 connected to the source.

The negative pulse expansion inverter 112 inputs an input pulse signal or an inverted output signal of the positive pulse expansion inverter 111 to a gate, and a PMOS transistor P3 whose source is connected to a power supply VCC, an input pulse signal or a positive pulse expansion inverter. An NMOS transistor N2 having a drain connected to the drain of the PMOS transistor P3 and an NMOS transistor N2.
A resistor R connected in series to the source of the S transistor N2
3, R4, a capacitor C2 connected to the resistors R3, R4 and the ground VSS, and an input pulse signal or an output signal of the positive pulse extension inverter 111 to the gate, a drain connected to the resistor P4, and a connection to the ground VSS. A source connected NMOS transistor N3.

The inverter unit 130 includes the pulse expander 11
The inverter 131 inverts the signal output from the last stage of 0 and 120 and outputs the inverted signal to the delay unit 200, and the inverter 132 further inverts the signal output from the inverter 131 and outputs the inverted signal to the delay unit 200. You.

The delay section 200 extends the signal output from the pulse expansion section 100. The delay section 210 delays the signal output from the inverter 131 of the pulse expansion section 100, and the delay circuit 210 outputs the signal. NOR gate 220 that performs a NOR operation on a signal output from the inverter 132 of the pulse extending unit 100 and a signal output from the inverter 132
A delay circuit 230 that delays a signal output from the NOR gate 220, a NOR gate 240 that performs a NOR operation on a signal output from the delay circuit 230 and a signal output from the inverter 132 of the pulse expansion unit 100, and An inverter 250 that inverts the signal output from the NOR gate 240 and finally outputs the inverted signal.

The operation of the pulse stretching circuit according to the present invention will be described in detail with reference to FIGS. 5, 6, and 7. FIG. FIGS. 5A and 5B show a positive pulse expansion inverter 111 and a negative pulse expansion inverter 112, respectively. FIGS. 6A, 6B, 6C and 5D show the positive pulse expansion inverter 111 and the negative pulse expansion inverter of FIG. FIG. 4 is a signal waveform diagram illustrating an operation of a stretching inverter 112.

The positive pulse extension inverter 1 shown in FIG.
Reference numeral 11 denotes an NMO input pulse signal PI11 which is a positive signal.
It is enabled quickly according to the S transistor N1, and PM
The OS transistors P1 and P2, the resistors R1 and R2, and the capacitor C1 are slowly disabled.

That is, as shown in FIG. 6A, when the input pulse signal PI11, which is a positive signal, transitions from a low level to a high level, a pulse output signal PO11 is output.
Quickly transitions to a low level, and when the input pulse signal PI11 transitions from a high level to a low level, the output pulse output signal PO11 slowly transitions to a high level to extend and output the input pulse signal. .
As shown in FIG. 6C, even when the input pulse signal PI11 is a short pulse signal, when the input pulse signal PI11 transitions from a low level to a high level, the output pulse output signal PO11 quickly changes to a low level. When the input pulse signal PI11 transitions from the high level to the low level, the output pulse output signal PO11 slowly transitions to the high level to output the expanded pulse output signal PO11.

The negative pulse expansion inverter 112 shown in FIG. 5B enables the input pulse signal PI12, which is a negative signal, in the opposite phase to the input pulse signal PI11, in accordance with the PMOS transistor P3, and quickly enables the NMOS transistors N2 and N3. And the resistors R3 and R4 and the capacitor C2 are slowly disabled.

That is, as shown in FIG. 6B, when the input pulse signal PI12, which is a negative signal, transitions from the high level to the low level, the output pulse output signal PO12 is output.
Quickly transitions to the high level, and when the input pulse signal PI12 transitions from the low level to the high level, the output pulse output signal PO12 slowly transitions to the low level, and the input pulse signal is expanded and output. .
As shown in FIG. 6D, even when the input pulse signal PI12 is a short pulse signal, when the input pulse signal PI12 transitions from the high level to the low level, the output pulse output signal PO12 is quickly turned to the high level. When the input pulse signal PI12 changes from the low level to the high level, the output pulse output signal PO12 changes slowly to the low level, and the expanded pulse output signal PO12 is output.

Accordingly, the pulse extender 1 of the pulse extender circuit
In the case where 10 and 120 are constituted only by the positive pulse expansion inverter 111 of FIG.
11 is extended and output, and when it is constituted only by the negative pulse extending inverter 112 in FIG. 5B, the negative input pulse signal PI12 is extended and outputted.

As shown in FIG. 4, a pulse expander 110,
In the case where 120 includes the positive pulse expansion inverter 111 and the negative pulse expansion inverter 112, the input pulse signal may be a positive pulse signal or a negative pulse signal, and the input pulse signal is expanded to double the delay effect. . By connecting a large number of pulse expanders 110 and 120 in series, it is possible to extend an input pulse signal to be input for a longer time.

As shown in FIG. 4, the pulse expanders 110 and 120
In the case where is composed of a positive pulse expansion inverter 111 and a negative pulse expansion inverter 112, will be described in detail with reference to FIG. The input pulse signal PI is expanded as a negative pulse signal by the positive pulse expansion inverter 111 as shown in FIG. 6A, and the negative pulse signal is converted into a positive pulse signal again by the negative pulse expansion inverter 112 as shown in FIG. It is extended while being returned. Incidentally, the delay effect can be doubled by further adding this to the pulse expander 120 for processing.

The signals output from the pulse expanders 110 and 120 are supplied to the inverter 13 of the inverter section 130.
Signal P2 stabilized at 1, 132 and having a constant pulse width
Is output as The pulse output signal output from the inverter 131 of the inverter unit 130 is delayed by the general delay circuit 210, and then NOR-ORed with the pulse output signal P2 output from the inverter 132 by the NOR gate 220. Is output from the NOR gate 24 after being delayed by the delay circuit 230.
By performing a NOR operation on the pulse output signal P2 output from the inverter 132 at 0, the pulse output signal P2 is extended by a desired pulse width. The signal output from NOR gate 240 is further inverted by inverter 250 and finally output as pulse output signal P3 expanded by a desired pulse width.

Therefore, when the pulse expanders 110 and 120 according to the present invention are used as shown in FIG. 7A, the resistor and the capacitor at the output end do not act as a load when enabled, so that the conventional delay circuit of FIG. Since it is enabled faster than used, and when disabled, the resistor and the capacitor both act as loads and are disabled later, so that a signal having a longer pulse width with respect to the input signal can be generated. As shown in FIG. 7B, when the pulse expanders 110 and 120 according to the present invention are used, a signal having a general pulse width can be output even when a short pulse signal is input.

[0032]

The pulse stretching circuit according to the present invention responds to an input signal faster than a pulse stretching circuit using a conventional delay circuit, and has the effect of increasing the delay effect. In the conventional circuit, a circuit for expanding this signal is used for the ATD block. However, in the present invention, an automatic power down block (Auto Power Down Bl) is used.
ock).

[Brief description of the drawings]

1 (a), (b), (c), (d), and (e) are configuration diagrams of a conventional delay circuit.

2 (a), (b), (c) and (d) show FIG. 1 (a).
It is a signal waveform diagram of each part of (b), (c), (d), and (e).

FIG. 3 is an overall configuration diagram of a semiconductor memory circuit to which the present invention is applied;

FIG. 4 is a configuration diagram of a pulse expansion circuit according to the present invention.

5A is a configuration diagram of a positive pulse extension inverter of FIG. 4, and FIG. 5B is a configuration diagram of a negative pulse extension inverter of FIG.

6 (a), (b), (c), and (d) show FIG. 5 (a).
It is a signal waveform diagram of each part of (b).

FIGS. 7A and 7B are signal waveform diagrams obtained by applying FIGS. 1 and 5 to FIG. 4;

[Explanation of symbols]

1 ... address input buffer, 2 ... row address decoder,
3 ... column address decoder, 4 ... main cell array, 5 ...
Word line driver, 6 column selector, 7 sense amplifier, 8 data output, 9 data output buffer, 10
.. ATD circuit, 11 ATD summing unit, 12 ATD summing and expanding circuit, 100 pulse expanding unit, 110, 120 pulse expander, 111, 121 positive pulse expanding inverter, 112, 122 negative pulse expanding inverter, 13
0: inverter unit, 131, 132, 250: inverter, 200: delay unit, 210, 230: delay circuit,
220, 240: NOR gate, P1 to P3: PMOS
Transistors, N1 to N3 ... NMOS transistors, R
1 to R4: resistance, C1, C2: capacitor.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-110396 (JP, A) JP-A-7-95024 (JP, A) JP-A-3-220914 (JP, A) 3869 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 5/00

Claims (3)

(57) [Claims] Comprising 1. A pulse stretcher unit to extend the input pulse signal by a predetermined width (100), a delay unit for expanding the signal output from the pre-Symbol pulse stretcher unit (100) and (200), the said The pulse extending unit (100) includes a plurality of pulses for extending the input pulse signal by a certain width.
And a signal output from the pulse expander (110, 120).
Includes, an inverter unit that stabilizes (130) to issue, the pulse stretcher (110, 120) is a positive of extending by inverting the input pulse signal by a predetermined width
A pulse extension inverter (111) and an output from the positive pulse extension inverter (111).
The inverted signal is expanded by inverting it by a certain width.
A negative pulse expansion inverter (112)
And the negative pulse extension inverter (112) is connected in series between a power supply (VCC) and a ground (VSS).
PMOS transistor (P3), first NMOS transistor
Transistor (N2), first and second resistors (R3 and R3).
4) and a connection point between the second NMOS transistor (N3) and the first and second resistors (R3 and R4) and ground.
(Vss), and an input terminal (P ) connected to the gates of all transistors.
I12), a PMOS transistor (P3) and a first NMOS transistor
The output terminal (PO1) connected to the connection point of the transistor (N2)
Has a 2), a pulse stretcher circuit, characterized in that. Provided wherein pulse extension portion extending the input pulse signal by a predetermined width (100), a delay unit for expanding the signal output from the pre-Symbol pulse stretcher unit (100) and (200), the said The pulse extending unit (100) includes a plurality of pulses for extending the input pulse signal by a certain width.
And a signal output from the pulse expander (110, 120).
Includes, an inverter unit that stabilizes (130) to issue, the pulse stretcher (110, 120) is negatively be extended by inverting the input pulse signal by a predetermined width
A pulse extension inverter (112), and an output from the negative pulse extension inverter (112).
The inverted signal is extended by inverting it by a certain width.
Positive pulse stretching inverter (111), it is composed of the negative pulse stretching inverter (112) is connected in series between the power supply (VCC) and ground (VSS)
PMOS transistor (P3), first NMOS transistor
Transistor (N2), first and second resistors (R3 and R3).
4) and a connection point between the second NMOS transistor (N3) and the first and second resistors (R3 and R4) and ground.
(Vss), and an input terminal (P ) connected to the gates of all transistors.
I12), a PMOS transistor (P3) and a first NMOS transistor
The output terminal (PO1) connected to the connection point of the transistor (N2)
Has a 2), a pulse stretcher circuit, characterized in that. 3. The delay unit (200) includes a first delay circuit (210) that delays a first signal output from the pulse expansion unit (100), and an output from the first delay circuit (210). that signal and is output from the pulse expander portion (100) and said first signal
A first NOR gate (220) that performs a NOR operation on a second signal that is a signal obtained by inverting a signal, a second delay circuit (230) that delays a signal output from the first NOR gate (220), A signal output from the second delay circuit (230) and the signal
A second NOR gate (24
0), before Symbol pulse stretcher circuit according to claim 1 or 2, wherein an inverter (250) for inverting a signal outputted from the 2NOR gate (240), characterized in that it comprises a.