JP3538467B2 - Clock signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generating circuit for generating an internal clock signal synchronized with a clock signal input from the outside in a semiconductor integrated circuit.

[0002] In a semiconductor integrated circuit, the operations of various internal circuits are controlled based on a predetermined clock signal. Such a clock signal is generated by a clock signal generation circuit provided in the semiconductor integrated circuit based on an external clock signal externally input to the semiconductor integrated circuit.

In recent years, the operation speed of a semiconductor integrated circuit has been increasing more and more, and the frequency of a clock signal for controlling the operation of an internal circuit tends to be higher. Therefore, it is necessary for the clock signal generation circuit to stably generate a high frequency clock signal required by the internal circuit.

[0004]

2. Description of the Related Art An example of a conventional clock signal generation circuit will be described with reference to FIG. The clock signal generation circuit has a two-stage T
The flip-flop circuits 1 and 2 are connected in series, and an external clock signal C is input to the first-stage T flip-flop circuit 1.

[0005] Each of the T flip-flop circuits 1 and 2, for example, divides an input signal by two and outputs the same, and outputs a clock signal CLK of a frequency necessary for controlling an internal circuit from the next-stage T flip-flop circuit 2. Is done.

Therefore, as shown in FIG. 8, when the external clock signal C is input to the first-stage T flip-flop circuit 1, a signal SG1 obtained by dividing the external clock signal C by 2 is supplied to the next-stage T flip-flop circuit 2. Is input to

The clock signal CLK output from the T flip-flop circuit 2 is a signal synchronized with the external clock signal C and obtained by dividing the external clock signal C by four.

[0008]

In the clock signal generation circuit configured as described above, the frequency of the external clock signal C cannot be divided by an odd number. Therefore, based on the external clock signal C, the clock signal CL having a desired pulse width
K may not be generated.

When the frequency of the external clock signal C fluctuates, the frequency of the clock signal CLK fluctuates accordingly.
Cannot be generated.

An object of the present invention is to provide a clock signal generating circuit which can synchronize with an external clock signal and stably output a clock signal having a desired frequency.

[0011]

FIG. 1 is a diagram for explaining the principle of claim 1. That is, the input circuit 11 receives the input clock signal C, detects the rise of the input clock signal C, and outputs the detection signal S1. The first pulse width setting circuit 12 outputs a first pulse width setting signal S2 after a predetermined time based on the detection signal S1. Output circuit 1
3 is an output clock signal C based on the detection signal S1.
LK is inverted, and the output clock signal CLK is inverted again based on the first pulse width setting signal S2. The second pulse width setting circuit 14 detects the detection signal S1
And the input circuit 11 is activated after a predetermined time based on the first pulse width setting signal S2, and the input circuit 11 detects the rise of the input clock signal C. A second pulse width setting signal S3 to be output is output.

According to a second aspect of the present invention, the input circuit outputs a logical product of the input clock signal and the second pulse width setting signal. According to claim 3, the first pulse width setting circuit is constituted by a first delay circuit that delays only the rising operation of the detection signal and inverts and outputs the inverted signal as the first pulse width setting signal. The output circuit outputs a logical product of the detection signal and a first pulse width setting signal.

According to a fourth aspect of the present invention, the second pulse width setting circuit delays only the fall of the first pulse width setting signal, and inverts and outputs the second pulse width setting signal; The output signal of the second delay circuit and an AND circuit for outputting a logical AND of the detection signal and the output signal.

According to a fifth aspect of the present invention, the first delay circuit comprises an odd-numbered inverter circuit for delaying and inverting the rise of the detection signal and outputting the inverted signal, and an output signal based on the fall of the detection signal. And a reset circuit for resetting to a high level.

According to a sixth aspect of the present invention, the second delay circuit delays and inverts the first pulse width setting signal and outputs an inverted number of inverter circuits based on the detection signal. And a reset circuit for resetting the signal to L level.

[0016]

According to the first aspect, the H-level pulse width and the L-level pulse width of the clock signal CLK output from the output circuit 13 in synchronization with the input clock signal C are equal to those of the first pulse width setting circuit 12. , And the second pulse width setting circuit 14.

According to the second aspect, when the output signal of the second pulse width setting circuit goes high, the input circuit outputs a signal based on the input clock signal, and the output signal of the second pulse width setting circuit goes low. Then, a signal irrelevant to the input clock signal is output. Therefore, when the output signal of the second pulse width setting circuit is at the H level and the rising of the input clock signal is detected, and based on the detection signal, the output signal of the second pulse width setting circuit becomes the L level, The input circuit is deactivated.

According to the third aspect, when the detection signal output from the input circuit rises to the H level, the clock signal output from the output circuit goes to the H level, and after the delay time of the first delay circuit, the clock signal changes to the L level. Level.

According to a fourth aspect, the input circuit is inactivated based on the delay time of the second delay circuit. Claim 5
In this case, the rise of the detection signal is delayed by an odd-numbered inverter circuit, inverted, and output. The output signal of the first delay circuit is reset to the H level by the reset circuit based on the fall of the detection signal.

According to the present invention, the first pulse width setting signal is delayed and inverted by the odd-numbered inverter circuits by the second delay circuit, and is output when the detection signal becomes H level. Is reset to the L level.

[0021]

FIG. 2 shows a data transfer apparatus according to the present invention. The clock signal generation circuit 3 is configured by an oscillation circuit that oscillates in synchronization with an external clock C input from the outside, and outputs a clock signal CLK to the data generation circuit 4 and the transfer signal generation circuit 5.

The data generation circuit 4 includes a data transfer circuit 6
And generates data based on the clock signal CLK, and outputs the data to the data transfer circuit 6. The transfer signal generation circuit 5 generates a transfer signal TR based on the clock signal CLK, and outputs the transfer signal TR to the data transfer circuit 6 and the latch control circuit 7. When the input transfer signal TR becomes H level, the data transfer circuit 6 transfers the data D input from the data generation circuit 4 to the data latch circuit 8.

The latch control circuit 7 receives a latch control signal LC. The latch control circuit 7 outputs an H level data latch signal DL to the data latch circuit 8 based on the input of the H level transfer signal TR and the H level latch control signal LC.

The data latch circuit 8 latches the data D transferred from the data transfer circuit 6 based on the rise of the data latch signal DL from L level to H level, and outputs it as output data Dout. Output to

A first embodiment of the clock signal generation circuit 3 will be described with reference to FIG. The external clock signal C is input to the inverter circuit 9a, and the output terminal of the inverter circuit 9a, that is, the node N1 is connected to the input terminal of the inverter circuit 9b.

The source of the N-channel MOS transistor forming the inverter circuit 9a is an N-channel MOS transistor.
Connected to ground GND via transistor Tr1,
The node N1 is connected to a power supply Vcc via a P-channel MOS transistor Tr2.

The source of the N-channel MOS transistor forming the inverter circuit 9b is an N-channel MOS transistor.
It is connected to the ground GND via the transistor Tr3. An output terminal of the inverter circuit 9b, that is, a node N2 is connected to an input terminal of the inverter circuit 9c, and an output terminal of the inverter circuit 9c, that is, a node N4.
Is connected to the input terminal of the inverter circuit 9d. Then, a clock signal CLK is output from the output terminal of the inverter circuit 9d.

The node N2 is connected to a power supply Vcc via a P-channel MOS transistor Tr4. The source of the N-channel MOS transistor forming the inverter circuit 9c is connected to the ground GND via the N-channel MOS transistor Tr5. The node N
4 is connected to a power supply Vcc via a P-channel MOS transistor Tr6.

The node N2 is connected to a first delay circuit 10a
Is connected to the input terminal. The first delay circuit 10a is composed of a three-stage inverter circuit, and a node N3 as an output terminal thereof is connected to gates of the transistors Tr5 and Tr6.

The source of the N-channel MOS transistor constituting the last stage inverter circuit of the first delay circuit 10a is connected to the ground GND via the N-channel MOS transistor Tr7. The node N3 includes:
Connected to power supply Vcc via P-channel MOS transistor Tr8. The gates of the transistors Tr7 and Tr8 are
It is connected to the node N2.

Therefore, the inverter circuit 9c and the transistors Tr5 and Tr6 form a NAND circuit, and the node N
When both N2 and N3 become H level, the node N4 becomes L level.
Level, and when at least one of the nodes N2 and N3 goes low, the node N4 goes high.

Node N based on rising of node N2
The falling edge of 3 makes up the first delay circuit 10a.
It is delayed by the operation time of the inverter circuit of the stage. When the node N2 falls, the transistor Tr7 is turned off, and the transistor Tr8 is turned on.
Rises immediately.

The node N3 is connected to an input terminal of the second delay circuit 10b. The second delay circuit 10b has 7
The stages of inverter circuits are serialized. The sources of the N-channel MOS transistors constituting the even-numbered inverter circuit of the second delay circuit 10b are connected to the ground GND via N-channel MOS transistors Tr9, Tr11, Tr13, respectively.

The output terminals of the even-numbered inverter circuits of the second delay circuit 10b are connected to a power supply Vcc via P-channel MOS transistors Tr10, Tr12 and Tr14, respectively. Gates of the transistors Tr9 to Tr14 are connected to the node N1.

Therefore, the AND circuits of the even-numbered stages of the second delay circuit 10b and the transistors Tr9 to Tr14 each constitute a logical AND circuit. When the node N1 is at the H level, the second delay circuit 10b raises the node N5 based on the fall of the node N3 after the operation delay time of the seven-stage inverter circuit. Also,
When the node N1 goes low, the node N5 immediately goes low.
Level.

The output terminal of the second delay circuit 10b, that is, the node N5 is connected to the input terminal of the inverter circuit 9e. An output terminal of the inverter circuit 9e, that is, a node N6, is connected to an input terminal of the inverter circuit 9f. An output terminal of the inverter circuit 9f, that is, a node N7, is connected to gates of the transistors Tr1 to Tr4. Therefore, the inverter circuits 9a and 9b and the transistors Tr1 to Tr4 each constitute a logical AND circuit.

The source of the N-channel MOS transistor forming the inverter circuit 9e is an N-channel MOS transistor.
It is connected to ground GND via a transistor Tr15. The node N6 is connected to a power supply Vcc via a P-channel MOS transistor Tr16. The gates of the transistors Tr15 and Tr16 are connected to the node N1. Therefore, the inverter circuit 9e and the transistors Tr15 and Tr16 form a logical product circuit that outputs the logical product of the nodes N1 and N5.

The source of the N-channel MOS transistor forming the inverter circuit 9f is an N-channel MOS transistor.
It is connected to ground GND via a transistor Tr17. The node N7 is connected to a power supply Vcc via a P-channel MOS transistor Tr18. The gates of the transistors Tr17 and Tr18 are connected to the node N2. Accordingly, the inverter circuit 9f and the transistors Tr17 and Tr18 form a logical product circuit that outputs the logical product of the nodes N2 and N6.

Next, the operation when the external clock signal C having the pulse width t1 is input to the clock signal generation circuit 3 configured as described above will be described with reference to FIG. When the external clock signal C is at the L level, the node N1 goes to the H level, the transistors Tr9, Tr11, Tr13, Tr15 are turned on, and the transistors Tr10, Tr112, Tr14, Tr1 are turned on.
6 is turned off.

Since the node N7 is at the H level, the operation of the inverter circuit 9b turns the node N2 to the L level, turning on the transistor Tr18 and turning off the transistor Tr17.

The node N3 is at the H level and the node N4
Goes high, and the clock signal CLK output from the inverter circuit 9d goes low. Node N
Since node 3 is at H level, node N5 is at L level and node N6 is at H level.

Next, when the external clock signal C rises to the H level, the node N1 falls to the L level, and the node N2 rises to the H level. Then, the transistor Tr17 is turned on and the transistor Tr18 is turned off. Since the node N6 is at H level, the node N7 is at L level and the node N1 is returned to H level.

When the node N2 rises to the H level, the node N3 falls to the H level, so that the node N4 falls to the L level and the clock signal CLK rises to the H level.

After the operation delay time t2 of the first delay time 10a from the rise of the node N2, the node N3 falls to the L level. Then, the node N4 rises and the clock signal CLK falls. Therefore, the clock signal CLK becomes H level in the time width t2.

When node N3 falls to L level, node N1 is maintained at H level and transistors Tr9, Tr9,
Since Tr11, Tr13 and Tr15 are on, the node N5 rises after the delay time t3 of the second delay circuit 10b. Then, the node N6 falls and the node N
7 rises.

When node N7 rises, node N2 falls and node N3 rises because node N1 is maintained at the H level. Then, in this state, the next rising of the external clock signal C is captured, the node N1 goes to the L level, and the above operation is repeated.

Next, a pulse width t4 longer than the pulse width t1 is supplied to the clock signal generation circuit 3 configured as described above.
The operation when the external clock signal C is input will be described with reference to FIG.

The operation in which the clock signal CLK rises in response to the rise of the external clock signal C and the clock signal CLK goes high with a pulse width t2 based on the delay time of the first delay circuit 10a is the same as that in FIG. is there.

Then, after the delay time t3 of the second delay circuit 10b from the fall of the node N3, the node N5 rises to the H level, the node N7 rises to the H level, and the node N2 goes to the L level.

Then, upon catching the next rising of external clock signal C, node N1 goes low and the above operation is repeated. Therefore, even if the frequency of the external clock signal C fluctuates, the H-level pulse width t2 of the clock signal CLK is kept constant by the delay time of the first delay circuit 10a.

Since the L level pulse width of the clock signal CLK is determined by the delay time of the second delay circuit 10b and the rising timing of the external clock signal C, the delay of the second delay circuit 10b If the time t3 is longer than the pulse width t4 of the external clock signal C, there is no large fluctuation.

As described above, the clock signal generation circuit 3
Then, the clock signal CLK rises based on the rising of the external clock signal C, and the clock signal CLK
Is set by the first delay circuit 10a.

After the clock signal CLK falls due to the operation of the first delay circuit 10a, the second delay circuit 10a
It becomes L level based on the delay time t3 set by b. Accordingly, the time widths of the H level and the L level of the clock signal CLK are set by the first and second delay circuits 10a, so that the clock signal having a stable pulse width regardless of the fluctuation of the frequency of the external clock signal C. CLK can be generated.

Also, by appropriately setting the delay times of the first and second delay circuits 10a by simulation, the clock signal CLK can be output at a frequency obtained by dividing the external clock signal C by an odd number.

The stable clock signal CLK can be supplied from the clock signal generation circuit 3 to the transfer signal generation circuit 5 and the data generation circuit 4. FIG.
Shows a second embodiment of the clock signal generation circuit. This embodiment differs from the first embodiment in the configuration of the first and second delay circuits 10a and 10b.

That is, in this embodiment, in the first and second delay circuits 10a and 10b of the first embodiment, the N-channel MOS transistor connected to the inverter circuit forming the AND circuit is omitted. .

With such a configuration, the operation is the same as in the first embodiment. Since the number of transistors can be reduced as compared with the first embodiment, the circuit layout area can be reduced.

Further, the first delay circuit 10 of the second embodiment
a, the P-channel M of the odd-numbered inverter circuit
If the gate width of the OS transistor is made, for example, about 10 times larger than the gate width of the N-channel MOS transistor, and the reverse of the even-numbered inverter circuit, the node N2
Fall of the node N3 based on the rise of the node N3 is sufficiently delayed, and the node N3 falls based on the fall of the node N2.
Can be configured quickly.

Further, the second delay circuit 10 of the second embodiment
b, the P-channel M of the odd-numbered inverter circuit
If the gate width of the OS transistor is made smaller than the gate width of the N-channel MOS transistor and the even-numbered inverter circuit is reversed, the rise of the node N5 based on the fall of the node N3 is sufficiently delayed, and the node N1
, A delay circuit in which the node N5 rises immediately on the basis of the falling edge can be configured.

The technical ideas other than the claims that can be grasped from the above embodiment will be described below together with their effects. (1) The reset circuit of the first delay circuit according to claim 5, wherein the reset circuit of the first delay circuit includes an N-channel MOS transistor connected between a source of an N-channel MOS transistor of a final-stage inverter circuit and a ground GND; It comprises a P-channel MOS transistor connected between the output terminal of the circuit and the power supply Vcc, and inputs the detection signal to each of the transistors. When the detection signal goes to L level, a reset circuit that immediately sets the output signal of the first delay circuit to H level can be easily configured.

(2) In the fifth and sixth aspects, the reset circuit of the first delay circuit includes a P-channel MOS transistor connected between the output terminal of the last-stage inverter circuit and the power supply Vcc. The detection signal is input, and the gate width of the transistor on the reset operation side of each inverter circuit is increased. When the detection signal goes low, the reset circuit that immediately sets the output signal of the first delay circuit to the high level can be configured with a small layout area.

[0062]

As described above in detail, according to the first aspect of the present invention, it is possible to provide a clock signal generating circuit which can synchronize with an external clock signal and stably output a clock signal having a desired frequency. .

According to the second aspect, an input circuit that detects only the rising of the input clock signal based on the output signal of the second pulse width setting circuit can be configured. According to the third aspect, the H level pulse width of the clock signal output from the output circuit can be set by the delay time of the first delay circuit.

According to the fourth aspect, the L-level pulse width of the clock signal output from the output circuit can be set by the delay time of the second delay circuit. According to the fifth and sixth aspects, by appropriately selecting the number of stages of the inverter circuits of the first and second delay circuits, the frequency division ratio with respect to the input clock signal can be arbitrarily set.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a data transfer device.

FIG. 3 is a circuit diagram showing a first embodiment of a clock signal generation circuit.

FIG. 4 is a timing waveform chart showing the operation of FIG.

FIG. 5 is a timing waveform chart showing the operation of FIG.

FIG. 6 is a circuit diagram showing a second embodiment of the clock signal generation circuit.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a timing waveform chart showing the operation of the conventional example.

[Explanation of symbols]

11 Input circuit 12 First pulse width setting circuit 13 Output circuit 14 Second pulse width setting circuit C input clock signal S1 detection signal S2 First pulse width setting signal S3 Second pulse width setting signal

Continuation of the front page (56) References JP-A-2-296410 (JP, A) JP-A-6-45891 (JP, A) JP-A-5-14151 (JP, A) JP-A-3-69294 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 5/04

Claims (6)

(57) [Claims] 1. An input circuit for receiving an input clock signal, detecting a rise of the input clock signal and outputting a detection signal, and outputting a first pulse width setting signal after a predetermined time based on the detection signal. A first pulse width setting circuit, and inverting an output clock signal based on the detection signal;
An output circuit that inverts the output clock signal again based on the first pulse width setting signal, and inactivates the input circuit based on the detection signal, based on the first pulse width setting signal, A second pulse width setting circuit that outputs a second pulse width setting signal that activates the input circuit after a predetermined time and detects a rise of the input clock signal in the input circuit. Signal generation circuit. 2. The clock signal generation circuit according to claim 1, wherein the input circuit outputs a logical product of the input clock signal and the second pulse width setting signal. 3. The first pulse width setting circuit includes a first delay circuit that delays and inverts only a rising operation of the detection signal and outputs the first pulse width setting signal as the first pulse width setting signal. 2. The clock signal generation circuit according to claim 1, wherein the output circuit outputs a logical product of the detection signal and a first pulse width setting signal. 4. The second pulse width setting circuit, wherein the second pulse width setting circuit delays only the falling edge of the first pulse width setting signal and outputs the inverted signal after inverting the second pulse width setting signal. 2. The clock signal generation circuit according to claim 1, further comprising: an AND circuit that outputs a logical product of the output signal and the detection signal. 5. An odd-numbered stage inverter circuit for delaying and inverting the rise of the detection signal and outputting the output signal to an H level based on the fall of the detection signal. 4. The clock signal generation circuit according to claim 3, comprising a reset circuit for resetting. 6. An odd-numbered inverter circuit that delays and inverts the first pulse width setting signal and outputs the first pulse width setting signal, and outputs an L level signal based on the detection signal. 5. The clock signal generation circuit according to claim 4, further comprising a reset circuit for resetting the clock signal.