JPH098148A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a MOS transistor which can suppress the sheet resistance of a gate electrode from being increased, which can suppress a current driving capability from being lowered and which is of a titanium silicide structure. CONSTITUTION: A titanium film 141a is formed, and titanium silicide films 111a, 111b are formed on the surface of gate electrodes 107a, 107b. An oxide silicon film 136 is removed by RIE. A titanium film 141b is formed, titanium silicide films 111ab, 111bb are formed on the surface of an N-type source-drain region 109 and a P-type source-drain region 110, and the titanium silicide films 111a, 111b are changed into titanium silicide films 111aa, 111ba.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a MOS transistor having a titanium salicide structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, in semiconductor devices including MOS transistors, the gate length (of the gate electrode made of a polycrystalline silicon film), source / drain regions, etc. of the MOS transistors are also reduced. In order to suppress the increase in the sheet resistance of the gate electrode and the source / drain regions due to the result, a titanium salicide structure MOS in which a titanium silicide film is provided in a self-aligned manner on the upper surface of the gate electrode and the surface of the source / drain region. Transistors are attracting attention. Further, particularly in a miniaturized P-channel MOS transistor having a gate length of 0.35 μm or less, the gate electrode tends to be formed of a high-concentration P-type polycrystalline silicon film.

Referring to FIGS. 5 and 6 which are schematic cross-sectional views of a manufacturing process of a semiconductor device, a conventional CMOS transistor in which both an N-channel MOS transistor and a P-channel MOS transistor have a titanium silicide structure is as follows. Is formed.

First, N is formed on the surface of the P-type silicon substrate 301.
A well 302 and a P well 303 are formed. N well 3
02, P-well 303 has a junction depth of 1.0
It is about μm. In the element isolation region on the surface of the P-type silicon substrate 301, a field oxide film 304 having a film thickness of about 400 nm is formed by selective oxidation. In addition, P well 3
In the element isolation region on the surface of 03, the field oxide film 30
Immediately below 4, a P-type diffusion layer 305 for a channel stopper is formed by ion implantation of 10 ¹³ cm ⁻² boron or the like. In the element isolation region on the surface of the P-type silicon substrate 301, the gate oxide film 3 with a film thickness of about 10 nm is formed by thermal oxidation.
06 is formed. A film thickness of 250 is formed on the entire surface by the vapor phase growth method.
A non-doped polycrystalline silicon film 327 of about nm is formed [FIG. 5 (a)].

Next, the polycrystalline silicon film 327 is patterned to form a polycrystalline silicon film pattern 327a on the surface of the N well 302 and the P well 303 in which the gate electrode is to be formed. Polycrystalline silicon film pattern 32
The width of 7a is about 0.35 μm. N well 302
A low-concentration N film is formed on the surface of the P-well 303 by ion implantation of 10 ¹⁴ cm ⁻² boron using a photoresist film (not shown) covering the film, the field oxide film 305 and the polycrystalline silicon film pattern 327a as a mask. Type diffusion layer 329
To form Further, another photoresist film (not shown) covering the P well 303, the field oxide film 305 and the polycrystalline silicon film pattern 327a are used as a mask 1
The N well 30 is formed by ion implantation of 0 ¹⁴ cm ^-2 phosphorus.
A low concentration P-type diffusion layer 330 is formed on the surface of No. 2. A silicon oxide film (not shown in the drawing) having a film thickness of about 100 nm is formed on the entire surface by a vapor phase growth method, and the silicon oxide film is etched back to form a silicon oxide film spacer 308 on the side surface of the polycrystalline silicon film pattern 327a. Form. The distance between the silicon oxide film spacer 308 and the field oxide film 304 is about 0.5 μm (FIG. 5B).

Next, ion implantation of boron difluoride (BF ₂ ) of about 5 × 10 ¹⁵ cm ⁻² is performed with a photoresist film (not shown) covering the P well 303 as a mask, and the N well 3 is used.
Arsenic ion implantation of about 5 × 10 ¹⁵ cm ⁻² using another photoresist film (not shown) covering 02 as a mask, and
A heat treatment or the like at about 00 ° C. to 850 ° C. is performed. By this series of processes, on the P well 303 side, a high-concentration N type diffusion layer 339 self-aligned with the field oxide film 305 and the silicon oxide film spacer 308 is formed on the surface of the P well 303, and the N type diffusion layer is formed. An N-type source / drain region 309 composed of 329 and an N-type diffusion layer 339 is formed. The junction depth of the N-type diffusion layer 339 is about 0.1 μm. Further, the polycrystalline silicon film pattern 327a on the surface of the P well 303 also becomes a high-concentration N type and is made of this (the gate length is about 0.35 μm) The gate electrode 307a.
Is formed. On the N well 302 side, a high concentration P-type diffusion layer 339 self-aligned with the field oxide film 305 and the silicon oxide film spacer 308 is formed on the surface of the N well 302, and the P-type diffusion layer 330 and the P-type diffusion layer are formed. A P-type source / drain region 310 composed of 340 is formed.
The junction depth of the P-type diffusion layer 340 is about 0.15 μm. The polycrystalline silicon film pattern 327a on the surface of the N well 302 also becomes a high-concentration P type, and a gate electrode 307b (having a gate length of about 0.35 μm) is formed (FIG. 5C).

Next, ion implantation of silicon of about 1 × 10 ¹⁵ cm ^-2 is performed on the entire surface to form gate electrodes 307a, 30.
An amorphous layer of silicon (not shown in the drawing) is formed near the upper surface of 7b, near the surface of the N-type source / drain region 309, and near the surface of the P-type source / drain region 310.
The natural oxide films on the upper surfaces of the gate electrodes 307a and 307b, the surfaces of the N-type source / drain regions 309 and the P-type source / drain regions 310 are removed. A titanium film 341 having a film thickness of about 50 nm is formed on the entire surface by sputtering [FIG. 5 (d)].

Next, heat treatment (rapid thermal nitriding treatment; RTN) is performed for about 30 seconds in a nitrogen atmosphere at about 700 ° C.,
C is self-aligned on the upper surfaces of the gate electrodes 307a and 307b.
Titanium silicide film 311aa, 311b having 49 structure
a is formed, and the surface of the N-type source / drain region 309 and the surface of the P-type source / drain region 310 that are self-aligned with the field oxide film 305 and the silicon oxide film spacer 308 are each formed of a titanium silicide film 31 having a C49 structure.
1ab and 311bb are formed. The titanium / silicide films 311aa, 311ab, 311ba, 311bb each have a film thickness of about 50 nm, and a titanium nitride film (not shown) having a film thickness of about 25 nm on each of these surfaces.
Are formed. Further, the surfaces of the field oxide film 305 and the silicon oxide film spacer 308 are mainly covered with the silicon nitride film, and the unreacted titanium film 341 may remain in the portions which are in direct contact with these surfaces. Ammonia (NH ₄ OH) water and hydrogen peroxide (H ₂ O
₂ ) The titanium nitride film and the unreacted titanium film 341 are removed by a mixed solution with water [FIG. 6 (a)].

Next, RT at 850 ° C. for about 10 seconds
Titanium silicide film 311aa, 311
ab, 311ba, and 311bb are titanium silicide films 312aa, 312ab, and 312 having a C54 structure, respectively.
phase transition to ba and 312bb. This completes the formation of the titanium salicide CMOS transistor [FIG. 6 (b)]. Although illustration is omitted, after that, an interlayer insulating film, a contact hole, a metal wiring, etc. are formed to form a semiconductor device including the CMOS transistor.

[0010]

However, the above-mentioned C
The MOS transistor has two problems that have an antinomy relation. These two problems are caused by the titanium film 341.
Related to the film thickness of the titanium silicide films 311aa, 311aa, 3
This is due to the film thickness of 11ab, 311ba, and 311bb.

The first problem occurs when the titanium film 341 becomes thin. Gate electrodes 307a and 307b
When the gate length of the titanium film 341 is reduced to about 0.35 μm and the film thickness of the titanium film 341 becomes about 30 nm, the titanium silicide films 311aa and 311ba having the C49 structure are changed to C5.
Titanium / silicide film 312aa, 312ba of four structure
Aggregation starts to occur at the time of phase transition, and the sheet resistance of the obtained titanium-silicide films 312aa and 312ba becomes higher than the sheet resistance of the titanium-silicide films 312aa and 312ba. This tendency becomes more remarkable as the film thickness of the titanium film 341 becomes thinner, and becomes more remarkable as the gate length becomes shorter than 0.35 μm. Therefore, it is possible to achieve the purpose of suppressing the increase of the sheet resistance of the gate electrode, which is the purpose of making the gate electrode (having a short gate length) a titanium polycide structure.
This problem can be solved by increasing the thickness of the titanium film 341 (thickness of the titanium / silicide films 311aa and 311ab) to more than 30 nm if the gate length is about 0.35 μm. Note that the problem of aggregation at the time of phase transition to C54 is caused by the N-type source / drain region 30.
9 also occurs on the surface of the P-type source / drain region 310, but as described above, their width is, for example, 0.5.
The titanium film 341 can be made as wide as about μm.
This phenomenon does not become apparent unless the film thickness of is less than 30 nm.

The second problem occurs when the titanium film 341 becomes thicker. When the thickness of the titanium film 341 is about 35 nm when the depth of the junction between the source / drain regions is about 0.1 to 0.15 μm, between the titanium / silicide film 312ab and the N-type source / drain region 309. Contact resistance, titanium silicide film 312bb and P
The contact resistance between the mold source / drain region 310 starts to increase. For this reason, the current drive capability of the N-channel MOS transistor and the current drive capability of the P-channel MOS transistor start to decrease. This tendency becomes remarkable as the titanium film becomes thicker. This phenomenon is because when the titanium film 341 is changed to a titanium / silicide film having a C49 structure, conductive impurities near the interface between the source / drain region and the titanium film 341 are diffused into the titanium / silicide film having a C49 structure. It is considered that the impurity concentration near these interfaces decreases (depletes). Further, this phenomenon is particularly remarkable in the P-type source / drain region 310. This phenomenon occurs with the silicidation reaction and does not occur when the titanium / silicide film undergoes a phase transition from the C49 structure to the C54 structure. This problem is solved by making the thickness of the titanium film 341 thinner than 35 nm.

This phenomenon also occurs on the upper surface of the gate electrode. However, in the titanium / polycide structure gate electrode, the titanium / silicide film 312ab is used.
To the gate electrode 307a through the gate electrode 307a or the titanium silicide film 312bb
Since there is no current path through b, the actual damage is reduced by setting the film thickness of the polycrystalline silicon film 327 to a desired value larger than the junction depth of the source / drain regions.

Therefore, an object of the present invention is to provide a semiconductor device including a MOS transistor of titanium salicide structure, which has a structure capable of suppressing an increase in the sheet resistance of the gate electrode and a decrease in the current driving capability, and manufacturing. It is to provide a manufacturing method capable of forming this semiconductor device with a margin.

[0015]

According to the present invention, there is provided a semiconductor device comprising:
A silicon substrate having one conductivity type region provided on at least a part of the surface, and a gate electrode formed of a polycrystalline silicon film having a desired film thickness provided on the surface of the one conductivity type region through a gate oxide film. An insulating film spacer that covers the side surface of the gate electrode, a first titanium-silicide film having a first required thickness and having a C54 structure that covers the upper surface of the gate electrode in a self-aligned manner, and the one conductive film. The reverse conductivity type source / drain regions provided on the surface of the mold region and the insulation film spacer are self-aligned and have a second required film thickness smaller than the first required film thickness. And a second titanium / silicide film having a C54 structure covering the surface of the source / drain region.

Preferably, the insulating film forming the insulating film spacer is a silicon oxide film or a silicon nitride film.

According to a first aspect of the method for manufacturing a semiconductor device of the present invention, a field insulating film is formed in an element isolation region of a surface of a silicon substrate having one conductivity type region provided on at least a part of the surface, A step of forming a gate oxide film in a device forming region on the approximate surface, a step of forming a polycrystalline silicon film of a desired film thickness directly covering the surface of the gate oxide film, and a step of forming at least the polycrystalline silicon film. At least the polycrystalline silicon film is formed by patterning the film and leaving at least the polycrystalline silicon film pattern in the region where the gate electrode is to be formed, and forming an insulating film of a predetermined thickness on the entire surface and etching back the insulating film. The step of forming an insulating film spacer on the side surface of the pattern and the above-described one self-alignment with at least the field insulating film and the insulating film spacer by thermal oxidation. The polycrystalline silicon film pattern is converted into a gate electrode by a step of forming a silicon oxide film on the surface of the conductivity type region and ion implantation of impurities of the opposite conductivity type, and a source of the opposite conductivity type is formed on the surface of the one conductivity type region. A step of forming a drain region, a step of exposing the upper surface of the gate electrode, a step of forming a first titanium film on the entire surface, and a first heat treatment in a nitrogen atmosphere to expose the upper surface of the gate electrode. Forming a first titanium-silicide film having a C49 structure that covers in a self-aligning manner, and selectively removing the first titanium nitride film and the unreacted first titanium film, and anisotropy to the silicon oxide film At least the silicon oxide film is removed by reactive etching to expose the surface of the reverse conductivity type source / drain region that is self-aligned with the field insulating film and the insulating film spacer. And a step of forming a second titanium film on the entire surface, and a second heat treatment in a nitrogen atmosphere is performed to increase the thickness of the first titanium / silicide film having a C49 structure. And a second C49 structure on the surface of the opposite conductivity type source / drain region self-aligned with the insulating film spacer.
Of the titanium / silicide film and selectively removing the second titanium nitride film and the unreacted second titanium film, and a third heat treatment in a nitrogen atmosphere are performed.
The above-mentioned first and second titanium-silicide films of the structure are C54
And a step of causing a phase transition to the first and second titanium-silicide films of the structure.

According to a second aspect of the method for manufacturing a semiconductor device of the present invention, a field insulating film is formed in an element isolation region of a surface of a silicon substrate having at least a part of the surface provided with one conductivity type region, A step of forming a gate oxide film in the device forming region on this surface, a step of sequentially forming a non-doped polycrystalline silicon film having a desired film thickness and a silicon nitride film on the entire surface, the silicon nitride film and polycrystalline silicon A step of sequentially patterning the film to leave a silicon nitride film pattern and a polycrystalline silicon film pattern in a region for forming a gate electrode, and forming a first silicon oxide film with a predetermined film thickness on the entire surface, The silicon film is etched back to form a silicon oxide film spacer on the side surface of the silicon nitride film pattern and the polycrystalline silicon film pattern, and A step of forming an exposed surface of the one conductivity type region self-aligned with the edge film and the silicon oxide film spacer; a step of forming a second silicon oxide film on the exposed surface by thermal oxidation; The polycrystalline silicon film pattern is converted into a reverse conductivity type polycrystalline silicon film pattern by ion implantation of impurities to form a gate electrode, and a reverse conductivity type source / drain region is formed on the surface of the one conductivity type region. A step of selectively removing the silicon nitride film pattern, a step of forming a first titanium film on the entire surface, and a first heat treatment in a nitrogen atmosphere to perform self-alignment on the upper surface of the gate electrode. Forming a first titanium-silicide film having a C49 structure covering the first titanium nitride film and selectively removing the first titanium nitride film and the unreacted first titanium film, and anisotropic etching. The step of removing the second silicon oxide film, the step of forming a second titanium film on the entire surface, and the second heat treatment in a nitrogen atmosphere to perform the film of the first titanium-silicide film having a C49 structure. A second titanium / silicide film having a C49 structure is formed on the surface of the reverse conductivity type source / drain region which is self-aligned with the field insulating film and the silicon oxide film spacer to form a second titanium nitride film. A step of selectively removing the film and the unreacted second titanium film and a third heat treatment in a nitrogen atmosphere are performed to replace the first and second titanium silicide films of the C49 structure with those of the C54 structure. And a step of undergoing a phase transition to a second titanium / silicide film.

Preferably, the etching back of the first silicon oxide film for forming the silicon oxide film spacer is performed by trifluoromethane (CH 3).
This is anisotropic etching using a mixed gas of F ₃ ) and carbon monoxide (CO) or a mixed gas of octafluorobutane (C ₄ F ₈ ) and carbon monoxide as an etching gas. Further, anisotropic etching for removing the second silicon oxide film is performed by using a mixed gas of CHF ₃ and CO, or C ₄ F ₈ and CO.
Is an anisotropic etching using a mixed gas consisting of

According to a third aspect of the method for manufacturing a semiconductor device of the present invention, a field insulating film is formed in an element isolation region on the surface of a silicon substrate having a surface of one conductivity type region, and a gate is formed in the element formation region. A step of forming an oxide film, a step of forming a non-doped polycrystalline silicon film having a desired film thickness on the entire surface, a patterning of the polycrystalline silicon film, and leaving a polycrystalline silicon film pattern in the gate electrode formation planned region. A step of forming a silicon nitride film of a predetermined thickness on the entire surface, etching back the silicon nitride film to form a silicon nitride film spacer on the side surface of the polycrystalline silicon film pattern, and by thermal oxidation, A first surface is formed on the upper surface of the polycrystalline silicon film pattern, on the surface of the field insulating film, and on the surface of the one conductivity type region that is self-aligned with the silicon nitride film spacer. And a step of forming a second silicon oxide film, and ion implantation of an impurity of opposite conductivity type converts the polycrystalline silicon film pattern into a polycrystalline silicon film pattern of opposite conductivity type to form a gate electrode. A step of forming source / drain regions of opposite conductivity type on the surface of the conductivity type region, a photoresist film is applied and formed on the entire surface, and the photoresist film is etched back until the upper surface of the first silicon oxide film is exposed. Then, the step of removing the first silicon oxide film, the step of forming the first titanium film on the entire surface, and the first heat treatment in a nitrogen atmosphere are performed to cover the upper surface of the gate electrode in a self-aligned manner. A step of forming a first titanium / silicide film having a C49 structure and selectively removing the first titanium nitride film and the unreacted first titanium film and anisotropic etching are performed. A step of removing at least the second silicon oxide film to expose the surface of the reverse conductivity type source / drain region self-aligned with the field insulating film and the silicon nitride film spacer; To increase the thickness of the first titanium / silicide film having a C49 structure, and to form C on the surface of the reverse conductivity type source / drain region self-aligned with the field insulating film and the silicon nitride film spacer.
A second titanium silicide film having a 49 structure is formed, and a second titanium silicide film is formed.
The step of selectively removing the titanium nitride film and the unreacted second titanium film described above and a third heat treatment in a nitrogen atmosphere are performed to remove the first and second titanium silicide films having a C49 structure by C54. And a step of causing a phase transition to the first and second titanium-silicide films of the structure.

Preferably, the etching back of the silicon nitride film for forming the silicon nitride film spacer is performed by etching difluoro methane (CH ₂ F ₂ ) or fluoro methane (CH ₃ F) as an etching gas. This is the anisotropic etching used for. In addition, anisotropic etching for removing the silicon oxide film covering the surface of the opposite conductivity type source / drain region is performed by CHF ₃ and C.
This is anisotropic etching using a mixed gas of O or a mixed gas of C ₄ F ₈ and CO as an etching gas.

[0022]

Next, the present invention will be described with reference to the drawings.

Referring to FIGS. 1 and 2 which are schematic cross-sectional views of a manufacturing process of a semiconductor device, a first embodiment of the present invention will be described.
It is a semiconductor device including a CMOS transistor having a titanium salicide structure according to the 0.35 μm design rule, and is formed as follows.

First, N is formed on the surface of the P-type silicon substrate 101.
A well 102 and a P well 103 are formed. N well 1
The junction depth of 02 and the depth of the P well 103 are respectively
It is about 1.0 μm. Surface of P-type silicon substrate 101
About 400 nm in film thickness is formed by selective oxidation in the element isolation region of
Then, the field oxide film 104 is formed. In addition, P-way
In the element isolation region on the surface of
10 just below 104¹³ cm^-2Ion implantation of boron etc.
The P-type diffusion layer 105 for the channel stopper
Form. Element isolation region on the surface of the P-type silicon substrate 101
Gate oxide film with a thickness of about 10 nm by thermal oxidation
Form 106. A film thickness of 25 is formed on the entire surface by the vapor phase growth method.
Form a non-doped polycrystalline silicon film 127 of about 0 nm
Further, by a vapor deposition method, a film thickness of about 10 nm is formed on the entire surface.
Then, a silicon nitride film 128 is formed [FIG. 1 (a)].
The field insulating film in this embodiment is LOCOS.
Type field oxide film 104, but is not limited to this.
Not something. For example, a groove isolation method is used in the element isolation region.
If adopted, the field insulating film fills this groove
Becomes an insulating film. In addition, in this embodiment, non-doped
The polycrystalline silicon film 127 of
Alternatively, a high-concentration N-type polycrystalline silicon film may be used.

Next, the silicon nitride film 128 and the polycrystalline silicon film 127 are sequentially patterned to form the N well 102.
In addition, a silicon nitride film pattern 128a and a polycrystalline silicon film pattern 127a are formed on the surface of the P well 103 where the gate electrode is to be formed, respectively. It is preferable to pattern the polycrystalline silicon film 127 by anisotropic etching by reactive ion etching (RIE) using HBr as an etching gas. Since the gate oxide film 106 is not removed by this RIE, there is no need to perform reoxidation prior to ion implantation in the next step. The width of the polycrystalline silicon film pattern 127a is 0.
It is about 35 μm. A photoresist film (not shown) covering the N well 102, the field oxide film 105 and the polycrystalline silicon film pattern 127a are used as a mask for 10 ¹⁴
cm ⁻² boron ion implantation etc.
A low concentration N-type diffusion layer 129 is formed on the surface of No. 3. Further, another photoresist film (not shown) covering the P well 103, the field oxide film 105 and the polycrystalline silicon film pattern 127a are used as a mask to implant 10 ¹⁴ cm ⁻² of phosphorus ions, etc. A low concentration P-type diffusion layer 130 is formed on the surface of the substrate [FIG. 1 (b)].

Next, a silicon oxide film (HTO film) having a film thickness of about 100 nm is formed on the entire surface by, eg, high temperature vapor phase epitaxy, and the silicon oxide film is etched back to form a silicon nitride film pattern 128a and a polycrystalline silicon film. A silicon oxide film spacer 118 is formed on the side surface of the pattern 127a. By this etch back (details will be described later), the portion of the gate oxide film 106 not covered by the silicon oxide film spacer 108 is removed by etching. The distance between the silicon oxide film spacer 108 and the field oxide film 104 is about 0.5 μm. At the time of this etch back, the silicon nitride film pattern 128a must be left. Therefore, this etch back is required to be anisotropic dry etching in which the etching rate of the silicon oxide film is sufficiently higher than the etching rate of the silicon nitride film. Therefore, this etchback is preferably RIE using a mixed gas of CHF ₃ and CO or a mixed gas of C ₄ F ₈ and CO as an etching gas. RIE above
Then, due to the presence of CO, reaction products tend to be deposited on the surface of the film other than the silicon oxide film, and the etching of these films is suppressed. On the other hand, it becomes difficult for reaction products to deposit on the surface of the silicon oxide film, and the etching of the silicon oxide film proceeds selectively [Fig.
(C)].

Next, thermal oxidation is performed in a dry oxygen atmosphere at about 900 ° C., and the surface of the N-type diffusion layer 129 and the surface of the P-type diffusion layer 130 which are self-aligned with the field oxide film 104 and the silicon oxide film spacer are respectively formed. Film thickness 30nm
A silicon oxide film 136 is formed to a certain degree [FIG.
(D)]. By this thermal oxidation, a silicon oxide film spacer 1
The width (thickness) of 08 is slightly increased, but the value is in the 1 nm range.

Next, using a photoresist film (not shown) covering the N well 102 as a mask, ion implantation of arsenic of about 3 × 10 ¹⁵ cm ^-2 is performed at about 70 KeV, and after removing this photoresist film. The heat treatment is performed in a nitrogen atmosphere at about 900 ° C. for about 10 minutes. As a result, on the P well 103 side, a high-concentration N type diffusion layer 139 self-aligned with the field oxide film 105 and the silicon oxide film spacer 108 is formed on the surface of the P well 103, and the N type diffusion layer 129 and the N type diffusion layer 129 are formed. N-type source consisting of the type diffusion layer 139.
The formation of the drain region 109 is completed. N-type diffusion layer 13
The junction depth of No. 9 is about 0.1 μm. In addition, the polycrystalline silicon film pattern 127 a on the surface of the P well 103
Also becomes a high-concentration N-type and consists of this (gate length 0.3
The formation of the gate electrode 107a (about 5 μm) is completed.
The reason why the dose of arsenic is lower than that of the conventional method is that the titanium / silicide film is formed smoothly. When the arsenic concentration in the N-type diffusion layer 139 and the gate electrode 107a is too high, the silicidation reaction for forming the titanium / silicide film is suppressed.

Next, another photoresist film (not shown) covering the P well 103 is used as a mask to form a mask of 5 × 10 ¹⁵ cm.
Ion implantation of boron difluoride (BF ₂ ) of about ^-2 to 70K
After eV, the photoresist film is removed and then heat treatment is performed at 850 ° C. for about 10 minutes. As a result, on the N well 102 side, the field oxide film 10 is formed.
5 and a silicon oxide film spacer 108, a high-concentration P-type diffusion layer 139 is formed on the surface of the N well 102, and a P-type source / drain including a P-type diffusion layer 130 and a P-type diffusion layer 140 is formed. The formation of the region 110 is completed. P
The junction depth of the mold diffusion layer 140 is about 0.15 μm. The polycrystalline silicon film pattern 127a on the surface of the N well 102 also becomes a high-concentration P type, and the formation of the gate electrode 107b (having a gate length of about 0.35 μm) is completed. There is also a method of forming the silicon oxide film 136 after forming the N-type diffusion layer 109, the P-type diffusion layer 110, etc., but in this case, the N-type diffusion layer 1 is formed.
The film thickness of the silicon oxide film formed on the surface of 09 is about twice the film thickness of the silicon oxide film formed on the surface of the P-type diffusion layer 110, which causes a problem in a later process.

Next, the silicon nitride film pattern 128a covering the upper surfaces of the gate electrodes 107a and 107b is removed by wet etching with hot phosphoric acid, for example. 1 x
Ion implantation of silicon of about 10 ¹⁵ cm ^-2 is performed at 70 KeV.
The polycrystalline silicon in the vicinity of the upper surfaces of the gate electrodes 107a and 107b is amorphized by performing the annealing to about a certain degree. The purpose of this is
It is aimed at promoting and homogenizing the silicidation reaction. Instead of silicon ion implantation, arsenic ion implantation of about 3 × 10 ¹⁴ cm ⁻² may be performed at about 70 KeV. If the above-mentioned ion implantation is performed without removing the silicon nitride film pattern 128a, the above-mentioned amorphization becomes difficult to occur. After removing the natural oxide film on the upper surfaces of the gate electrodes 107a and 107b, a titanium film 141a having a thickness of about 30 nm is formed on the entire surface by sputtering [FIG. 2 (a)].

Next, RT at about 700 ° C. for about 30 seconds
N, and the titanium / silicide film 111 having a C49 structure is self-aligned with the upper surfaces of the gate electrodes 107a and 107b.
a and 111b are formed. Titanium silicide film 111
The film thicknesses of a and 111a are around 30 nm,
A titanium nitride film (not shown) having a film thickness of about 15 nm is formed on each of these surfaces. Further, the surfaces of the field oxide film 105, the silicon oxide film 136 and the silicon oxide film spacer 108 are mainly covered with the silicon nitride film, and the unreacted titanium film 141a may remain in the portions which are in direct contact with these surfaces. . The titanium nitride film and the unreacted titanium film 141a are removed by a mixed solution of ammonia (NH ₄ OH) water and hydrogen peroxide (H ₂ O ₂ ) water. In this embodiment, the gate electrode 107
Insulating film (silicon nitride film pattern 128a) covering the upper surfaces of a and 107b and N-type source / drain regions 109 and P
Since the insulating film (silicon oxide film 136) covering the surface of the source / drain region 110 is made different,
As described above, it becomes possible to form the titanium / silicide films 111a and 111a only on the upper surfaces of the gate electrodes 107a and 107b.

Subsequently, for example, by RIE using a mixed gas of CHF ₃ and CO or a mixed gas of C ₄ F ₈ and CO as an etching gas, N-type source / drain regions 109 and P-type source / drain regions are formed. 1
The silicon oxide film 136 on the surface 10 is removed. This RI
At the time of E, the field oxide film 104 is also etched and the film thickness becomes slightly thin.
a and 111b are not etched [FIG. 2 (b)].

Next, the N-type source / drain regions 109,
In order to amorphize the single crystal silicon near the surface of the P-type source / drain region 110, the same ion implantation of silicon as described above is performed to remove the natural oxide film on these surfaces. In this case, it is not preferable to remove the natural oxide film by wet etching. Then, a titanium film 1 having a thickness of about 30 nm is formed on the entire surface by sputtering.
41b is formed [FIG.2 (c)].

Next, RT at about 700 ° C. for about 30 seconds
Repeat N. As a result, the field oxide film 105
Titanium silicide films 111ab and 111bb having a C49 structure are formed on the surface of the N-type source / drain region 109 and the surface of the P-type source / drain region 110 which are self-aligned with the silicon oxide film spacer 108. The thickness of each of the titanium / silicide films 111ab and 111bb is about 30 nm. On the other hand, on the upper surfaces of the gate electrodes 107a and 107b, a titanium silicide film is further grown on the surfaces of the titanium silicide films 111a and 111b, and as a result, C is self-aligned on these upper surfaces.
Titanium silicide film 111aa, 111b having a 49 structure
a will be formed. Titanium silicide film 11
The film thicknesses of 1aa and 111ba are around 60 nm, respectively. These titanium / silicide films 111aa, 111
A titanium nitride film (not shown) having a film thickness of about 25 nm is formed on the surfaces of ab, 111ba, and 111bb, respectively. Further, the surfaces of the field oxide film 105 and the silicon oxide film spacer 108 are mainly covered with the silicon nitride film, and the unreacted titanium film 141b may remain in the portions which are in direct contact with these surfaces. The titanium nitride film and the unreacted titanium film 141b are removed with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide [FIG.
(D)].

In the present embodiment, the surface of the N-type source / drain region 109 and the P-type source / drain region 110.
The thickness of the titanium film 141b covering the surface of the is about 30 nm. Therefore, when the titanium / silicide films 111ab and 111bb having the C49 structure are formed by the silicidation reaction, the vicinity of the interface between the N-type source / drain region 109 and the titanium / silicide film 111ab, the P-type source / drain region 110 and the titanium are formed. The depletion phenomenon near the interface with the silicide film 111bb is suppressed.
On the other hand, in the gate electrodes 107a and 107b, the depletion phenomenon at the time when the titanium / silicide films 111a and 111b are formed on the upper surfaces thereof is suppressed, but the titanium / silicide films 111aa and 111ba are formed on the upper surfaces thereof.
The depletion phenomenon cannot be avoided at the time of the formation of () (this matter will be described later).

Next, RT at 850 ° C. for about 10 seconds
N, the titanium silicide film 111aa, 111
ab, 111ba, and 111bb are titanium silicide films 112aa, 112ab, and 112 having a C54 structure, respectively.
phase transition to ba and 112bb. The thickness of the titanium / silicide films 112aa and 112ba is about 60 nm, and the thickness of the titanium / silicide films 112ab and 112bb is about 30 nm. This completes the formation of the CMOS transistor of the titanium salicide structure according to this embodiment [FIG. 2 (d)].

In this embodiment, the gate electrode 107
titanium silicide film 111 covering the upper surfaces of a and 107b
Since the thicknesses of aa and 111ba are sufficiently thick, the titanium / silicide film 112a is used when the phase transition to the C54 structure occurs.
a and 112ba are formed without aggregation. Further, a titanium silicide film 111ab covering the surfaces of the N-type source / drain region 109 and the P-type source / drain region 110,
Although the film thickness of 111 bb is around 30 nm, the N-type source / drain region 109 and the P-type source / drain region 110 have wide widths, respectively, so that these N-type source / drain regions 109 do not aggregate.
A titanium silicide film 112a is formed on the surfaces of the p-type source / drain regions 109 and the p-type source / drain regions 110.
It becomes possible to form b, 112bb. The depletion of the gate electrodes 107a and 107b at the time when the titanium / silicide films 111aa and 111ba are formed is somewhat relaxed when the phase transition to the C54 structure occurs. This is because the diffusion coefficient of impurities in polycrystalline silicon at a temperature of 850 ° C. is larger than that in single crystal silicon.

Although illustration is omitted, after that, an interlayer insulating film, a contact hole, a metal wiring, etc. are formed to form a semiconductor device including the CMOS transistor.

In the semiconductor device having the titanium-salicide structure formed according to the first embodiment, the titanium-silicide film covering the upper surface of the gate electrode is thick enough to prevent aggregation. . The thickness of the titanium silicide film covering the surface of the source / drain region is such that aggregation does not easily occur at this portion, and is smaller than the thickness of the titanium silicide film covering the upper surface of the gate electrode. -It is thin enough to avoid depletion near the surface of the drain region. Therefore, in the semiconductor device according to the present embodiment, the increase in the sheet resistance of the gate electrode is suppressed, and the reduction in the current driving capability of the MOS transistor can be easily avoided.

In the conventional manufacturing method, the formation of the titanium film is 1
Therefore, the manufacturing margin for the thickness of the titanium film becomes strict (for example, thicker than 30 nm and thinner than 35 nm) when manufacturing a miniaturized semiconductor device having a design rule of about 0.35 μm. Therefore, as miniaturization further progresses, the manufacturing margin becomes more severe. On the other hand, in the first embodiment, the purpose is achieved by forming the titanium film twice, so that there is a sufficient manufacturing margin even for a finer design rule than the 0.35 μm design rule. Can respond.

Referring to FIGS. 3 and 4 which are schematic sectional views of the manufacturing process of the semiconductor device, the second embodiment of the present invention also includes
It is a semiconductor device including a CMOS transistor having a titanium salicide structure according to the 0.35 μm design rule, and is formed as follows.

First, N is formed on the surface of the P-type silicon substrate 201.
The well 202 and the P well 203 are formed. N well 2
The junction depth of 02 and the depth of the P well 203 are both about 1.0 μm. A field oxide film 204 having a film thickness of about 400 nm is formed in the element isolation region on the surface of the P-type silicon substrate 201 by selective oxidation. P well 20
In the element isolation region on the surface of No. 3, the field oxide film 204
Immediately below, a P-type diffusion layer 205 for a channel stopper is formed. A gate oxide film 206 having a film thickness of about 10 nm is formed in the element isolation region on the surface of the P-type silicon substrate 201 by thermal oxidation. A film thickness of 30 is formed on the entire surface by the vapor phase growth method.
A non-doped polycrystalline silicon film 227 of about 0 nm is formed [FIG. 3 (a)]. The film thickness of the polycrystalline silicon film 227 is preferably larger than half the film thickness of the field oxide film 204.

Next, the polycrystalline silicon film 227 is patterned to form a polycrystalline silicon film pattern 227a in the gate electrode formation planned regions on the surfaces of the N well 202 and the P well 203, respectively. The width of the polycrystalline silicon film pattern 227a is about 0.35 μm. A low-concentration N-type diffusion layer 229 is formed on the surface of the P well 203 by, for example, boron ion implantation using a photoresist film (not shown) covering the N well 202 as a mask. further,
A low-concentration P-type diffusion layer 230 is formed on the surface of the N well 202 by, for example, ion implantation of phosphorus using another photoresist film that covers the P well 103 as a mask.

Next, a film thickness of 100 is formed on the entire surface by a vapor phase growth method.
a silicon nitride film (not shown in the figure) of about nm is formed,
This silicon nitride film is etched back to form a silicon nitride film spacer 2 on the side surface of the polycrystalline silicon film pattern 227a.
18 are formed. Difluoro methane (CH ₂ F ₂ ) or fluoro methane (C
RIE using H ₃ F) as an etching gas is preferable. In this RIE, the silicon nitride film is anisotropically etched almost selectively, and it is possible to avoid removal of the gate oxide film 206 and thinning of the field oxide film 204. The space between the silicon nitride film spacer 218 and the field oxide film 204 is about 0.5 μm [FIG.
(B)].

Next, thermal oxidation is performed in a dry oxygen atmosphere at about 900 ° C. to form an N-type diffusion layer 229 self-aligned with the field oxide film 204 and the silicon nitride film spacer 218.
A silicon oxide film 236a is formed on the surface of the P type diffusion layer 230 and the surface of the P type diffusion layer 230, and a silicon oxide film 236b is formed on the upper surface of the polycrystalline silicon film pattern 227a.
The film thickness of the silicon oxide film 236a is about 30 nm [FIG. 3 (c)].

Next, using a photoresist film (not shown) covering the N well 202 as a mask, ion implantation of arsenic of about 3 × 10 ¹⁵ cm ^-2 is performed at about 70 KeV, and after removing this photoresist film. The heat treatment is performed in a nitrogen atmosphere at about 900 ° C. for about 10 minutes. As a result, on the P well 203 side, a high-concentration N type diffusion layer 239 self-aligned with the field oxide film 205 and the silicon nitride film spacer 218 is formed on the surface of the P well 203, and the N type diffusion layer 229 and the N type diffusion layer 229 are formed. Type diffusion layer 239 and N type source
The formation of the drain region 209 is completed. N-type diffusion layer 23
The junction depth of No. 9 is about 0.1 μm. In addition, the polycrystalline silicon film pattern 227a on the surface of the P well 203
Also becomes a high-concentration N-type and consists of this (gate length 0.3
The formation of the gate electrode 207a (about 5 μm) is completed.

Then, using another photoresist film (not shown) covering the P well 203 as a mask, 5 × 10 ¹⁵ cm
Ion implantation of boron difluoride (BF ₂ ) of about ^-2 to 70K
After eV, the photoresist film is removed and then heat treatment is performed at 850 ° C. for about 10 minutes. As a result, on the N well 202 side, the field oxide film 20 is formed.
5 and the silicon nitride film spacer 218 are self-aligned to form a high-concentration P-type diffusion layer 239 on the surface of the N well 202, and a P-type source / drain including a P-type diffusion layer 230 and a P-type diffusion layer 240 is formed. The formation of the region 210 is completed. P
The junction depth of the mold diffusion layer 240 is about 0.15 μm. Further, the polycrystalline silicon film pattern 227a on the surface of the N well 202 also becomes a high-concentration P-type, and the formation of the gate electrode 207b (gate length of about 0.35 μm) is completed [FIG. 3 (d)]. .

Next, a photoresist film (not shown in the drawing) is applied and formed on the entire surface. For example, plasma with oxygen
By etching, the photoresist film is etched back until the upper surface of the silicon oxide film 236b is exposed, and the photoresist film 251 is left. In this embodiment, since the thickness of the polycrystalline silicon film 227 (300 nm) is thicker than 1/2 (200 nm) of the thickness of the field oxide film 204, the upper surface of the silicon oxide film 236b can be exposed by this etch back. it can. Using this photoresist film 251 as a mask, the silicon oxide film 236b is selectively removed by, for example, buffered hydrofluoric acid [FIG.
(E)].

After removing the photoresist film 251, ion implantation of silicon of about 1 × 10 ¹⁵ cm ⁻² is performed.
The gate electrodes 207a and 207 are formed at about 0 KeV.
The polycrystalline silicon near the upper surface of b is made amorphous. After removing the natural oxide film on the upper surfaces of the gate electrodes 207a and 207b, a first titanium film (not shown) having a film thickness of about 30 nm is formed on the entire surface by sputtering. Next, 700
Perform RTN for about 30 seconds at about ℃, gate electrode 2
Titanium silicide films 211a and 211b having a C49 structure are formed on the upper surfaces of 07a and 207b in a self-aligned manner. The thickness of each of the titanium / silicide films 211a and 211a is about 30 nm. The titanium nitride film and the unreacted first titanium oxide film were mixed with a mixed solution of ammonia water and hydrogen peroxide water.
The titanium film is removed [FIG. 4 (a)]. In this embodiment, since the silicon oxide film 207b covering the upper surfaces of the gate electrodes 207a and 207b is selectively removed and then the first titanium film is formed, the gate electrode 20 is formed as described above.
Titanium silicide film 21 only on the upper surface of 7a, 207b
It becomes possible to form 1a and 211a.

Next, for example, by RIE using a mixed gas of CHF ₃ and CO or a mixed gas of C ₄ F ₈ and CO as an etching gas, N-type source / drain regions 209 and P-type source / drain regions are formed. Two
The silicon oxide film 236a on the surface 10 is removed [FIG.
(B)].

Next, the N-type source / drain regions 209,
In order to make the single crystal silicon near the surface of the P-type source / drain region 210 amorphous, the same ion implantation of silicon as described above is performed to remove the natural oxide film on these surfaces. After that, the film thickness is 30n on the entire surface by sputtering.
A second titanium film (not shown) of about m is formed. Next, RTN is performed again at about 700 ° C. for about 30 seconds. As a result, the surface of the N-type source / drain region 209 self-aligned with the field oxide film 205 and the silicon nitride film spacer 218, and the P-type source / drain region 21.
On the surface of 0, titanium-silicide films 211ba and 211bb each having a C49 structure are formed. The thicknesses of the titanium / silicide films 211ab and 211bb are also around 30 nm. On the other hand, the gate electrodes 207a, 20
On the upper surface of 7b, titanium silicide films 211a, 21a
A titanium silicide film is further grown on the surface of 1b, and as a result, titanium silicide films 211aa and 211ba having a C49 structure are formed on these upper surfaces in a self-aligned manner. Titanium silicide film 211aa, 211
The film thickness of ba is also around 60 nm. The titanium nitride film and the unreacted second titanium film are removed by a mixed solution of aqueous ammonia and aqueous hydrogen peroxide [FIG.
(C)].

Next, RT at about 850 ° C. for about 10 seconds
N, and titanium silicide films 211aa and 211aa
ab, 211ba, and 211bb are titanium silicide films 212aa, 212ab, and 212 having a C54 structure, respectively.
phase transition to ba, 212bb. The titanium / silicide films 212aa and 112ba also have a thickness of about 60 nm, and the titanium / silicide films 212ab and 212bb also have a thickness of about 30 nm. This completes the formation of the CMOS transistor of the titanium salicide structure according to this embodiment [FIG. 4 (d)].

Also in this embodiment, the gate electrode 207 is used.
a titanium silicide film 211 covering the upper surfaces of a and 207b
Since the thicknesses of aa and 211ba are sufficiently thick, the titanium / silicide film 212a is used when the phase transition to the C54 structure occurs.
a and 212ba are formed without aggregation. Further, a titanium silicide film 211ab covering the surfaces of the N-type source / drain regions 209 and the P-type source / drain regions 210,
Although the film thickness of 211 bb is around 30 nm, since the widths of the N-type source / drain region 209 and the P-type source / drain region 210 are wide, these N-type source / drain regions 209 do not aggregate.
A titanium silicide film 212a is formed on the surfaces of the p-type source / drain regions 209 and the p-type source / drain regions 210.
It is possible to form b, 212bb. The depletion of the gate electrodes 207a and 207b at the time when the titanium / silicide films 211aa and 211ba are formed is somewhat relaxed when the phase transition to the C54 structure occurs. This is because the diffusion coefficient of impurities in polycrystalline silicon at a temperature of 850 ° C. is larger than that in single crystal silicon.

Although illustration is omitted, after that, an interlayer insulating film, a contact hole, a metal wiring, etc. are formed to form a semiconductor device including the CMOS transistor.

The second embodiment has the effects of the first embodiment. Furthermore, this embodiment is based on the first
This embodiment has the effect that the manufacturing process is somewhat simpler than in the above embodiment.

[0056]

As described above, in the semiconductor device according to the present invention, the thickness of the titanium-silicide film of the C54 structure which covers the upper surface of the gate electrode made of the polycrystalline silicon film in a self-aligned manner is such that the surface of the source / drain region is self-aligned. C5 to cover consistently
4 structure titanium ・ Titanium thicker than silicide film
It has a salicide structure MOS transistor.

The MOS transistor having the above structure according to the method for manufacturing a semiconductor device of the present invention is formed as follows.
First, a titanium silicide film having a C49 structure is selectively formed on the upper surface of the gate electrode by using the first titanium film. Subsequently, a titanium silicide film having a C49 structure is formed by a second titanium film so as to cover the surface of the source / drain region in a self-aligned manner, and at the same time, a film thickness of the titanium silicide film having a C49 structure is selectively formed on the upper surface of the gate electrode. Increase. After that, the titanium silicide film having the C49 structure becomes a titanium silicide film having the C54 structure by the phase transition.

As a result, the MO of titanium salicide structure is obtained.
In the S-transistor, it is easy to suppress an increase in sheet resistance of the gate electrode, and it is also easy to suppress a decrease in current driving capability. Further, it becomes easy to form a titanium salicide structure MOS transistor having such characteristics with a manufacturing margin.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the first embodiment.

FIG. 3 is a schematic sectional view of a manufacturing process according to a second embodiment of the present invention.

FIG. 4 is a schematic sectional view of a manufacturing process of the second embodiment.

FIG. 5 is a schematic cross-sectional view of a manufacturing process of a conventional semiconductor device.

FIG. 6 is a schematic sectional view of a manufacturing process of the conventional semiconductor device.

[Explanation of symbols]

101, 201, 301 P-type silicon substrate 102, 202, 302 N well 103, 203, 303 P well 104, 204, 304 Field oxide film 106, 206, 306 Gate oxide film 107a, 107b, 207a, 207b, 307a,
307b Gate electrodes 108, 308 Silicon oxide film spacers 109, 209, 309 N-type source / drain regions 110, 210, 310 P-type source / drain regions 111a, 111aa, 111ab, 111b, 111
ba, 111bb, 112aa, 112ab, 112b
a, 112bb, 211a, 211aa, 211ab,
211b, 211ba, 211bb, 212aa, 21
2ab, 212ba, 212bb, 311aa, 311
ab, 311ba, 312aa, 312ab, 312b
a Titanium silicide film 136, 236a, 236b Silicon oxide film 141a, 141b, 341 Titanium film 218 Silicon nitride film spacer 251 Photoresist film

Claims (9)

[Claims] 1. A silicon substrate having one conductivity type region provided on at least a part of its surface, and polycrystalline silicon having a desired film thickness provided on the surface of said one conductivity type region via a gate oxide film. A gate electrode formed of a film, an insulating film spacer covering a side surface of the gate electrode, a first titanium silicide film having a first required thickness and having a C54 structure and covering the upper surface of the gate electrode in a self-aligned manner. And a reverse conductivity type source provided on the surface of the one conductivity type region.
A second C54 structure having a second required thickness smaller than the first required thickness and covering the surface of the opposite conductivity type source / drain region in a self-aligned manner with the drain region and the insulating film spacer. And a titanium silicide film of 1. 2. The semiconductor device according to claim 1, wherein the insulating film forming the insulating film spacer is a silicon oxide film or a silicon nitride film. 3. A field insulating film is formed in an element isolation region on a surface of a silicon substrate having one conductivity type region provided on at least a part of the surface, and a gate oxide film is formed in an element forming region on the approximate surface. A step of forming at least a polycrystalline silicon film having a desired thickness directly covering the surface of the gate oxide film on the entire surface, and patterning at least the polycrystalline silicon film,
A step of leaving at least the polycrystalline silicon film pattern in the region where the gate electrode is to be formed, an insulating film having a predetermined thickness is formed on the entire surface, the insulating film is etched back, and the insulating film is formed on at least the side surface of the polycrystalline silicon film pattern. Forming a spacer, forming a silicon oxide film on at least the surface of the one conductivity type region self-aligned with the field insulating film and the insulating film spacer by thermal oxidation, and ion of an impurity of opposite conductivity type A step of converting the polycrystalline silicon film pattern into a gate electrode by implantation and forming a source / drain region of opposite conductivity type on the surface of the one conductivity type region; a step of exposing the upper surface of the gate electrode; A step of forming a first titanium film and a first heat treatment in a nitrogen atmosphere to cover the upper surface of the gate electrode in a self-aligned manner C49. The first of titanium elephant -
Forming a silicide film and selectively removing the first titanium nitride film and the unreacted first titanium film; and removing at least the silicon oxide film by anisotropic etching of the silicon oxide film, Exposing the surface of the reverse conductivity type source / drain region self-aligned with the field insulating film and the insulating film spacer; forming a second titanium film on the entire surface; and performing a second heat treatment in a nitrogen atmosphere. To increase the thickness of the first titanium / silicide film having a C49 structure, and to form a C49 structure on the surface of the reverse conductivity type source / drain region self-aligned with the field insulating film and the insulating film spacer. Forming a titanium silicide film of No. 2 and selectively removing the second titanium nitride film and the unreacted second titanium film; and Performing a third heat treatment to cause the first and second titanium-silicide films having a C49 structure to undergo a phase transition to first and second titanium-silicide films having a C54 structure. Manufacturing method. 4. A field insulating film is formed in an element isolation region of a surface of a silicon substrate having a surface of at least one conductivity type region, and a gate oxide film is formed in an element formation region of the surface. A step, a step of sequentially forming a non-doped polycrystalline silicon film having a desired film thickness and a silicon nitride film on the entire surface, and sequentially patterning the silicon nitride film and the polycrystalline silicon film to form a gate electrode formation planned region. A step of leaving the silicon nitride film pattern and the polycrystalline silicon film pattern, and forming a first silicon oxide film of a predetermined thickness on the entire surface, etching back the first silicon oxide film, and then the silicon nitride film pattern And a silicon oxide film spacer is formed on the side surface of the polycrystalline silicon film pattern and self-aligned with the field insulating film and the silicon oxide film spacer. A step of forming an exposed surface of the one conductivity type region, a step of forming a second silicon oxide film on the exposed surface by thermal oxidation, and an ion implantation of an impurity of opposite conductivity type to form the polycrystalline silicon film pattern. To a reverse conductivity type polycrystalline silicon film pattern to form a gate electrode, and to form a reverse conductivity type source / drain region on the surface of the one conductivity type region, and the silicon nitride film pattern is selectively formed. A step of removing, a step of forming a first titanium film on the entire surface, and a step of performing a first heat treatment in a nitrogen atmosphere to cover the upper surface of the gate electrode in a self-aligned manner with the first titanium film having a C49 structure.
A step of forming a silicide film and selectively removing the first titanium nitride film and the unreacted first titanium film; and a step of removing the second silicon oxide film by anisotropic etching, A step of forming a second titanium film on the entire surface and a second heat treatment in a nitrogen atmosphere are performed to increase the film thickness of the first titanium / silicide film having a C49 structure, and the field insulating film and the silicon oxide film. A second titanium-silicide film having a C49 structure is formed on the surface of the opposite conductivity type source / drain region self-aligned with the film spacer, and the second titanium nitride film and the unreacted second titanium film are selected. And a third heat treatment in a nitrogen atmosphere are performed to phase-transform the first and second titanium / silicide films having a C49 structure into first and second titanium / silicide films having a C54 structure. A method of manufacturing a semiconductor device, comprising: 5. The mixed gas of trifluoromethane (CHF ₃ ) and carbon monoxide (CO) is used for etching back the first silicon oxide film to form the silicon oxide film spacer. Or octa
5. The method for manufacturing a semiconductor device according to claim 4, wherein the anisotropic etching is performed using a mixed gas of fluorobutane (C ₄ F ₈ ) and carbon monoxide as an etching gas. 6. The anisotropic etching for removing the second silicon oxide film is performed by using a mixed gas containing trifluoromethane and carbon monoxide or a mixed gas containing octafluorobutane and carbon monoxide. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the etching is anisotropic etching using a gas as an etching gas. 7. A step of forming a field insulating film in an element isolation region on a surface of a silicon substrate having a surface of one conductivity type region, and forming a gate oxide film in the element formation region, and a desired film over the entire surface. A step of forming a thick non-doped polycrystalline silicon film, a step of patterning the polycrystalline silicon film and leaving a polycrystalline silicon film pattern in the region where the gate electrode is to be formed, and a silicon nitride film of a predetermined thickness on the entire surface. Forming and etching back the silicon nitride film to form a silicon nitride film spacer on the side surface of the polycrystalline silicon film pattern; and by thermal oxidation, the upper surface of the polycrystalline silicon film pattern and the field insulating film, Forming a first silicon oxide film and a second silicon oxide film on the surface of the one conductivity type region that is self-aligned with the silicon nitride film spacer; The gate electrode is formed by converting the polycrystalline silicon film pattern into a reverse conductive type polycrystalline silicon film pattern by ion implantation of a reverse conductive type impurity, and the reverse conductive type source / drain regions are formed on the surface of the one conductive type region. And a step of coating and forming a photoresist film on the entire surface, etching back the photoresist film until the upper surface of the first silicon oxide film is exposed, and removing the first silicon oxide film And a step of forming a first titanium film on the entire surface, and a first titanium film having a C49 structure that covers the upper surface of the gate electrode in a self-aligned manner by performing a first heat treatment in a nitrogen atmosphere.
Forming a silicide film and selectively removing the first titanium nitride film and the unreacted first titanium film; and removing at least the second silicon oxide film by anisotropic etching. Exposing the surface of the opposite conductivity type source / drain region self-aligned with the field insulating film and the silicon nitride film spacer; forming a second titanium film over the entire surface; Heat treatment is performed to increase the thickness of the first titanium / silicide film having a C49 structure, and the C49 structure is formed on the surface of the reverse conductivity type source / drain region self-aligned with the field insulating film and the silicon nitride film spacer. Forming a second titanium-silicide film, and selectively removing the second titanium nitride film and the unreacted second titanium film; and Third heat treatment is performed to cause the first and second titanium / silicide films having the C49 structure to undergo phase transition to the first and second titanium / silicide films having the C54 structure. Device manufacturing method. 8. The etching back of the silicon nitride film performed to form the silicon nitride film spacer is performed by using difluoro methane (CH ₂ F ₂ ) or fluoro methane (CH ₃ F) as an etching gas. The method of manufacturing a semiconductor device according to claim 7, wherein the anisotropic etching is used. 9. Anisotropic etching for removing the silicon oxide film covering the surface of the opposite conductivity type source / drain regions is performed by a mixed gas of trifluoromethane and carbon monoxide, or octafluoromethane. 8. The method of manufacturing a semiconductor device according to claim 7, wherein anisotropic etching is performed using a mixed gas of butane and carbon monoxide as an etching gas.