JPH098146A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device which prevents a threshold voltage from becoming not matched by a method wherein gate electrodes of a pair of differential transistors are connected electrically by a conductor for charging-up prevention up to the halfway part of their manufacture. CONSTITUTION: The gate of a first transistor M1 and the gate of a second transistor M2 are connected electrically to each other by polysilicon 12 as an interconnection for charging-up prevention up to the stage of a prescribed production process. Then, by using the polysilicon 12 as the interconnection for charging-up prevention, a passivation film 14 is etched selectively, and the interconnection 12 for charging-up prevention is etched selectively. As a result, when the gates of the first and second transistors M1, M2 are formed, it is possible to restrain the deviation of the threshold voltage of the transistors as a pair from being generated by the influence of a charging-up operation which is subjected in a manufacturing process in which the passivation film 14 is etched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a differential input pair transistor having a MOS structure.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional differential pair transistor is composed of a first transistor M1 and a second transistor M2. The gate may be connected to the first high-polysilicon resistor R1, and the gate of the second transistor M2 may be connected to the drain of the sixth transistor M6, that is, the diffusion layer. Note that the sources of the first transistor M1 and the second transistor M2 are commonly connected to a fifth transistor M5 that constitutes a constant current source, and the drain of the first transistor M1 has a third and a fourth transistor M5. Transistors M3, M
4 is connected to the input end of the current mirror circuit composed of 4 and the output is taken out from the connection point between the second transistor M2 and the output end of the current mirror circuit.

[0003]

In this conventional differential input pair transistor, the gate of the first transistor M1 is connected to the first high polysilicon resistor R1 and is not connected to the diffusion layer. Since the gate of the transistor M2 is connected to the diffusion layer, due to the influence of charge-up in the manufacturing process, for example, etching of aluminum, as shown in FIG.
A difference in threshold voltage (threshold voltage) ΔV _T = about 20 mV occurs in the G characteristic (drain current-gate voltage characteristic).

This is because the charge (charge) accumulated at the interface between the gate oxide film and the gate polysilicon due to charge-up easily escapes in the second transistor M2 whose gate is connected to the diffusion layer, and the high polysilicon resistance R1. Is connected to the gate (not connected to the diffusion layer)
This occurs because it is difficult for the first transistor M1 to come off.

As described above, in the conventional differential input pair transistor, the most important threshold voltage V _T cannot be matched, and when used as an input stage of an operational amplifier, an offset (input offset voltage) is large. There was a problem that

Therefore, the present invention solves the above-mentioned problems, and
It is an object of the present invention to provide a semiconductor device and its manufacturing method in which the threshold voltage V _T is prevented from becoming unmatched due to the effect of charge-up in a differential input pair transistor having an OS structure.

[0007]

In order to achieve the above-mentioned object, the present invention electrically connects the gate electrodes of the differential pair transistors of the input portion of the MOS structure for differential operation to each other until a predetermined manufacturing process. There is provided a semiconductor device including a charge-up preventing wiring for connecting to the semiconductor device.

Further, the present invention provides a semiconductor device comprising first and second MOS transistors, each of which includes a differential pair transistor whose gate connection destination is different from each other such as a diffusion layer and polysilicon. A charge-up preventing wiring for electrically connecting the gate electrodes of the second MOS transistor to each other is provided, and the charge-up preventing wiring is accumulated in the gate region of the MOS transistor by charge-up generated in a later manufacturing process. There is provided a semiconductor device characterized in that the generated charge functions to escape to the diffusion layer side through the charge-up prevention wiring and then the charge-up prevention wiring is cut.

The present invention also provides an MO for performing a differential operation.
A semiconductor device characterized in that the gate electrodes of the differential pair transistor of the input section of the S structure are electrically connected to each other by a charge-up prevention wiring, and the charge-up prevention wiring is cut after a predetermined manufacturing process is completed. A method for manufacturing the same is provided.

The semiconductor device manufacturing method of the present invention is preferably characterized in that the charge-up preventing wiring is made of a polysilicon wiring and is cut by selective etching after the passivation film is formed.

Further, a method of manufacturing a semiconductor device according to the present invention
Preferably, the charge-up preventing wiring is made of a polysilicon wiring, and two electrode pads are connected to the polysilicon wiring via a contact, and a predetermined distance is provided between the two electrode pads during a wafer test after manufacturing a semiconductor device. Is applied to disconnect the charge-up preventing wiring.

[0012]

According to the present invention, even if the connection destination of the gate of the differential pair transistor is different from that of the diffusion layer and the high polysilicon resistance, by electrically connecting the gate electrodes to each other during the manufacturing process, the aluminum Since the influence of charge-up that occurs during etching or growth of the passivation film is made equal in the direction of facilitating the escape of charge to the diffusion layer, the shift in the threshold voltage V _T of the pair transistor can be reduced from about 20 mV to several mV. .

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

[0014]

Embodiment 1 FIGS. 1 to 4 are views for explaining one embodiment of the present invention. 1 and 4, elements having the same functions as those in FIG. 6 are designated by the same reference numerals.

Referring to FIG. 1, the first transistor M1
Gate and the gate of the second transistor M2 are electrically connected to each other by polysilicon 6 which is a charge-up preventing wiring. Note that FIG. 1 shows an equivalent circuit before the polysilicon 6 which is the charge-up preventing wiring is cut.

FIG. 2 is a view showing a cross section taken along the line AA 'in FIG. 1, showing an embodiment of the present invention in the order of manufacturing steps. That is, FIG. 2A shows the gate polysilicon 12
2 (b) is a state after the wiring pattern is formed by selectively etching the layer, and FIG. 2 (b) is a state after the gate polysilicon 12 and the interlayer film 13 between the wirings of the first layer are selectively etched. FIG. 3C is a sectional view showing a state after the passivation film 14 is selectively etched. 2D is a sectional view showing a state after the gate polysilicon 12 is selectively etched and removed (cut). And FIG. 3 is a plan view in each state of FIG. 2 (a) -FIG. 2 (c). Further, FIG. 4 is a diagram showing a circuit configuration after the gate polysilicon 12 is selectively etched (corresponding to the step of FIG. 2D).

First, the first and second transistors M1 and M
The two gates are connected by the gate polysilicon 12 using the photolithography technique (see FIG. 2A).

Thereafter, an interlayer film 13, aluminum (not shown) for forming a wiring layer (first wiring layer), and a passivation film 14 are formed on the connected gate polysilicon 12, but at least the one shown in FIG. The line AA ′ is selectively etched by using the photolithography technique (see FIGS. 2B and 2C). That is, FIG.
Referring to FIG. 3B, the interlayer film on the line AA ′ in FIG.
13 is selectively etched, and similarly with reference to FIG. 2C, the passivation film 14 is selectively etched to expose the surface of the gate polysilicon 12 in advance. Note that, referring to FIG. 3, the gate 4 of the first transistor M1 and the gate 5 of the second transistor M2 are made of polysilicon (gate polysilicon), and on the interlayer film 13 via the gate polysilicon-aluminum contact 7. Electrically connected to aluminum wiring, high polysilicon resistance R1 and transistor M6
Respectively connected to the drain electrodes of.

Finally, the gate polysilicon 12 is selectively etched by plasma etching (see FIG. 2D).

At the time of this etching, since the aluminum of the electrode pad such as a bonding pad (not shown) is not etched, the photolithography technique may not be used. That is, in the present embodiment, no new photolithography process is required for cutting the charge-up preventing wiring. It is assumed that electrode pads such as bonding pads are formed in the manufacturing process stage of FIG. 2C (aluminum surface is exposed).

In this embodiment, the gate polysilicon 12 is used as the charge-up preventing wiring, and the charge-up preventing wiring (gate polysilicon) is selectively etched after the passivation film 14 is selectively etched.

Therefore, the first and second transistors M
The deviation of the threshold voltage V _T of the paired transistors of the first and second transistors M1 and M2, which is caused by the influence of charge-up during the manufacturing process during the etching of the passivation film 14 when the gates of 1 and M2 are formed, is suppressed. be able to.

[0023]

Second Embodiment A second embodiment of the present invention will be described. FIG. 5 is a plan view before the charge-up preventing wiring 6 is cut in the second embodiment of the present invention.

Referring to FIG. 5, the gates of the first and second MOS transistors M1 and M2 are connected to each other by a charge-up preventing wiring 6 made of polysilicon, and the charge-up preventing wiring 6 is a gate poly-silicon aluminum. It is electrically connected to the first and second charge-up preventing wiring cutting pads 8 and 9 via the contact 7.

In this embodiment, the charge-up prevention wiring 6 is used for cutting the first charge-up prevention wiring 8 and the second charge-up prevention wiring during the wafer electrical test (during the wafer test). A predetermined voltage is applied between the pad 9 and the pad 9 from a probe needle of a wafer prober (not shown) to cut the wafer. Thus, in this embodiment,
Since the charge-up preventing wiring 6 is cut at the time of the wafer test after the semiconductor wafer is manufactured, the number of manufacturing steps for the semiconductor wafer situation is not increased.
The same effect as the first embodiment can be obtained.

In the above-mentioned embodiment, even if the gates of the differential input pair transistors are connected at different destinations such as the diffusion layer and the high polysilicon resistance, the gate electrodes are electrically connected to each other until the middle of the manufacturing process. The effect of charge-up that occurs during the etching and growth of the passivation film is made equal in the direction of facilitating the escape of the charge to the diffusion layer.
Number mV _T deviation a (= [Delta] V _T) of about 20mV of the prior art
Therefore, the input offset voltage of the operational amplifier can be significantly reduced.

Although the present invention has been described with reference to the above embodiments, it is needless to say that the present invention is not limited to the above embodiments and includes various embodiments according to the principle of the present invention.

[0028]

As described above, according to the present invention, even when the connection destinations of the gates of the differential input pair transistor are different from each other such as the diffusion layer and the high polysilicon resistance, the gate electrodes are electrically connected to each other until the manufacturing process. The connection makes the effects of charge-up that occur during etching of aluminum or growth of the passivation film equal in the direction of facilitating the escape of charges to the diffusion layer. Therefore, the deviation ΔV _T of the threshold voltage V _T of the pair transistor is several mV. It can be reduced to the extent. Further, according to the present invention, since the charge-up preventing wiring is cut at the time of the wafer test after the wafer is manufactured, the above effect can be obtained without increasing the wafer manufacturing process.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention (a diagram showing an equivalent circuit before disconnection of a charge-up prevention wiring).

FIG. 2 is a diagram showing an embodiment of the present invention in the order of manufacturing steps, and is a diagram showing a cross section taken along line AA ′ in FIG. 1.

FIG. 3 is a plan view of an embodiment of the present invention (a diagram showing an equivalent circuit before disconnection of charge-up preventing wiring).

FIG. 4 is a diagram showing a circuit configuration of an embodiment of the present invention (a diagram showing an equivalent circuit after cutting off charge-up prevention wiring).

FIG. 5 is a plan view for explaining the second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a conventional example.

FIG. 7 is a diagram showing ID-VG characteristics of a conventional example.

[Explanation of symbols]

 M1 1st transistor M2 2nd transistor M3 3rd transistor M4 4th transistor M5 5th transistor M6 6th transistor R1 1st high polysilicon resistance VDD power supply 1 Drain of 1st transistor M1 2 M1 Source of (M2) 3 M2 drain 4 M1 gate 5 M2 gate 6 Charge-up prevention wiring 7 Gate poly-aluminum contact 8 First charge-up prevention wiring cutting pad 9 Second charge-up prevention wiring Pad 11 Field oxide film 12 Gate polysilicon 13 Interlayer film 14 Passivation film

Claims (5)

[Claims] 1. A charge-up prevention wiring for electrically connecting gate electrodes of a differential pair transistor of an input portion of a MOS structure for performing a differential operation to each other until a predetermined manufacturing process. A semiconductor device characterized by: 2. A semiconductor device comprising first and second MOS transistors, each including a differential pair transistor whose gate connection destination is different from each other such as a diffusion layer and polysilicon, wherein the first and second MOS transistors are provided. A charge-up preventing wiring for electrically connecting the gate electrodes of the transistors to each other is provided, and the charge-up preventing wiring prevents the charge accumulated in the gate region of the MOS transistor from being charged up in a later manufacturing process. A semiconductor device, which functions so as to escape to the diffusion layer side through the charge-up prevention wiring, and thereafter cuts the charge-up prevention wiring. 3. A charge-up preventing wiring after electrically connecting the gate electrodes of a differential pair transistor of an input section of a MOS structure for performing a differential operation with a charge-up preventing wiring, after a predetermined manufacturing process is completed. A method of manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, wherein the charge-up preventing wiring is made of a polysilicon wiring and is cut by selective etching after forming a passivation film. 5. The charge-up preventing wiring is composed of a polysilicon wiring, and two electrode pads are connected to the polysilicon wiring via a contact, and between the two electrode pads during a wafer test after manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a predetermined voltage is applied to the wiring, and the charge-up preventing wiring is cut.