JP3017049B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS-structured differential input pair transistor.

[0002]

2. Description of the Related Art As shown in FIG. 6, a conventional differential pair transistor includes a first transistor M1 and a second transistor M2. In some cases, the gate is connected to the first high polysilicon resistance R1, and the gate of the second transistor M2 is connected to the drain of the sixth transistor M6, that is, the diffusion layer. Note that the sources of the first transistor M1 and the second transistor M2 are connected in common and connected to a fifth transistor M5 forming a constant current source, and the drain of the first transistor M1 is connected to the third and fourth transistors. Transistors M3, M
4 is connected to the input terminal of the current mirror circuit composed of the first and second transistors M4, and the output is taken out from the connection point between the second transistor M2 and the output terminal of the current mirror circuit.

[0003]

In this conventional differential input pair transistor, the gate of the first transistor M1 is connected to the first high polysilicon resistance R1, not to the diffusion layer, and to the second transistor M1. Since the gate of the transistor M2 is connected to the diffusion layer, as shown in FIG. 7, the ID-V of the differential pair transistors M1 and M2 is affected by the influence of charge-up in the manufacturing process, for example, etching of aluminum.
A difference ΔV _T = approximately 20 mV in the threshold voltage (threshold voltage) occurs in the G characteristic (drain current-gate voltage characteristic).

[0004] This is because the charge (charge) accumulated at the interface between the gate oxide film and the gate polysilicon due to charge-up easily escapes in the second transistor M2 whose gate is connected to the diffusion layer, and the high polysilicon resistance R1 Connected to the gate (not connected to the diffusion layer)
This occurs because the first transistor M1 is hard to come off.

[0005] Thus, in the conventional differential input pair transistors, the most important match threshold voltage V _T (matching) is Torezu large offset (input offset voltage) in the case of using as an input stage of an operational amplifier There was a problem of becoming.

Accordingly, the present invention solves the above-mentioned problems, and
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same in which the threshold voltage _VT is prevented from being unmatched due to the influence of charge-up in a differential input pair transistor having an OS structure.

[0007]

In order to achieve the above object, the present invention provides a differential pair comprising first and second MOS transistors, each of which has a gate connection destination different from each other such as a diffusion layer and polysilicon. In a semiconductor device including a transistor, a charge-up preventing wiring for electrically connecting gate electrodes of the first and second MOS transistors is provided, wherein the charge-up preventing wiring comprises:
It functions to release charges accumulated in the gate region of the MOS transistor due to charge-up occurring in a later manufacturing process to the diffusion layer side through the charge-up prevention wiring, and thereafter cuts the charge-up prevention wiring. A semiconductor device is provided.

The present invention also relates to a method of manufacturing a semiconductor device comprising first and second MOS transistors, each of which includes a differential pair transistor such as a diffusion layer and polysilicon, the connection destinations of gates of which are different from each other. The gate electrodes of the first and second MOS transistors are electrically connected to each other by a charge-up prevention wiring, and the charge-up prevention wiring is connected to the gate region of the MOS transistor by charge-up occurring in a predetermined manufacturing process. A method for manufacturing a semiconductor device, wherein the function is to release accumulated charges to the diffusion layer side through the charge-up prevention wiring, and the charge-up prevention wiring is cut off after a predetermined manufacturing process is completed. I do.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the charge-up preventing wiring is made of a polysilicon wiring, and is cut by selective etching after forming a passivation film.

Further, the method of manufacturing a semiconductor device according to the present invention comprises:
Preferably, the charge-up preventing wiring is made of a polysilicon wiring, two electrode pads are connected to the polysilicon wiring via contacts, and a predetermined distance is provided between the two electrode pads during a wafer test after manufacturing the semiconductor device. And disconnecting the charge-up preventing wiring.

[0011]

[0012]

According to the present invention, even when the connection destination of the gate of the differential pair transistor is different from that of the diffusion layer and the high polysilicon resistance, the gate electrodes are electrically connected to each other until the middle of the manufacturing, thereby making the aluminum. the effect of charge-up which occurs during the etching and passivation film growth, due to the comparable direction easily removed charge to the diffusion layer, it is possible to reduce the deviation of the threshold voltage V _T of the transistor pair from about 20mV to several mV .

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

[0014]

Embodiment 1 FIGS. 1 to 4 are diagrams for explaining an embodiment of the present invention. 1 and 4, the elements having the same functions as those in FIG. 6 are denoted by the same reference numerals.

Referring to FIG. 1, first transistor M1
And the gate of the second transistor M2 are electrically connected to each other by a polysilicon 6 serving as a charge-up prevention wiring. FIG. 1 shows an equivalent circuit before cutting the polysilicon 6 serving as a charge-up preventing wiring.

FIG. 2 is a view showing a cross section taken along the line AA 'of FIG. 1, and is a view showing one embodiment of the present invention in the order of manufacturing steps. That is, FIG. 2A shows the gate polysilicon 12.
2B is a state after selectively etching to form a wiring pattern, FIG. 2B is a state after selectively etching the interlayer film 13 between the gate polysilicon 12 and the first wiring, and FIG. 3C is a sectional view showing a state after the passivation film 14 is selectively etched. FIG. 2D is a sectional view showing a state after the gate polysilicon 12 is selectively etched and removed (cut). FIG. 3 is a plan view in each state of FIGS. 2 (a) to 2 (c). FIG. 4 is a diagram showing a circuit configuration after the selective etching of the gate polysilicon 12 (corresponding to the step of FIG. 2D).

First, first and second transistors M1, M
The two gates are connected by a gate polysilicon 12 using a photolithography technique (see FIG. 2A).

Thereafter, an interlayer film 13, aluminum (not shown) for forming a wiring layer (first wiring layer), and a passivation film 14 are formed on the connected gate polysilicon 12, at least as shown in FIG. The etching is selectively performed on the line AA 'by using the photolithography technique (see FIGS. 2B and 2C). That is, FIG.
Referring to FIG. 3B, an interlayer film is taken along line AA 'in FIG.
13 is selectively etched, and similarly, referring to FIG. 2C, the passivation film 14 is selectively etched to expose the surface of the gate polysilicon 12. Referring to FIG. 3, gate 4 of first transistor M1 and gate 5 of second transistor M2 are made of polysilicon (gate polysilicon), and are formed on interlayer film 13 via gate polysilicon-aluminum contact 7. It is electrically connected to the aluminum wiring, and has a high polysilicon resistance R1 and a transistor M6.
, Respectively.

Finally, the gate polysilicon 12 is selectively etched by plasma etching (see FIG. 2D).

In this etching, the aluminum of the electrode pad such as a bonding pad (not shown) is not etched, so that the photolithography technique may not be used. That is, in this embodiment, a new photolithography step is not required for cutting off the charge-up prevention wiring. It is assumed that an electrode pad such as a bonding pad is formed in the manufacturing process step of FIG. 2C (the aluminum surface is exposed).

In this embodiment, the gate polysilicon 12 is used as the charge-up preventing wiring, and the charge-up preventing wiring (gate polysilicon) is selectively etched after the passivation film 14 is selectively etched.

For this reason, the first and second transistors M
1, when the gate formation of M2 caused by the influence of charge-up received by the manufacturing process during etching of the passivation film 14, suppress the deviation of the first, threshold voltage V _T of the pair transistors of the second transistor M1, M2 be able to.

[0023]

[Embodiment 2] A second embodiment of the present invention will be described. FIG. 5 is a plan view of the second embodiment of the present invention before the charge-up preventing wiring 6 is cut.

Referring to FIG. 5, the gates of the first and second MOS transistors M1 and M2 are connected by a charge-up preventing wire 6 made of polysilicon, and the charge-up preventing wire 6 is formed of a gate polysilicon aluminum. It is electrically connected to first and second charge-up prevention wiring cutting pads 8 and 9 via a contact 7.

In this embodiment, the first charge-up prevention wiring disconnection pad 8 and the second charge-up prevention wiring disconnection wiring 8 are cut during the electrical test (wafer test) of the wafer. For example, a predetermined voltage is applied between the pad 9 and a probe needle of a wafer prober (not shown) to cut the pad. Thus, in this embodiment,
Since the charge-up preventing wiring 6 is configured to be cut at the time of a wafer test after manufacturing a semiconductor wafer, the number of manufacturing steps in the semiconductor wafer situation is increased without increasing
The same effects as in the first embodiment can be obtained.

In the above embodiment, even when the connection destination of the gate of the differential input pair transistor is different, such as a diffusion layer and a high polysilicon resistance, the gate electrodes are electrically connected to each other until the middle of the manufacturing process. The effect of charge-up that occurs during the etching and growth of the passivation film is equalized in the direction that facilitates the release of charge (charge) to the diffusion layer.
The deviation of _T (= ΔV _T ) is reduced from about 20 mV of the conventional example to several mV.
, And the input offset voltage of the operational amplifier can be particularly reduced.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment, but includes various embodiments according to the principle of the present invention.

[0028]

As described above, according to the present invention, even when the connection destination of the gates of the differential input pair transistors is different from each other, such as the diffusion layer and the high polysilicon resistance, the gate electrodes are electrically connected to each other until the manufacturing is completed. By connecting, the effect of charge-up occurring during etching of aluminum or growth of the passivation film is made equal in a direction that makes it easy for the charge to escape to the diffusion layer, so that the deviation ΔV _T of the threshold voltage V _T of the pair transistor is reduced by several mV. To a degree. Further, according to the present invention, the configuration is such that the charge-up prevention wiring is cut off at the time of a wafer test after the manufacture of the wafer, so that the above effects can be obtained without increasing the number of wafer manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention (a diagram showing an equivalent circuit before disconnection of a charge-up preventing wiring).

FIG. 2 is a view showing an embodiment of the present invention in the order of manufacturing steps, and is a view showing a cross section taken along line AA ′ of FIG. 1;

FIG. 3 is a plan view of one embodiment of the present invention (a diagram showing an equivalent circuit before charge-up prevention wiring is cut).

FIG. 4 is a diagram showing a circuit configuration of one embodiment of the present invention (a diagram showing an equivalent circuit after a charge-up prevention wiring is cut).

FIG. 5 is a plan view for explaining a second embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a conventional example.

FIG. 7 is a diagram showing ID-VG characteristics of a conventional example.

[Explanation of symbols]

 M1 first transistor M2 second transistor M3 third transistor M4 fourth transistor M5 fifth transistor M6 sixth transistor R1 first high polysilicon resistance VDD power supply 1 drain of first transistor M1 2 M1 (M2) source 3 M2 drain 4 M1 gate 5 M2 gate 6 Charge-up prevention wiring 7 Gate polysilicon-aluminum contact 8 First charge-up prevention wiring disconnection pad 9 Second charge-up prevention wiring disconnection Pad 11 Field oxide film 12 Gate polysilicon 13 Interlayer film 14 Passivation film

Claims (4)

(57) [Claims] 1. A semiconductor device comprising first and second MOS transistors, each of which includes a differential pair transistor having a gate connection destination different from each other such as a diffusion layer and polysilicon, wherein the first and second MOS transistors are provided. A charge-up prevention line for electrically connecting the gate electrodes of the transistors; and the charge-up prevention line stores charge accumulated in the gate region of the MOS transistor due to charge-up occurring in a later manufacturing process. Function to escape to the diffusion layer side through the charge-up prevention wiring,
Thereafter, the charge-up prevention wiring is cut off. 2. A method of manufacturing a semiconductor device comprising first and second MOS transistors, each having a gate connected to a differential pair transistor such as a diffusion layer and polysilicon, which are different from each other. The gate electrodes of the two MOS transistors are electrically connected to each other by a charge-up prevention wiring, and the charge-up prevention wiring is a charge stored in a gate region of the MOS transistor due to charge-up occurring in a predetermined manufacturing process. A semiconductor device, which functions to escape to the diffusion layer side through the charge-up prevention wiring, and cuts the charge-up prevention wiring after a predetermined manufacturing process is completed. 3. The method of manufacturing a semiconductor device according to claim 2, wherein said charge-up prevention wiring is made of polysilicon wiring, and is cut by selective etching after forming a passivation film. 4. The semiconductor device according to claim 1, wherein the charge-up preventing wiring comprises a polysilicon wiring, and two electrode pads are connected to the polysilicon wiring via a contact. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a predetermined voltage is applied to the semiconductor device to cut the charge-up prevention wiring.