JPH098128A - Soi substrate and its manufacturing method - Google Patents
Soi substrate and its manufacturing methodInfo
- Publication number
- JPH098128A JPH098128A JP15046495A JP15046495A JPH098128A JP H098128 A JPH098128 A JP H098128A JP 15046495 A JP15046495 A JP 15046495A JP 15046495 A JP15046495 A JP 15046495A JP H098128 A JPH098128 A JP H098128A
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- JP
- Japan
- Prior art keywords
- single crystal
- insulating film
- silicon substrate
- crystal silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＳＯＩ基板およびその
製造方法に関し、特にパワー素子と超薄膜ＳＯＩ素子を
含む制御回路素子を１チップに集積したパワーＩＣに有
効なＳＯＩ基板およびその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI substrate and a method for manufacturing the same, and more particularly to an SOI substrate effective for a power IC in which control circuit elements including a power element and an ultrathin film SOI element are integrated in one chip and a method for manufacturing the same. It is a thing.
【０００２】[0002]
【従来の技術】シリコン基板の表面から裏面に電流経路
を有する高耐圧のパワー素子と、低耐圧の素子で構成さ
れる制御回路とを１チップに集積する場合、パワー素子
形成領域から絶縁分離されたＳＯＩ層に制御回路を形成
することができるようにしたＳＯＩ基板が用いられる。
この種ＳＯＩ基板については、特開平４−２９３５３号
公報、ＩＳＰＳＤ’９２会報（Ｐｒｏｃｅｅｄｉｎｇｓ
ｏｆ １９９２ ＩＳＰＳＤ）にて公知となってい
る。2. Description of the Related Art When a high breakdown voltage power element having a current path from the front surface to the back surface of a silicon substrate and a control circuit composed of a low breakdown voltage element are integrated on one chip, they are isolated from the power element formation region. An SOI substrate is used in which a control circuit can be formed on the SOI layer.
Regarding this type of SOI substrate, Japanese Patent Laid-Open No. 4-29353 and ISPSD'92 bulletin (Proceedings)
of 1992 ISPSD).
【０００３】図５は特開平４- ２９３５３号公報にて開
示された、縦型のパワー素子と制御回路を集積すること
を目的としたＳＯＩ基板の製造方法（以下、第１の従来
例という）を示す工程順断面図である。FIG. 5 shows a method of manufacturing an SOI substrate for the purpose of integrating a vertical power device and a control circuit disclosed in Japanese Patent Laid-Open No. 4-29353 (hereinafter referred to as a first conventional example). FIG.
【０００４】まず、図５（ａ）に示すように、第１のシ
リコン基板（Ｎ- 型）１の主面上にフォトリソグラフィ
法によりパターニングを行い、フォトレジストをマスク
にイオンエッチ法等により浅い段差２を形成する。次
に、図５（ｂ）に示すように熱酸化等でＳｉＯ2の絶縁
膜を形成した後、凸になった絶縁膜を研磨あるいはエッ
チングにより除去し、第１のシリコン基板（Ｎ- 型）１
の露出表面と形成された埋込絶縁膜３の表面とが同一平
面となるようにする。次に、図５（ｃ）に示すように埋
込絶縁膜３の形成された第１のシリコン基板（Ｎ- 型）
１の一主面と第２のシリコン基板（Ｎ+ 型）４の一主面
とを貼り合わせ、熱処理を行い、強固に接合された一枚
の複合基板を得る。次に、図５（ｄ）に示すように第１
のシリコン基板（Ｎ- 型）１を研削・研磨して所望の厚
さにするとともにその表面を平坦化し、ＳＯＩ層９を形
成する。次に、図５（ｅ）に示すように、その平坦化面
に絶縁膜を形成後フォトリソグラフィ法によりパターニ
ングを行い、絶縁膜をマスクにアルカリエッチングを行
って素子分離用の分離溝１０を形成する。次に、図５
（ｆ）に示すように、第１のシリコン基板（Ｎ-型）１
の表面に熱酸化等により絶縁膜を形成後、ＣＶＤ法ある
いはエピタキシャル法により多結晶シリコン層を形成
し、さらにその多結晶シリコンおよび絶縁膜を研磨する
ことにより、分離溝１０の側壁に絶縁膜１１を形成し、
その内部には多結晶シリコン層１２を埋設する。以上の
ようにして素子形成領域間が誘電体分離されたＳＯＩ基
板を得る。[0004] First, as shown in FIG. 5 (a), the first silicon substrate - and patterned by photolithography to (N type) 1 on the main surface, shallow by ion etching method or the like of the photoresist as a mask The step 2 is formed. Next, as shown in FIG. 5B, after forming an insulating film of SiO 2 by thermal oxidation or the like, the convex insulating film is removed by polishing or etching to form a first silicon substrate (N − type). 1
The exposed surface and the surface of the buried insulating film 3 thus formed are flush with each other. Next, as shown in FIG. 5C, the first silicon substrate (N − type) on which the embedded insulating film 3 is formed.
One main surface 1 and one main surface of the second silicon substrate (N + type) 4 are bonded together and heat-treated to obtain one strongly bonded composite substrate. Next, as shown in FIG.
The silicon substrate (N − type) 1 is ground and polished to a desired thickness, and the surface thereof is flattened to form the SOI layer 9. Next, as shown in FIG. 5E, an insulating film is formed on the flattened surface, patterning is performed by photolithography, and alkali etching is performed using the insulating film as a mask to form isolation trenches 10 for element isolation. To do. Next, FIG.
As shown in (f), the first silicon substrate (N − type) 1
After forming an insulating film on the surface of the insulating film by thermal oxidation or the like, a polycrystalline silicon layer is formed by a CVD method or an epitaxial method, and the polycrystalline silicon and the insulating film are polished to form an insulating film 11 on the side wall of the isolation trench 10. To form
A polycrystalline silicon layer 12 is embedded inside thereof. As described above, the SOI substrate in which the element formation regions are dielectrically separated is obtained.
【０００５】図６はＩＳＰＳＤ’９２会報にて開示され
た、横型のパワー素子と制御回路を集積することを目的
としたＳＯＩ基板の製造方法（以下、第２の従来例とい
う）を示す工程順断面図である。FIG. 6 is a process sequence showing a method of manufacturing an SOI substrate (hereinafter referred to as a second conventional example) disclosed in the ISPSD'92 bulletin for the purpose of integrating a lateral power element and a control circuit. FIG.
【０００６】まず、図６（ａ）に示されるように第１の
シリコン基板（Ｐ- 型）１０１の一主面に熱酸化により
絶縁膜１０３を形成後、その面と第２のシリコン基板
（任意の濃度・導電型）１０２の一主面とを貼り合わ
せ、熱処理を行い、強固に接合された一枚の複合基板を
得る。次に、図６（ｂ）に示すように第１のシリコン基
板（Ｐ- 型）１０１の表面を研削・研磨して所望の厚さ
とするとともにその表面を平坦化し、ＳＯＩ層９を形成
する。その後、図５（ｅ）〜（ｆ）の工程と同様の工程
を適用して、図５（ｆ）に示されるような素子形成領域
間が誘電体分離されたＳＯＩ基板を得る。First, as shown in FIG. 6A, an insulating film 103 is formed on one main surface of a first silicon substrate (P − type) 101 by thermal oxidation, and then the surface and a second silicon substrate ( One main surface of arbitrary concentration and conductivity type) 102 is bonded and heat treatment is performed to obtain a single strongly bonded composite substrate. Next, as shown in FIG. 6B, the surface of the first silicon substrate (P − type) 101 is ground and polished to have a desired thickness and the surface is planarized to form the SOI layer 9. Thereafter, steps similar to those of FIGS. 5E to 5F are applied to obtain an SOI substrate in which element formation regions are dielectrically separated as shown in FIG. 5F.
【０００７】[0007]
【発明が解決しようとする課題】高耐圧のパワー素子
と、低耐圧の素子で構成される制御回路とを１チップに
集積したパワーＩＣにおいて、制御回路に高速動作・低
消費電力・高信頼性等の特徴を持つ超薄膜ＳＯＩ素子を
集積する場合には、超薄膜ＳＯＩ素子動作時は高速化の
ためＳＯＩ層を完全空乏化させることが必要になる。そ
のためには、厚さ０．１μｍ程度が要求される。また、
素子寸法の縮小化に伴い微細化される設計ルールは常に
各寸法において±１０％以下の精度を想定しており、Ｓ
ＯＩ層の厚さ精度も同様に±１０％が要求される。In a power IC in which a high breakdown voltage power element and a control circuit composed of a low breakdown voltage element are integrated on one chip, the control circuit has high-speed operation, low power consumption, and high reliability. In the case of integrating an ultra-thin film SOI device having the above characteristics, it is necessary to completely deplete the SOI layer for speeding up the operation of the ultra-thin film SOI device. For that purpose, a thickness of about 0.1 μm is required. Also,
The design rule that is miniaturized as the element size is reduced always assumes an accuracy of ± 10% or less in each dimension.
Similarly, the thickness accuracy of the OI layer is required to be ± 10%.
【０００８】このような超薄膜ＳＯＩ素子をパワーＩＣ
の中に集積するためにＳＯＩ層の厚さを０．１μｍにし
ようとした場合、第１の従来例では、縦型パワー素子形
成領域（図５（ｆ））の低濃度領域の厚さも同時に薄く
なってしまう。通常、縦型パワー素子には数１０Ｖ〜数
１００Ｖの耐圧が要求され、そのための低濃度領域の厚
さは数μｍから数１０μｍ必要である。従って、従来の
ＳＯＩ基板では高速動作の超薄膜ＳＯＩ素子と十分な耐
圧を有するパワー素子とを同一ＳＯＩ基板に形成するこ
とができないという問題点があった。Such an ultra-thin SOI device is used as a power IC
If the thickness of the SOI layer is set to 0.1 μm for the purpose of integration in the inside, in the first conventional example, the thickness of the low-concentration region of the vertical power element formation region (FIG. 5 (f)) is also increased. It becomes thin. Normally, the vertical power element is required to have a withstand voltage of several tens of volts to several hundreds of volts, and the thickness of the low concentration region for that is required to be several μm to several tens μm. Therefore, in the conventional SOI substrate, there is a problem that an ultra-thin film SOI element that operates at high speed and a power element having a sufficient breakdown voltage cannot be formed on the same SOI substrate.
【０００９】また、横型パワー素子についても数１０Ｖ
〜数１００Ｖの耐圧が要求され、形成領域のＳＯＩ層と
して約１μｍの厚さが必要であるが、第２の従来例のＳ
ＯＩ基板では、横型パワー素子形成領域のＳＯＩ層は超
薄膜ＳＯＩ層と同じく０．１μｍ程度の厚さになってし
まうため、高速動作の超薄膜ＳＯＩ素子と十分な耐圧の
横型パワー素子とを同一ＳＯＩ基板に形成することがで
きないという問題点があった。また、第２の従来例で
は、横型パワー素子形成領域（図６（ｄ））の厚さも
０．１μｍとなり、従来の製法では十分な性能のパワー
素子を形成することはできなくなるといった問題点が生
じる。Also, with respect to the lateral power element, it is several tens of volts.
The breakdown voltage of several hundreds of V is required, and the thickness of the SOI layer in the formation region is about 1 μm.
In the OI substrate, since the SOI layer in the lateral power element formation region has a thickness of about 0.1 μm like the ultra-thin SOI layer, the ultra-thin film SOI element operating at high speed and the lateral power element having sufficient withstand voltage are the same. There is a problem in that it cannot be formed on the SOI substrate. Further, in the second conventional example, the thickness of the lateral power element formation region (FIG. 6 (d)) is also 0.1 μm, and it is impossible to form a power element with sufficient performance by the conventional manufacturing method. Occurs.
【００１０】本発明は、従来より公知となっている構造
・製法では実現できない、超薄膜ＳＯＩ素子をパワーＩ
Ｃ中に集積するためのＳＯＩ基板およびその製造方法を
提供する。The present invention provides an ultrathin film SOI device with a power I which cannot be realized by the conventionally known structure and manufacturing method.
An SOI substrate for integration in C and a method for manufacturing the same are provided.
【００１１】[0011]
【課題を解決するための手段】本発明の第１の特徴は、
第１の単結晶のシリコン基板と第２の単結晶のシリコン
基板とが貼り合わされ、第１のシリコン基板が超薄膜Ｓ
ＯＩ層として形成されているＳＯＩ基板において、いず
れか一方の単結晶のシリコン基板の貼り合わせ面側の表
面には部分的に埋め込まれた第１の絶縁膜を有し、他方
の単結晶のシリコン基板の貼り合わせ側表面には低濃度
の単結晶のシリコンのエピタキシャル層を有し、かつ、
前記超薄膜ＳＯＩ層表面から第１の絶縁膜まで達する第
２の絶縁膜が複数形成されていることを特徴とするＳＯ
Ｉ基板にある。The first feature of the present invention is to:
The first single crystal silicon substrate and the second single crystal silicon substrate are bonded together, and the first silicon substrate is the ultrathin film S.
In the SOI substrate formed as the OI layer, the first insulating film that is partially embedded is formed on the surface of the bonding surface side of one of the single crystal silicon substrates, and the other single crystal silicon substrate is formed. The surface of the substrate on the bonding side has an epitaxial layer of low-concentration single-crystal silicon, and
A plurality of second insulating films reaching from the surface of the ultra-thin SOI layer to the first insulating film are formed.
I board.
【００１２】また、（１）第１または第２の単結晶シリ
コン基板の一主面に部分的に埋め込まれた第１の絶縁膜
を形成する工程と、（２）前記第１の絶縁膜の埋め込ま
れた単結晶のシリコン基板の一主面において、単結晶シ
リコン基板の面と第１の絶縁膜の面を同一平面上の平坦
面とする工程と、（３）第１、第２の単結晶のシリコン
基板の内第１の絶縁膜が埋め込まれなかった方の単結晶
のシリコン基板の一主面に該単結晶のシリコン基板より
低濃度の単結晶シリコンをエピタキシャル成長する工程
と、（４）前記単結晶シリコン基板の面と部分的に埋め
込まれた第１の絶縁膜の面を平坦な同一平面とした面
と、前記エピタキシャル成長した単結晶のシリコン表面
とを貼り合わせ、加熱処理を行って両基板を一体化する
工程と、（５）前記一体化した貼り合わせのシリコン基
板の一主面を研磨し超薄膜ＳＯＩ層を形成する工程と、
（６）前記超薄膜ＳＯＩにおいて、第１の絶縁膜に達す
る複数の第２の絶縁膜を形成する工程と、を有すること
を特徴とするＳＯＩ基板の製造方法にある。In addition, (1) a step of forming a first insulating film partially embedded in one main surface of the first or second single crystal silicon substrate, and (2) a step of forming the first insulating film. A step of making the surface of the single crystal silicon substrate and the surface of the first insulating film flat on the same plane in one main surface of the embedded single crystal silicon substrate; and (3) the first and second single crystals. A step of epitaxially growing a single-crystal silicon substrate having a lower concentration than that of the single-crystal silicon substrate on one main surface of the single-crystal silicon substrate in which the first insulating film is not embedded in the crystalline silicon substrate; The surface of the single crystal silicon substrate and the surface of the partially buried first insulating film, which are flat and coplanar, and the surface of the epitaxially grown single crystal silicon are attached to each other, and heat treatment is applied to both surfaces. A step of integrating the substrates, and (5) the above It polished one main surface of the silicon substrate bonding that embody a step of forming a super-thin film SOI layer,
(6) In the ultra-thin SOI film, a step of forming a plurality of second insulating films reaching the first insulating film is included, which is a method of manufacturing an SOI substrate.
【００１３】本発明の第２の特徴は、第１の単結晶のシ
リコン基板と第２の単結晶のシリコン基板とが張り合わ
され、第１のシリコン基板がＳＯＩ層として形成されて
いるＳＯＩ基板において、いずれか一方の単結晶シリコ
ン基板の貼り合わせ面側表面には部分的に埋め込まれた
第１の絶縁膜を有し、前記ＳＯＩ層表面から第１の絶縁
膜まで達する複数の誘電体分離領域を有し、少なくとも
一つの前記誘電体分離領域に囲まれたＳＯＩ層内に第３
の絶縁膜と、この絶縁膜と前記ＳＯＩ層の表面との間に
形成された超薄膜ＳＯＩ層を有することを特徴とするＳ
ＯＩ基板にある。A second feature of the present invention is an SOI substrate in which a first single crystal silicon substrate and a second single crystal silicon substrate are bonded together, and the first silicon substrate is formed as an SOI layer. A plurality of dielectric isolation regions reaching a first insulating film from the surface of the SOI layer, the first insulating film partially embedded on the surface of the single crystal silicon substrate on the bonding surface side. And a third layer in the SOI layer surrounded by at least one of the dielectric isolation regions.
And an ultra-thin SOI layer formed between the insulating film and the surface of the SOI layer.
Located on the OI substrate.
【００１４】また、（１）第１または第２の単結晶のシ
リコン基板の一主面に部分的に埋め込まれた第１の絶縁
膜を形成する工程と、（２）前記第１の絶縁膜の埋め込
まれた単結晶のシリコン基板の一主面において、単結晶
シリコン基板面と第１の絶縁膜面を同一平面上の平坦面
とする工程と、（３）該平坦面と、第１、第２の単結晶
のシリコン基板の内第１の絶縁膜が埋め込まれなかった
方の単結晶シリコン基板の一主面とを貼り合わせ、加熱
処理を行って両基板を一体化する工程と、（４）前記一
体化した貼り合わせシリコン基板の一主面を研磨しＳＯ
Ｉ層を形成する工程と、（５）前記ＳＯＩ層において、
第１の絶縁膜に達する深さの分離溝を形成する工程と、
（６）前記分離溝内壁に第２の絶縁膜を形成する工程
と、（７）前記第２の絶縁膜の形成された分離溝内を誘
電体で埋設し誘電体分離領域を形成する工程と、（８）
前記誘電体分離領域で囲まれたＳＯＩ層表面に、酸素イ
オン注入および熱処理を行って第３の絶縁膜を埋め込
み、超薄膜ＳＯＩ層を形成する工程とを有することを特
徴とするＳＯＩ基板の製造方法にある。Also, (1) a step of forming a first insulating film partially embedded in one main surface of the first or second single crystal silicon substrate, and (2) the first insulating film. In the main surface of the embedded single crystal silicon substrate, the single crystal silicon substrate surface and the first insulating film surface are flat surfaces on the same plane; (3) the flat surface; A step of bonding a main surface of the single crystal silicon substrate of the second single crystal silicon substrate, in which the first insulating film is not embedded, and performing heat treatment to integrate the two substrates; 4) Polish one surface of the bonded bonded silicon substrate
A step of forming an I layer, and (5) in the SOI layer,
Forming a separation groove having a depth reaching the first insulating film;
(6) a step of forming a second insulating film on the inner wall of the isolation groove, and (7) a step of burying a dielectric material in the isolation groove in which the second insulating film is formed to form a dielectric isolation region. , (8)
A step of performing oxygen ion implantation and heat treatment on the surface of the SOI layer surrounded by the dielectric isolation region to bury the third insulating film to form an ultra-thin SOI layer. On the way.
【００１５】更に本発明の第３の特徴は、第１の単結晶
シリコン基板と第２の単結晶シリコン基板とが貼り合わ
され第１のシリコン基板がＳＯＩ層として形成されてい
るＳＯＩ基板において、いずれか一方の単結晶シリコン
基板の貼り合わせ面側表面には部分的に埋め込まれた第
１の絶縁膜および前記第１の絶縁膜を含む前記単結晶シ
リコン基板の貼り合わせ面側表面全面を覆う多結晶シリ
コン層を有し、前記ＳＯＩ層表面から第１の絶縁膜まで
達する複数の誘電体分離領域を有し、少なくとも一つの
前記誘電体分離領域に囲まれたＳＯＩ層内に超薄膜ＳＯ
Ｉ層を有するＳＯＩ基板にある。A third feature of the present invention is the SOI substrate in which the first single crystal silicon substrate and the second single crystal silicon substrate are bonded together and the first silicon substrate is formed as an SOI layer. One surface of the single crystal silicon substrate on the side of the bonding surface has a partly embedded first insulating film and the entire surface of the surface of the single crystal silicon substrate including the first insulating film on the side of the bonding surface. An ultrathin film SO having a crystalline silicon layer, a plurality of dielectric isolation regions reaching from the surface of the SOI layer to the first insulating film, and being surrounded by at least one of the dielectric isolation regions.
An SOI substrate having an I layer.
【００１６】また、前記第２の特徴で示した第（２）の
工程と第（３）の工程との間に、前記単結晶シリコン基
板面と第１の絶縁膜面の平坦面上に多結晶シリコン層を
形成し、前記多結晶シリコン層の表面を研磨して平坦面
とする工程を付加するＳＯＩ基板の製造方法にある。Further, between the step (2) and the step (3) shown in the second feature, a large number of layers are formed on the flat surface of the single crystal silicon substrate surface and the first insulating film surface. A method of manufacturing an SOI substrate further includes the step of forming a crystalline silicon layer and polishing the surface of the polycrystalline silicon layer to form a flat surface.
【００１７】本発明の第４の特徴は、第１の単結晶シリ
コン基板と第２の単結晶シリコン基板とが貼り合わされ
第１のシリコン基板がＳＯＩ層として形成されるＳＯＩ
基板において、いずれか一方または両方の単結晶シリコ
ン基板の貼り合わせ面側表面の全面に第１の絶縁膜を有
し、前記ＳＯＩ層表面から第１の絶縁膜まで達する複数
の誘電体分離領域を有し、少なくとも一つの前記誘電体
分離領域に囲まれたＳＯＩ層内に超薄膜ＳＯＩ層を有す
るＳＯＩ基板にある。A fourth feature of the present invention is that the first single crystal silicon substrate and the second single crystal silicon substrate are bonded to each other and the first silicon substrate is formed as an SOI layer.
In the substrate, a first insulating film is provided on the entire surface of the bonding surface of either one or both of the single crystal silicon substrates, and a plurality of dielectric isolation regions reaching from the SOI layer surface to the first insulating film are provided. And an ultra-thin SOI layer within the SOI layer surrounded by at least one of the dielectric isolation regions.
【００１８】また、（１）第１、第２の単結晶シリコン
基板の少なくとも一方の一主面に第１の絶縁膜を形成す
る工程と（２）第１、第２の単結晶シリコン基板の一主
面どうしを貼り合わせ、加熱処理を行って両基板を一体
化する工程と、（４）前記一体化した貼り合わせシリコ
ン基板の一主面を研磨しＳＯＩ層を形成する工程と、
（５）前記ＳＯＩ層において、第１の絶縁膜に達する深
さの分離溝を形成する工程と、（６）前記分離溝内壁に
第２の絶縁膜を形成する工程と、（７）前記第２の絶縁
膜の形成された分離溝内を誘電体で埋設し誘電体分離領
域を形成する工程と、（８）前記誘電体分離領域で囲ま
れたＳＯＩ層表面に、酸素イオン注入および熱処理を行
って第３の絶縁膜を埋め込み、超薄膜ＳＯＩ層を形成す
る工程と、を有するＳＯＩ基板の製造方法にある。Further, (1) a step of forming a first insulating film on at least one main surface of the first and second single crystal silicon substrates, and (2) a step of forming the first and second single crystal silicon substrates. A step of adhering one main surface to each other and performing a heat treatment to integrate the two substrates; and (4) a step of polishing one main surface of the integrated bonded silicon substrate to form an SOI layer,
(5) In the SOI layer, a step of forming a separation groove having a depth reaching the first insulation film, (6) a step of forming a second insulation film on the inner wall of the separation groove, and (7) the above And (2) oxygen ion implantation and heat treatment are performed on the surface of the SOI layer surrounded by the dielectric isolation region by burying a dielectric in the isolation trench in which the insulating film is formed to form a dielectric isolation region. And a step of burying the third insulating film to form an ultra-thin SOI layer.
【００１９】更に、前記第１、第２、第３の特徴で示し
た第１および第２の単結晶シリコン基板は同一導電型で
あり、一方の単結晶シリコン基板は不純物濃度が低く、
他方の単結晶シリコン基板は不純物濃度が高いＳＯＩ基
板にある。Furthermore, the first and second single crystal silicon substrates shown in the first, second and third characteristics have the same conductivity type, and one of the single crystal silicon substrates has a low impurity concentration,
The other single crystal silicon substrate is an SOI substrate having a high impurity concentration.
【００２０】[0020]
【作用】上記構成によれば、パワー素子形成領域と制御
回路形成領域とが誘電体分離され、かつ、それぞれの形
成領域に適した低濃度層の厚さが選択可能となるため、
十分な耐圧のパワー素子と高速動作の超薄膜ＳＯＩ素子
とを動作時に互いの影響を受けないようにして、一つの
チップに集積することができる。According to the above structure, the power element formation region and the control circuit formation region are dielectrically separated, and the thickness of the low concentration layer suitable for each formation region can be selected.
It is possible to integrate a power element having a sufficient breakdown voltage and an ultra-thin film SOI element that operates at high speed so as not to be influenced by each other during operation and integrated on one chip.
【００２１】[0021]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１（ａ）〜（ｅ）は本発明の第１の実施
例のＳＯＩ基板の製造方法と構造を示す製造工程順断面
図である。まず、あとで形成する素子の特性を所望のも
のとするために、例えばリンが１０14ｃｍ-3〜１０15ｃ
ｍ-3程度導入された第１のシリコン基板（Ｎ-型）１を
用意し、その一主面にフォトリソグラフィ法およびイオ
ンエッチ法を適用して、次に形成する第１の絶縁膜であ
る埋込絶縁膜３の厚さに合わせた深さの浅い段差２を形
成する［図１（ａ）］。次に図１（ｂ）に示すように、
熱酸化等により、素子分離に必要な数μｍの厚さのＳｉ
Ｏ2からなる絶縁膜を形成した後、凸になった絶縁膜を
研磨あるいはエッチングにより除去し、第１のシリコン
基板（Ｎ- 型）１の露出表面と形成された埋込絶縁膜３
の表面とが同一平面となるようにする。次に、例えばア
ンチモンが１０19ｃｍ-3程度導入された第２のシリコン
基板（Ｎ+ 型）４を用意し、その一主面に例えばリンが
１０ 14ｃｍ-3〜１０15ｃｍ-3程度導入されたエピタキシ
ャル層（Ｎ- 型）５を、後で形成する縦型パワー素子の
要求耐圧に必要な厚さで形成する。そして、図１（ｃ）
に示すように埋込絶縁膜３の形成された第１のシリコン
基板（Ｎ- 型）１の一主面と、そのエピタキシャル層
（Ｎ- 型）５面とを貼り合わせ、１１００〜１２００
℃、１〜２時間程度の熱処理を行い、強固に接合された
一枚の複合基板を得る。次に、図１（ｄ）に示すように
第１シリコン基板（Ｎ- 型）１を研削・研磨してその表
面を平坦化するとともに、厚さ０．１μｍ程度の超薄膜
ＳＯＩ層７を形成する。次に、図１（ｅ）が示すよう
に、その平坦化面にＬＯＣＯＳ法により埋込絶縁膜３に
達する厚さで素子分離用の絶縁膜８を形成する。以上の
ようにして素子形成領域間が誘電体分離されたＳＯＩ基
板を得る。図２（ａ）〜（ｅ）は本発明の第２の実施例
のＳＯＩ基板の製造方法と構造を示す製造工程順断面図
である。まず、図１（ａ）〜（ｂ）と同様の工程を適用
して得られた埋込絶縁膜３を有する第１のシリコン基板
（Ｎ- 型）１の一主面と、第２のシリコン基板（Ｎ+
型）４の一主面とを貼り合わせ、熱処理を行い、強固に
接合された一枚の複合基板を得る［図２（ａ）］。次
に、図２（ｂ）に示すように第１のシリコン基板（Ｎ-
型）１を研削・研磨してＮ- 層厚さを縦型パワー素子の
特性を得るのに必要な厚さとするとともにその表面を平
坦化し、ＳＯＩ層９を形成する。次に、図２（ｃ）に示
すように第１のシリコン基板（Ｎ- 型）１の表面に熱酸
化法等によりＳｉＯ2を形成し、フォトリソグラフィ法
によりパターニングを行った後、アルカリエッチングあ
るいはリアクティブイオンエッチ（ＲＩＥ）等により素
子分離用の分離溝１０を形成する。この時、ＳＯＩ層９
が比較的薄い（１０数μｍ以下程度）場合は分離に要す
る面積をできるだけ小さく抑えるため、ＲＩＥ法を選択
することが望ましい。次に、図２（ｄ）に示すように、
第１シリコン基板（Ｎ- 型）１の表面全面に、熱酸化法
等によりＳｉＯ2からなる絶縁膜を形成し、さらにＣＶ
Ｄ法あるいはエピタキシャル法等により多結晶シリコン
層を形成した後、研削・研磨により基板表面の絶縁膜お
よび多結晶シリコン層を除去する。そして、分離溝１０
の側壁に絶縁膜１１が形成され、さらにその内部に多結
晶シリコン１２が埋設された誘電体分離領域を得る。次
に、図２（ｅ）に示すように、第１のシリコン基板（Ｎ
- 型）１の表面全面に熱酸化法等によりＳｉＯ2からな
る絶縁膜を形成しフォトリソグラフィ法によりパターニ
ングを行った後、誘電体分離領域で囲まれたＳＯＩ層９
表面に、１０17ｃｍ-2〜１０ 18ｃｍ-2程度のドーズ量で
酸素をイオン注入し、さらに１３００℃で数時間の熱処
理を行うＳＩＭＯＸ法を適用することで、０．１μｍ程
度の厚さを持つ超薄膜ＳＯＩ層７を有し、かつ、図２
（ｅ）に示すように、縦型パワー素子形成領域とは互い
に誘電体分離された構造のＳＯＩ基板を得る。図３
（ａ）〜（ｅ）は本発明の第３の実施例のＳＯＩ基板の
製造方法と構造を示す製造工程順断面図である。まず、
図１（ａ）〜（ｂ）と同様の工程を適用して得られた埋
込絶縁膜３を有する第１のシリコン基板（Ｎ- 型）１の
一主面にＣＶＤ法等により多結晶シリコン層１４を形成
し、研磨により平坦化した面と、第２のシリコン基板
（Ｎ+ 型）４の一主面とを貼り合わせ、熱処理を行い、
強固に接合された一枚の複合基板を得る［図３
（ａ）］。この時、多結晶シリコン層１４は埋込絶縁膜
３を有する第１のシリコン基板（Ｎ- 型）１の表面をよ
り平坦にする目的で形成されており、埋込絶縁膜３を有
する第１のシリコン基板（Ｎ- 型）１の表面の平坦化研
磨を省略した場合でも貼り合わせ可能とするものであ
る。また多結晶シリコン層１４には必要に応じて不純物
を添加し低抵抗化をはかる。次に、図２（ｂ）〜（ｅ）
と同様の工程を適用をして、０．１μｍ程度の厚さを持
つ超薄膜ＳＯＩ層７を有し、かつ、図３（ｅ）に示す縦
型パワー素子形成領域とは互いに誘電体分離された構造
のＳＯＩ基板を得る。図４（ａ）〜（ｅ）は本発明の第
４の実施例のＳＯＩ基板の製造方法と構造を示す製造工
程順断面図である。まず、図４（ａ）に示されるように
第１のシリコン基板（Ｎ- 型）１の一主面に熱酸化によ
り絶縁膜１０３を形成後、その面と第２のシリコン基板
（任意の濃度・導電型）１０２の一主面とを貼り合わ
せ、熱処理を行い、強固に接合された一枚の複合基板を
得る。次に、図２（ｂ）〜（ｅ）と同様の工程を適用し
て、０．１μｍ程度の厚さを持つ超薄膜ＳＯＩ層を有
し、かつ、図４（ｅ）に示すように横型パワー素子形成
領域とは互いに誘電体分離された構造のＳＯＩ基板を得
る。Embodiments of the present invention will now be described with reference to the drawings.
Will be explained. 1A to 1E show a first embodiment of the present invention.
Sectional view of manufacturing process showing manufacturing method and structure of example SOI substrate
FIG. First, the characteristics of the device to be formed later
For example, phosphorus is 1014cm-3-10Fifteenc
m-3First introduced silicon substrate (N-Type 1
Prepare the photolithography method and
A first insulating film to be formed next by applying an etching method.
To form a shallow step 2 having a depth corresponding to the thickness of the buried insulating film 3
[Fig. 1 (a)]. Next, as shown in FIG.
Si with a thickness of several μm required for element isolation due to thermal oxidation
O2After forming the insulating film consisting of
First silicon removed by polishing or etching
Substrate (N- Type) 1 exposed surface and buried insulating film 3 formed
Be flush with the surface of. Then, for example,
Nchimon 1019cm-3Second silicon introduced to a degree
Substrate (N+ Type) 4 is prepared, and for example, phosphorus is on one main surface
10 14cm-3-10Fifteencm-3Degree introduced epitaxy
Layer (N- Of the vertical power device to be formed later.
It is formed with the thickness necessary for the required breakdown voltage. And FIG. 1 (c)
The first silicon having the buried insulating film 3 formed thereon as shown in FIG.
Substrate (N- Type) 1 main surface and its epitaxial layer
(N- (Type) 5 surfaces are pasted together, 1100 to 1200
Heat treatment was carried out for 1 to 2 hours at ℃, and a strong bond was obtained.
Obtain a composite substrate. Next, as shown in FIG.
First silicon substrate (N- Mold) 1 is ground and polished, and its table
Ultra thin film with a flat surface and a thickness of about 0.1 μm
The SOI layer 7 is formed. Next, as shown in FIG.
Then, the embedded insulating film 3 is formed on the flattened surface by the LOCOS method.
The insulating film 8 for element isolation is formed to a thickness that reaches it. More than
Thus, the SOI group in which the element formation regions are dielectrically separated
Get the board. 2 (a) to (e) are the second embodiment of the present invention.
Of manufacturing steps showing the manufacturing method and structure of the SOI substrate
It is. First, the same steps as those in FIGS. 1A to 1B are applied.
First silicon substrate having a buried insulating film 3 obtained by
(N- Type) 1 main surface and the second silicon substrate (N+
(Mold) 4 is attached to one main surface and heat treatment is performed to firmly
One bonded composite substrate is obtained [FIG. 2 (a)]. Next
Then, as shown in FIG. 2B, the first silicon substrate (N-
Mold) 1 is ground and polished to N- The layer thickness of the vertical power device
Make it as thick as necessary to obtain the characteristics and flatten its surface.
It is realized and the SOI layer 9 is formed. Next, as shown in FIG.
So that the first silicon substrate (N- Type) 1 surface with hot acid
SiO by the chemical method2Forming photolithography method
After patterning by
Rui is made by reactive ion etching (RIE), etc.
The separation groove 10 for separating the child is formed. At this time, the SOI layer 9
Is required for separation when the thickness is relatively thin (about 10 μm or less)
The RIE method to minimize the area
It is desirable to do. Next, as shown in FIG.
First silicon substrate (N- Type) 1 on the entire surface, thermal oxidation method
SiO etc.2Insulating film consisting of
Polycrystalline silicon by D method or epitaxial method
After forming the layer, the insulating film on the substrate surface is ground and polished.
And removing the polycrystalline silicon layer. And the separation groove 10
The insulating film 11 is formed on the side wall of the
A dielectric isolation region in which the crystalline silicon 12 is embedded is obtained. Next
As shown in FIG. 2 (e), the first silicon substrate (N
- (Type) 1 on the entire surface by thermal oxidation or the like2Empty
An insulating film is formed and patterned by photolithography.
SOI layer 9 surrounded by a dielectric isolation region
10 on the surface17cm-2-10 18cm-2With a dose of about
Ion-implant oxygen and heat treatment at 1300 ℃ for several hours.
By applying the SIMOX method for processing, about 0.1 μm
2 having an ultra-thin SOI layer 7 having a thickness of 2 degrees and FIG.
As shown in (e), the vertical power element formation region is
An SOI substrate having a structure in which a dielectric is separated is obtained. Figure 3
(A)-(e) of the SOI substrate of the third embodiment of the present invention
It is a manufacturing-process order sectional drawing which shows a manufacturing method and a structure. First,
An embedding obtained by applying the same steps as in FIGS.
The first silicon substrate (N- Type) 1
A polycrystalline silicon layer 14 is formed on one main surface by a CVD method or the like.
Surface planarized by polishing and the second silicon substrate
(N+ (Type) 4 is bonded to one main surface, heat treatment is performed,
Obtain a strongly bonded composite substrate [Fig. 3
(A)]. At this time, the polycrystalline silicon layer 14 is a buried insulating film.
First silicon substrate (N- Type) 1 surface
It is formed for the purpose of flattening and has a buried insulating film 3.
The first silicon substrate (N- Type) 1 surface flattening
Even if the polishing is omitted, it is possible to bond them together.
You. Further, the polycrystalline silicon layer 14 may contain impurities as necessary.
Is added to reduce the resistance. Next, FIGS. 2B to 2E.
Apply the same process as above, and have a thickness of about 0.1 μm.
Having an ultra-thin SOI layer 7 and having the vertical structure shown in FIG.
Type power element formation region is dielectrically separated from each other
To obtain an SOI substrate. 4 (a) to (e) show the first embodiment of the present invention.
Manufacturing method showing structure and structure of SOI substrate of Example 4
FIG. First, as shown in FIG.
First silicon substrate (N- Type) 1 on one main surface by thermal oxidation
After forming the insulating film 103, the surface and the second silicon substrate
Laminate with one main surface (arbitrary concentration and conductivity type) 102
And heat-treat it to form a single, tightly bonded composite substrate.
obtain. Next, the same steps as those in FIGS. 2B to 2E are applied.
The ultra-thin SOI layer with a thickness of about 0.1 μm.
And, as shown in FIG. 4 (e), a lateral power element is formed.
An SOI substrate having a structure in which a region is dielectrically separated from each other is obtained.
You.
【００２２】[0022]
【発明の効果】以上説明したように、本発明によれば、
図１〜４に示すように、パワー素子形成領域と制御回路
形成領域とが厚い絶縁膜によって互いに誘電体分離さ
れ、かつ、それぞれの形成領域に適した低濃度層の厚さ
が選択可能となるため、十分な耐圧のパワー素子と高速
動作の超薄膜ＳＯＩ素子とを、動作時に互いの影響を受
けないようにして一つのチップに集積することができ
る。特に、低濃度のエピタキシャル層をもつシリコン基
板を貼り合わせることにより、縦型パワー素子を集積す
るということを可能とするとともに、エピタキシャル層
厚さを変えることで幅広いパワー素子耐圧に対応するこ
とを可能とする。また、数μｍの厚い絶縁膜上に形成さ
れた比較的厚いＳＯＩ層を有するＳＯＩ基板にＳＩＭＯ
Ｘ法を用い超薄膜ＳＯＩ層を形成することにより、超薄
膜ＳＯＩ層の膜厚制御性がより向上するとともに、ＳＩ
ＭＯＸ法で形成可能な約０．３μｍ以下の厚さのシリコ
ン酸化膜では耐圧の点で分離不可能だった高耐圧のパワ
ー素子を集積することが可能となる。更に、貼り合わせ
面を多結晶シリコンの平坦面とすることにより、単結晶
シリコンと絶縁膜の混在する面を平坦にする工程を省略
した場合でも十分貼り合わせ可能とする。As described above, according to the present invention,
As shown in FIGS. 1 to 4, the power element formation region and the control circuit formation region are dielectrically separated from each other by a thick insulating film, and the thickness of the low concentration layer suitable for each formation region can be selected. Therefore, the power element having a sufficient breakdown voltage and the ultra-thin film SOI element operating at high speed can be integrated on one chip without being influenced by each other during operation. In particular, it is possible to integrate vertical power devices by bonding silicon substrates with low-concentration epitaxial layers, and it is possible to support a wide range of power device breakdown voltage by changing the epitaxial layer thickness. And Moreover, SIMO is applied to an SOI substrate having a relatively thick SOI layer formed on a thick insulating film of several μm.
By forming the ultra-thin film SOI layer using the X method, the film thickness controllability of the ultra-thin film SOI layer is further improved, and SI
It is possible to integrate power devices with high withstand voltage, which cannot be separated in terms of withstand voltage with a silicon oxide film having a thickness of about 0.3 μm or less that can be formed by the MOX method. Further, by using a flat surface of polycrystalline silicon as the bonding surface, sufficient bonding can be performed even when the step of flattening the surface where the single crystal silicon and the insulating film are mixed is omitted.
【図１】本発明の第１の実施例のＳＯＩ基板の製造方法
を示す工程断面図。FIG. 1 is a process sectional view showing a method for manufacturing an SOI substrate according to a first embodiment of the present invention.
【図２】本発明の第２の実施例のＳＯＩ基板の製造方法
を示す工程断面図。FIG. 2 is a process sectional view showing a method for manufacturing an SOI substrate according to a second embodiment of the present invention.
【図３】本発明の第３の実施例のＳＯＩ基板の製造方法
を示す工程断面図。FIG. 3 is a process sectional view showing a method for manufacturing an SOI substrate according to a third embodiment of the present invention.
【図４】本発明の第４の実施例のＳＯＩ基板の製造方法
を示す工程断面図。FIG. 4 is a process sectional view showing the method of manufacturing the SOI substrate of the fourth embodiment of the present invention.
【図５】第１の従来例のＳＯＩ基板の製造方法を示す工
程断面図。FIG. 5 is a process sectional view showing the method of manufacturing the SOI substrate of the first conventional example.
【図６】第２の従来例のＳＯＩ基板の製造方法を示す工
程断面図。FIG. 6 is a process cross-sectional view showing the method of manufacturing the SOI substrate of the second conventional example.
１ 第１のシリコン基板（Ｎ- 型） ２ 浅い段差 ３ 埋込絶縁膜（第１の絶縁膜） ４ 第２のシリコン基板（Ｎ+ 型） ５ エピタキシャル層（Ｎ- 型） ６ 貼り合わせ面 ７ 超薄膜ＳＯＩ層 ８ 絶縁膜（第２の絶縁膜） ９ ＳＯＩ層 １０ 分離溝 １１ 絶縁膜（第２の絶縁膜） １２ 多結晶シリコン １３ 埋込絶縁膜（第３の絶縁膜） １４ 多結晶シリコン １０１ 第１のシリコン基板（Ｐ- 型） １０２ 第２のシリコン基板（任意の濃度・導電型） １０３ 絶縁膜1 First Silicon Substrate (N − Type) 2 Shallow Step 3 Embedded Insulating Film (First Insulating Film) 4 Second Silicon Substrate (N + Type) 5 Epitaxial Layer (N − Type) 6 Bonding Surface 7 Ultra-thin SOI layer 8 Insulating film (second insulating film) 9 SOI layer 10 Separation groove 11 Insulating film (second insulating film) 12 Polycrystalline silicon 13 Embedded insulating film (third insulating film) 14 Polycrystalline silicon 101 First Silicon Substrate (P - Type) 102 Second Silicon Substrate (Arbitrary Concentration / Conductivity Type) 103 Insulating Film
Claims (9)
晶シリコン基板とが貼り合わされたＳＯＩ基板におい
て、前記第１の単結晶シリコン基板が、その貼り合わせ
面側の表面に部分的に埋め込まれた第１の絶縁膜と、前
記絶縁膜と前記貼り合わせ面の反対側の、第１の単結晶
シリコン基板の表面との間に形成された超薄膜ＳＯＩ層
とを有し、第２の単結晶シリコン基板の貼り合わせ面表
面には低濃度の単結晶シリコンエピタキシャル層を有
し、かつ、前記超薄膜ＳＯＩ層側表面から第１の絶縁膜
まで達する第２の絶縁膜が複数形成されていることを特
徴とするＳＯＩ基板。1. An SOI substrate in which a first single crystal silicon substrate and a second single crystal silicon substrate are bonded to each other, wherein the first single crystal silicon substrate is partially bonded to the bonding surface side surface. A first insulating film embedded, and an ultrathin film SOI layer formed between the insulating film and a surface of the first single crystal silicon substrate opposite to the bonding surface, Has a low-concentration single crystal silicon epitaxial layer on the surface of the single crystal silicon substrate, and a plurality of second insulating films reaching from the surface of the ultra-thin SOI layer side to the first insulating film are formed. An SOI substrate characterized in that
面に部分的に埋め込まれた第１の絶縁膜を形成する工程
と、 （２）前記第１の絶縁膜の埋め込まれた第１の単結晶シ
リコン基板の一主面において、単結晶シリコン基板面と
第１の絶縁膜面を同一平面上の平坦面とする工程と、 （３）前記第２の単結晶シリコン基板の一主面に該単結
晶シリコン基板より低濃度の単結晶シリコンをエピタキ
シャル成長する工程と、 （４）前記単結晶シリコン基板面と部分的に埋め込まれ
た第１の絶縁膜面を平坦な同一平面とした第１のシリコ
ン基板の一主面と前記エピタキシャル成長した第２の単
結晶シリコン表面とを貼り合わせ、加熱処理を行って両
基板を一体化する工程と、 （５）前記一体化して貼り合わせられた前記第１の絶縁
膜の埋め込まれた第１のシリコン基板の他主面を研磨し
超薄膜ＳＯＩ層を形成する工程と、 （６）前記超薄膜ＳＯＩ層において、第１の絶縁膜に達
する第２の絶縁膜を形成する工程とを有することを特徴
とするＳＯＩ基板の製造方法。2. A step of (1) forming a first insulating film which is partially embedded in a main surface of a first single crystal silicon substrate, and (2) a step of filling the first insulating film. A step of making the single crystal silicon substrate surface and the first insulating film surface flat on the same plane in the one main surface of the first single crystal silicon substrate; and (3) one of the second single crystal silicon substrate. A step of epitaxially growing a single crystal silicon having a concentration lower than that of the single crystal silicon substrate on the main surface, and (4) the first insulating film surface partially buried with the single crystal silicon substrate surface is made flat and coplanar. A step of bonding one main surface of the first silicon substrate and the surface of the second epitaxially grown second single crystal silicon and performing a heat treatment to integrate the two substrates; and (5) the integrated bonding Embedded with the first insulating film And polishing the other main surface of the silicon substrate 1 to form an ultra-thin SOI layer, and (6) forming a second insulating film reaching the first insulating film in the ultra-thin SOI layer. A method for manufacturing an SOI substrate, comprising:
結晶のシリコン基板とが貼り合わされ、第１のシリコン
基板がＳＯＩ層として形成されているＳＯＩ基板におい
て、いずれか一方の単結晶シリコン基板の貼り合わせ面
側表面には部分的に埋め込まれた第１の絶縁膜を有し、
前記ＳＯＩ層表面から第１の絶縁膜まで達する複数の誘
電体分離領域を有し、少なくとも一つの前記誘電体分離
領域に囲まれたＳＯＩ層内に第３の絶縁膜と、この絶縁
膜と前記ＳＯＩ層の表面との間に形成された超薄膜ＳＯ
Ｉ層とを有することを特徴とするＳＯＩ基板。3. An SOI substrate in which a first single crystal silicon substrate and a second single crystal silicon substrate are bonded to each other, and the first silicon substrate is formed as an SOI layer. The silicon substrate has a first insulating film partially embedded on the bonding surface side,
A plurality of dielectric isolation regions extending from the surface of the SOI layer to the first insulation film, and a third insulation film in the SOI layer surrounded by at least one of the dielectric isolation regions; Ultra thin film SO formed between the surface of the SOI layer
An SOI substrate having an I layer.
のシリコン基板の貼り合わせ面側の表面の全面を覆う多
結晶シリコン層が設けられている請求項３記載のＳＯＩ
基板。4. The SOI according to claim 3, wherein a polycrystalline silicon layer is provided to cover the entire surface of the bonding surface side of the single crystal silicon substrate in which the first insulating film is embedded.
substrate.
コン基板の貼り合わせ面側の表面の全面に第１の絶縁膜
が設けられている請求項３記載のＳＯＩ基板。5. The SOI substrate according to claim 3, wherein the first insulating film is provided on the entire surface of the bonding surface side of either one or both of the single crystal silicon substrates.
は同一導電型であり、第１の単結晶シリコン基板は不純
物濃度が低く、第２の単結晶シリコン基板は不純物濃度
が高いことを特徴とする請求項１、３又は４記載のＳＯ
Ｉ基板。6. The first and second single crystal silicon substrates have the same conductivity type, the first single crystal silicon substrate has a low impurity concentration, and the second single crystal silicon substrate has a high impurity concentration. SO according to claim 1, 3 or 4, characterized in that
I substrate.
ン基板の一主面に部分的に埋め込まれた第１の絶縁膜を
形成する工程と、 （２）前記第１の絶縁膜の埋め込まれた単結晶シリコン
基板の一主面において、単結晶シリコン基板面と第１の
絶縁膜面を同一平面上の平坦面とする工程と、 （３）該平坦面と、第１、第２の単結晶シリコン基板の
内第１の絶縁膜が埋め込まれなかった方の単結晶シリコ
ン基板の一主面とを貼り合わせ、加熱処理を行って両基
板一体化する工程と、 （４）前記一体化した貼り合わせシリコン基板の一主面
を研磨しＳＯＩ層を形成する工程と、 （５）前記ＳＯＩ層において、第１の絶縁膜に達する深
さの分離溝を形成する工程と、 （６）前記分離溝内壁に第２絶縁膜を形成する工程と （７）前記第２の絶縁膜の形成された分離溝内を誘電体
で埋設し誘電体分離領域を形成する工程と、 （８）前記誘電体分離領域で囲まれたＳＯＩ層表面に、
酸素イオン注入および熱処理を行って第３の絶縁膜を埋
め込み、超薄膜ＳＯＩ層を形成する工程と、を有するこ
とを特徴とするＳＯＩ基板の製造方法。7. (1) A step of forming a first insulating film partially embedded in one main surface of a first or second single crystal silicon substrate, and (2) the first insulating film. In the main surface of the embedded single crystal silicon substrate, the single crystal silicon substrate surface and the first insulating film surface are flat surfaces on the same plane; (3) the flat surface; A step of adhering one main surface of the single crystal silicon substrate of the second single crystal silicon substrate in which the first insulating film is not embedded and performing heat treatment to integrate the two substrates; A step of polishing one main surface of the bonded bonded silicon substrate to form an SOI layer; (5) a step of forming a separation groove having a depth reaching the first insulating film in the SOI layer; ) A step of forming a second insulating film on the inner wall of the separation groove, and (7) Shape of the second insulating film Filling the inside of the formed isolation groove with a dielectric to form a dielectric isolation region, (8) on the surface of the SOI layer surrounded by the dielectric isolation region,
And a step of performing oxygen ion implantation and heat treatment to bury the third insulating film to form an ultra-thin SOI layer, a method for manufacturing an SOI substrate.
に、第１の絶縁膜の埋め込まれた単結晶のシリコン基板
面と第１の絶縁膜面の平坦面上に多結晶シリコン層を形
成し、前記多結晶シリコン層の表面を研磨して平坦面と
する工程を有する請求項７記載のＳＯＩ基板の製造方
法。8. A single crystal silicon substrate surface in which a first insulating film is embedded and a flat surface of the first insulating film surface between the second (2) step and the (3) step. 8. The method for manufacturing an SOI substrate according to claim 7, further comprising the step of forming a polycrystalline silicon layer and polishing the surface of the polycrystalline silicon layer to form a flat surface.
くとも一方の一主面に第１の絶縁膜を形成する工程に続
いて、第１、第２の単結晶シリコン基板の一主面どうし
を貼り合わせ、加熱処理を行って両基板を一体化する、
請求項７記載のＳＯＩ基板の製造方法。9. A main surface of the first and second single crystal silicon substrates, following the step of forming a first insulating film on the main surface of at least one of the first and second single crystal silicon substrates. Bonding together, heat treatment to integrate both boards,
The method for manufacturing an SOI substrate according to claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7150464A JP2755215B2 (en) | 1995-06-16 | 1995-06-16 | Method for manufacturing SOI substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7150464A JP2755215B2 (en) | 1995-06-16 | 1995-06-16 | Method for manufacturing SOI substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH098128A true JPH098128A (en) | 1997-01-10 |
| JP2755215B2 JP2755215B2 (en) | 1998-05-20 |
Family
ID=15497496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7150464A Expired - Lifetime JP2755215B2 (en) | 1995-06-16 | 1995-06-16 | Method for manufacturing SOI substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2755215B2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01112746A (en) * | 1987-10-27 | 1989-05-01 | Nippon Denso Co Ltd | Semiconductor device |
| JPH03126255A (en) * | 1989-10-11 | 1991-05-29 | Nippondenso Co Ltd | Semiconductor device and manufacture thereof |
| JPH0429353A (en) * | 1990-05-24 | 1992-01-31 | Sharp Corp | Semiconductor device |
| JPH0555494A (en) * | 1991-08-22 | 1993-03-05 | Yokogawa Electric Corp | High-voltage mos ic |
| JPH05129536A (en) * | 1991-11-01 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1995
- 1995-06-16 JP JP7150464A patent/JP2755215B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01112746A (en) * | 1987-10-27 | 1989-05-01 | Nippon Denso Co Ltd | Semiconductor device |
| JPH03126255A (en) * | 1989-10-11 | 1991-05-29 | Nippondenso Co Ltd | Semiconductor device and manufacture thereof |
| JPH0429353A (en) * | 1990-05-24 | 1992-01-31 | Sharp Corp | Semiconductor device |
| JPH0555494A (en) * | 1991-08-22 | 1993-03-05 | Yokogawa Electric Corp | High-voltage mos ic |
| JPH05129536A (en) * | 1991-11-01 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2755215B2 (en) | 1998-05-20 |
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