JPH098060A - Semiconductor device - Google Patents

Abstract

PURPOSE: To ensure electric contact and radiation bus to a mounting surface when precision of flatness of the mounting surface of a mounting board or a package is low, by coupling source electrodes through air bridge wiring, and bonding a chip to the mounting surface of medium for mounting by using mounting material. CONSTITUTION: Source electrodes 2, 2', 2'' and a plurality of gate electrodes 3 and drain electrodes 4 are arranged on a semiconductor substrate 1, and field-effect transistor element parts are formed. At least the two or more source electrodes 2, 2', 2'' or the drain electrodes 4 are coupled together by using air bridge wring. A semiconductor chip 30 like this is mounted, and the air bridge wiring surface of the semiconductor chip 30 is bonded to the mounting surface 10 of medium 16 for mounting the semiconductor chip 30 by using mounting material 7, or thermally bonded with pressure. For example, wiring metal 5 constituted of Au is bonded to a heat sink 16 by using mounting solder material 7 like AuSn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a flip-chip type structure in which a field effect transistor (hereinafter abbreviated as "high output FET") capable of obtaining high output power is mounted.

[0002]

2. Description of the Related Art A high-power FET using GaAs is formed by arranging a plurality of FETs having a small gate width in parallel. However, most of the DC input power input to obtain high output power is high. Since it becomes heat, it is important to dissipate heat efficiently. The FET is composed of three terminals, source, drain, and gate. When multiple FETs are connected in parallel, one terminal will always intersect with another terminal. An increase in the parasitic capacitance of electric charge becomes a problem at the crossing point of.

Therefore, a semiconductor device of a high-power FET having a flip-chip type structure has been developed for the purpose of reducing the parasitic capacitance and efficient heat dissipation (for example, published by Institute of Electronics, Information and Communication Engineers, Masumi Fukuda, Yasushi Hirachi). Goto, "Basics of GaAs field effect transistors", pp. 198-199).

A conventional semiconductor device having a flip-chip type structure will be described with reference to FIG. FIG. 5 is a cross-sectional view of a conventional semiconductor device having a flip-chip type structure.

As shown in FIG. 5, the semiconductor chip 30 is
After arranging the source electrode 2, the gate electrode 3 and the drain electrode 4 on the semiconductor substrate 1 by the existing FET forming technique (for example, ion implantation technique, etching technique, metal forming technique, etc.), Au of about 20 μm or the like is formed on the source electrode 2. Source pad 18 is formed by subjecting the source electrode 2, gate electrode 3 and drain electrode 4 to 3
I try to separate them dimensionally. The semiconductor chip 30 manufactured in this manner is mounted with the bonding material 19 on the mounting area surface 10 on the mounting substrate 6 (or the mounting package) with the FET formation surface facing down.

[0006]

However, in the semiconductor device shown in FIG. 5, since the source electrodes 2 each subjected to the thick plating process are independently in contact with the mount surface 10 of the mounting substrate 6 (or package), the semiconductor device The mounting surface 10 of the mounting substrate 6 on which the chip 30 is mounted is required to have highly accurate flatness. When the flatness of the mount surface 10 is low and there are many irregularities, there is a high risk that the source electrode 2 that does not contact the mount surface 10 is generated.

For example, in FIG. 6A, the conventional semiconductor chip 3 shown in FIG. 5 is mounted on the mount surface 10 'having low flatness accuracy.
The figure shows the case where 0 is mounted, and the semiconductor chip 30
Then, the source electrodes 2, 2 ′, 2 ″ formed on the substrate 1
Source pads 18, 18 ', 18 "are formed on the respective surfaces, but the source pad 18' is not in contact with the mounting surface 10 'because there is a recess in the mounting surface 10'.
If there is the source pad 18 'that does not contact the mount surface 10', the source electrode 2'connected to the source pad 18 'is electrically opened, which interferes with the normal operation of the FET. Further, if the source pad 18 'is also intended for heat dissipation, the heat dissipation path will be cut off between the source pad 18' and the mount surface 10 ', so that the heat dissipation from the source electrode 2'is extremely. In the case of a power element or the like that deteriorates and heat affects the characteristics, it may cause deterioration of characteristics, oscillation, or destruction.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an electrical connection to a mounting surface of a mounting substrate for mounting a semiconductor chip or a package even if the mounting surface has low flatness accuracy. It is an object of the present invention to provide a semiconductor device having a flip chip type structure capable of ensuring a contact and heat dissipation path.

[0009]

In order to achieve the above-mentioned object, a semiconductor device according to the present invention comprises a field effect transistor element portion formed by arranging a plurality of source electrodes, gate electrodes and drain electrodes on a semiconductor substrate. A semiconductor chip in which at least two or more source electrodes of the field effect transistor element part are connected to each other by air bridge wiring is mounted, and an air bridge wiring surface of the semiconductor chip is mounted on a mount surface of a medium on which the semiconductor chip is mounted. It is characterized by being bonded or thermally pressure-bonded by.

Another aspect of the semiconductor device according to the present invention is that a plurality of source electrodes, gate electrodes, and drain electrodes are arranged on a semiconductor substrate to form a field effect transistor element part, and the field effect transistor element part is formed. A dielectric layer is formed on the gate electrode, or on one of the gate electrode and one of the drain electrode and the source electrode, and a mounting conductor layer is formed on the dielectric layer and the electrode not covered by the dielectric layer. A semiconductor chip, on which electrodes formed and not covered by the dielectric layer are electrically joined, is mounted, and the mounting conductor layer of the semiconductor chip adheres or heats the mounting surface of the medium to be mounted by a mounting material. It is characterized by being crimped.

[0011]

According to the semiconductor device of the present invention, the source electrode of the field effect transistor element portion of the semiconductor chip is bonded by the air bridge wiring, and then bonded or thermally attached to the mount surface of the medium to be mounted by the mount material. Since it is pressure-bonded to the mounting surface, even if the accuracy of the flatness of the mounting surface is low, it is possible to secure electrical contact and a heat dissipation path to the mounting surface.

According to a second aspect of the present invention, in a semiconductor device, a dielectric layer is formed on a gate electrode and a drain electrode of a field effect transistor element portion of a semiconductor chip, and the dielectric layer and the source electrode are mounted. Since the conductor layer for mounting is formed and the conductor layer for mounting is electrically bonded to the source electrode and then bonded or thermally pressure-bonded to the mount surface of the medium to be mounted by the mount material,
It is possible to secure electrical contact with the mount surface, prevent the deformation due to an external force applied when the semiconductor chip is mounted by forming the dielectric layer, and further improve the heat dissipation effect.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a semiconductor device according to the present invention. FIG. 1 (a) is a plan view of a semiconductor chip 30 and FIG. 1 (b) is a semiconductor shown in FIG. 1 (a). Chip 3
0 is mounted on the heat sink 16 of the package, a cross-sectional view of the semiconductor device 31 taken along line XX ′ in FIG. 1A, and FIG. 1C is the semiconductor chip 3 shown in FIG.
FIG. 2 is a cross-sectional view of the semiconductor device 31 taken along line YY ′ in FIG. 1A with 0 mounted on the heat sink 16 of the package.

As shown in FIG. 1A, a semiconductor chip 30 to be mounted on the semiconductor device according to this embodiment has a source electrode 2 of a FET element formed on a GaAs substrate 1 by an existing technique.
2 ′, 2 ″, a gate electrode 3 and a drain electrode 4 are formed. The gate electrode 3 is wired to a gate pad 8 provided for connection with an external circuit. , Is connected to a drain pad 9 provided for connection with an external circuit.In FIG. 1 (a), hatched portions indicated by reference numeral 5 are source electrodes 2, 2 ', 2 ".
As shown in FIG. 1B, the source electrodes 2, 2 ′ and 2 ″ are air-bridged with the wiring metal 5 having a thickness of about 5 μm by the existing air-bridge wiring technique. ing.

The semiconductor chip 30 configured as described above
As shown in FIGS. 1 (b) and 1 (c), the wiring metal 5 is placed on the mounting surface of the heat sink 16 of the package with the wiring metal 5 facing downward, and is thermally pressure-bonded or adhered by the mounting brazing material 7 such as AuSn. The drain pad 9 and the gate pad 8 are thermally pressure-bonded or bonded to the external lead-out leads 12 and 11 of the package and the mount brazing material 7'such as AuSn. further,
The semiconductor chip 30, the heat sink 16, and the external lead-out leads 11 and 12 are fixed by a mold resin 14 such as epoxy filled in the mold area 13.

Here, a method of thermally press-bonding or bonding the heat sink 16 of the package and the semiconductor chip 30 will be described. First, the mounting surface 10 of the heat sink 16 is Sn-plated, the wiring metal 5 is made of Au, and the semiconductor chip 30 is mounted on the mounting surface 10 with the wiring metal 5 facing downward while the heat sink 16 is heated to about 350 ° C. When mounted on, the Sn of the mount surface 10 and the Au of the wiring metal 5 form a eutectic of AuSn and can be bonded. When using GaAs or the like for the semiconductor substrate 1, AnSn is generally used as the mount brazing material 7.
When a Si semiconductor is used for the semiconductor substrate 1, AuSi, A
uGe or the like is also used. Further, when it is desired to bond at a low temperature, it is possible to use a silver paste.

FIG. 2A shows the semiconductor device 3 described with reference to FIG.
FIG. 2B is a plan view of the lead frame 15 of the package for manufacturing 1., and FIG. 2B is a sectional view of the semiconductor device 31 according to the first embodiment after cutting the leads and molding the leads.

In FIG. 2A, the lead frame 15
Is formed by punching a metal plate such as copper or kovar material having a thickness of about 0.5 mm by press working and subjecting it to a surface treatment such as silver plating. This lead frame 15 is shown in FIG.
The semiconductor chip 30 shown in (1) is bonded or pressure-bonded to the mount surface 10 of the heat sink 6 with the wiring metal 5 facing downward, and the drain pad 9 and the gate pad 8 are bonded or pressure-bonded to the external lead-out leads 12 and 11. And
As shown in FIG. 2B, after fixing the semiconductor chip 30 and the lead frame 15 with the molding resin 14, the semiconductor device 31 according to the present embodiment is processed through the steps of cutting the leads of the external leads 12 and 11 and forming the leads. Complete.

Here, when the semiconductor chip 30 according to the first embodiment is mounted on the mounting surface 10 'of the substrate 6'having low flatness accuracy as shown in FIG. 6B, the FET element of the semiconductor chip 30 is mounted. Source electrode 2 arranged in the
Since 2 ′ and 2 ″ are also electrically coupled by the air bridge wiring by the wiring metal 5, they are not electrically opened regardless of the flatness of the mount surface 10 ′.

Further, since the wiring metal 5 connecting the source electrodes 2, 2 ', 2 "also functions as a heat radiation path, the heat radiation is extremely high when the semiconductor chip 30 is mounted on the mounting surface 10' having a large unevenness. The generation of a bad source electrode can be prevented.

FIG. 3 shows a second embodiment of the semiconductor device according to the present invention. FIG. 3 (a) is a plan view of the semiconductor chip 30, and FIG. 3 (b) is the semiconductor shown in FIG. 3 (a). Chip 3
4 is a cross-sectional view of the semiconductor device 31 taken along line XX ′ in FIG. 3A with 0 mounted on the mount surface 10 of the heat sink 16 of the package.

In FIG. 3, the same reference numerals as those in FIG. 1 represent the same components, and as shown in FIG. 3A, the planar configuration of the semiconductor chip 30 of the semiconductor device according to the second embodiment is This is the same as the first embodiment shown in FIG. Therefore, the description of FIG. 3A is omitted, and FIG.
In FIG. 1, the components different from those in FIG. 1B will be mainly described.

In the second embodiment, as shown in FIG. 3B, the wiring of the wiring metal 36 connecting the source electrodes 2, 2 ', 2 "is the same as in the first embodiment. The feature is that the element forming portions of the gate electrode 3 and the drain electrode 4 are covered with the dielectric layer 17 instead of by wiring.

Next, a method of manufacturing the semiconductor chip 30 in the second embodiment will be described. The source electrodes 2, 2'of the FET element are formed on the GaAs substrate 1 by the existing technology.
After 2 ″, the gate electrode 3 and the drain electrode 4 are formed, a dielectric film 17 such as SiN is formed on the surface of the semiconductor chip 30 by the CVD method or the like. Next, the source electrodes 2, 2 ′,
2 "and the gate pad 8 and the portion of the dielectric pad 17 at the portion of the drain pad 9 are opened by a dry etching technique, and then a metal for a plating pass is sputtered on the whole surface, and then the wiring for the source electrodes 2, 2 ', 2" is required Wiring metal 3 only on the part
The resist is patterned so that 6 is plated, and the wiring metal 36 is formed by the plating technique. After that, the semiconductor chip 30 can be manufactured by etching the plating pass metal by the dry etching technique using the wiring metal 36 as a mask.

The semiconductor chip 30 configured as described above
As shown in FIG. 3B, the wiring metal 36 is attached to the mounting surface 10 of the heat sink 16 of the package with the mounting brazing material 7 such as AuSn bonded or pressure bonded.

In the semiconductor device 31 according to the second embodiment,
The mount conductor layer for connecting the source electrodes 2, 2 ′ and 2 ″, that is, the wiring metal 36 is not on the air bridge wiring, but on the dielectric layer 17 covering the element forming portions of the gate electrode 3 and the drain electrode 4. Since the wiring metal 36 is formed, it is possible to prevent the air bridge portion from being deformed by an external force applied when the semiconductor chip 30 is mounted.
Further, as compared with the first embodiment in which a part of the heat generating portion of the FET element is air, since the dielectric layer 17 exists in the heat generating portion of the FET element, the heat radiation effect is further improved.

FIG. 4 shows a third embodiment of the semiconductor device according to the present invention. (A) is a plan view of the semiconductor chip 30 mounted on the semiconductor device before wiring, and (b) is a semiconductor chip 30. FIG. 4 is a plan view after wiring.

In this embodiment, as shown in FIG. 4A, an FET element portion having source electrodes 2, 2 ', 2 ", a gate electrode 3 and a drain electrode 4 having the same structure as in the second embodiment is formed. 28, the matching circuit portions 21, 22 and the ground pattern portion 23 are formed on the GaAs substrate 1. Further, F
As a contact window other than the ET element portion 28, the gate pad 8 has a gate pad portion window 24, the drain pad 9 has a drain pad portion window 25, the matching circuit portions 21 and 22 have a matching circuit portion window 27, and the ground pattern portion 23 has a ground. Pattern window 2
6 is provided so that the package can be contacted. Further, as shown in FIG.
Source electrodes 2, 2 ',
2 ″, the matching circuit section window 27, and the ground pattern section window 26 are wired so as to be electrically connected. The semiconductor chip 30 thus configured is mounted with the wiring surface of the wiring metal 36 facing downward. The brazing material adheres or crimps to the mounting surface of the heat sink of the package.

Since the semiconductor device according to the third embodiment is constructed in this way, the input line 29 and the output line 30 have the ground pattern 2 when mounted in a package.
A coplanar type transmission line is formed between the two and 3.

In the method of bonding the grounding portion of the coplanar type circuit to the heat sink with the bonding wire, the grounding condition is deteriorated in the high frequency region due to the inductance component of the wire. Since the ground portion pattern portion 23 of the circuit using the line is wired by the wiring metal 36 and the wiring surface is joined to the mounting surface of the heat sink of the package, the inductive component can be drastically reduced and the grounding state becomes good, The operation of the circuit can be stabilized.

Although the GaAs substrate is used as the semiconductor substrate in the above embodiment, the semiconductor device according to the present invention can be implemented by using another semiconductor substrate such as a Si substrate.

Further, in the above embodiment, the source electrode of the FET element part is connected by the common wiring metal, but not the source electrode but the drain electrode, or both the source electrode and the drain electrode are connected by the common wiring metal. You may let me.

[0034]

As described above, the flip-chip type semiconductor device according to the present invention has a structure in which desired electrodes of the FET element portion formed on the semiconductor chip are connected by a common wiring metal. Even when the mounting surface of the substrate on which the chip is mounted or the package has low flatness, electrical contact to the mounting surface and a heat radiation path can be secured. As a result, the mounting surface of the substrate or package used for the semiconductor device according to the present invention does not need to have high-precision flatness, so that the production yield is improved, the reliability is improved, and the package surface is improved. It becomes possible to realize cost reduction.

[Brief description of drawings]

1A and 1B are views showing a first embodiment of a semiconductor device according to the present invention, FIG. 1A is a plan view of a semiconductor chip, and FIG. 1B is a semiconductor chip shown in FIG. 1A mounted on a heat sink of a package. 14A is a cross-sectional view of the semiconductor device taken along line XX ′ in FIG. 9A, FIG. 13C shows the semiconductor chip shown in FIG.
FIG. 3 is a cross-sectional view of the semiconductor device taken along line YY ′ in FIG.

2A is a plan view of a lead frame of a package for manufacturing the semiconductor device shown in FIG. 1, and FIG.
6 is a cross-sectional view of the semiconductor device according to the example of FIG.

3A and 3B are views showing a second embodiment of a semiconductor device according to the present invention, FIG. 3A is a plan view of a semiconductor chip, and FIG. 3B is a mounting surface of a heat sink of a package for the semiconductor chip shown in FIG. FIG. 3 is a cross-sectional view of the semiconductor device taken along the line XX ′ in (a) in the state of being mounted in FIG.

4A and 4B show a third embodiment of a semiconductor device according to the present invention, FIG. 4A is a plan view before wiring a semiconductor chip mounted on the semiconductor device, and FIG. 4B is a plan view after wiring the semiconductor chip. It is a top view.

FIG. 5 is a cross-sectional view of a conventional semiconductor device having a flip-chip type structure.

FIG. 6A is a sectional view showing a state in which a conventional semiconductor chip is mounted on a mount surface having low flatness accuracy;
FIG. 2 is a cross-sectional view showing a state where the semiconductor chip shown in FIG. 1 is mounted on a mount surface having low flatness accuracy.

[Explanation of symbols]

 1 Substrate 2, 2 ', 2 "Source Electrode 3 Gate Electrode 4 Drain Electrode 5, 36 Wiring Metal 6 Mounting Substrate 7 Mount Brazing Material 8 Gate Pad 9 Drain Pad 10 Mounting Surface 11, 12 External Lead Lead 16 Heat Sink 17 Dielectric Layer 18 Source Pad 19 Bonding Material 21, 22 Matching Circuit Section 23 Grounding Pattern Section 24 Gate Pad Section Window 25 Drain Pad Section Window 26 Grounding Pattern Section Window 27 Matching Circuit Section Window 28 FET Element Section 29 Input Line 39 Output Line

Claims (4)

[Claims] 1. A field effect transistor element portion is formed by arranging a plurality of source electrodes, gate electrodes, and drain electrodes on a semiconductor substrate, and at least two source electrodes or drain electrodes of the field effect transistor element portion are formed. It is characterized in that semiconductor chips connected to each other by air bridge wiring are mounted, and the air bridge wiring surface of the semiconductor chips is bonded or thermally pressure-bonded to a mount surface of a medium on which the semiconductor chips are mounted by a mount material. Semiconductor device. 2. A field effect transistor element section is formed by arranging a plurality of source electrodes, gate electrodes, and drain electrodes on a semiconductor substrate, and a dielectric layer is formed on the gate electrode and drain electrode of the field effect transistor element section. And a mounting conductor layer is formed on the dielectric layer and the source electrode, and the mounting conductor layer electrically mounts the source electrode on which a semiconductor chip is mounted, and the mounting of the semiconductor chip is performed. A semiconductor device, wherein the conductor layer is adhered or thermally pressure-bonded to a mount surface of a medium on which the semiconductor chip is mounted by a mount material. 3. A field effect transistor element section is formed by arranging a plurality of source electrodes, gate electrodes, and drain electrodes on a semiconductor substrate, and a dielectric layer is formed on the gate electrode of the field effect transistor element section. Further, a mounting conductor layer is formed on the dielectric layer and the source electrode and the drain electrode, and the mounting conductor layer is mounted on a semiconductor chip in which the source electrode and the drain electrode are electrically joined. A semiconductor device, wherein the mounting conductor layer of a chip is bonded or thermally pressure-bonded to a mount surface of a medium on which the semiconductor chip is mounted by a mount material. 4. A field effect transistor element part is formed by arranging a plurality of source electrodes, gate electrodes, and drain electrodes on a semiconductor substrate, and a dielectric layer is formed on the gate electrode and the source electrode of the field effect transistor element part. And a mount conductor layer is formed on the dielectric layer and the gate electrode, the mount conductor layer electrically mounts the gate electrode on the semiconductor chip, and the mount of the semiconductor chip is performed. A semiconductor device, wherein the conductor layer is adhered or thermally pressure-bonded to a mount surface of a medium on which the semiconductor chip is mounted by a mount material.