JP2004228402A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2004228402A
JP2004228402A JP2003015891A JP2003015891A JP2004228402A JP 2004228402 A JP2004228402 A JP 2004228402A JP 2003015891 A JP2003015891 A JP 2003015891A JP 2003015891 A JP2003015891 A JP 2003015891A JP 2004228402 A JP2004228402 A JP 2004228402A
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Prior art keywords
semiconductor device
inner lead
semiconductor
passive elements
passive
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JP2003015891A
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Japanese (ja)
Inventor
Hiroyuki Ishida
裕之 石田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2003015891A priority Critical patent/JP2004228402A/en
Publication of JP2004228402A publication Critical patent/JP2004228402A/en
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with two passive elements or more together with a semiconductor wherein a broken line and deterioration in the element performance or the like hardly take place and the manufacturing cost can be suppressed. <P>SOLUTION: The semiconductor device includes: a die pad; a semiconductor chip adhered to and mounted on the principal face of the die pad; a plurality of leads one-end sides of which configure inner leads and the other-end sides of which configure outer leads; a plurality of passing elements adhered to and mounted on the inner leads and electrically connected to the semiconductor chip; and a package for containing the die pad, the semiconductor chip, the inner leads and the passive elements. A plurality of the passive elements are integrally configured. Since a plurality of the passive elements are arranged without a gap by employing a multiple string chip, the passive elements are closely arranged on a small-sized lead frame. As a result, the passive elements are stably mounted in the vicinity of a frame fixed part of the inner leads, and the semiconductor device immune to a broken line is obtained. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子と複数の受動素子とを一体に備えた半導体装置に関し、特に、高電圧制御用半導体装置に関する。
【０００２】
【従来の技術】
現在、半導体素子や受動素子などの複数のチップを回路基板上に実装して樹脂等で封止したモジュール型半導体装置が、高出力に耐える小型半導体装置として知られており、さらに新たな試みとして、リードフレームを利用した樹脂封止型半導体装置が開発されている。
【０００３】
リードフレームを利用した樹脂封止型半導体装置としては、半導体集積回路チップと共に、ノイズキャンセラとしてコンデンサを備えた半導体装置が知られている。その構造の一例は、リードフレームのダイパッドの表面に半導体集積回路のチップと、裏面にコンデンサとを各々取り付けており、その後にモールドパッケージして成る（例えば、特許文献１参照。）。
【０００４】
【特許文献１】
特開昭６１−３５５４４号公報
【０００５】
【発明が解決しようとする課題】
半導体装置に求める多様な機能に対応するために、さらに多くの半導体素子や受動素子を備えた半導体装置が要求されているが、上記の樹脂封止型半導体装置では、３つ以上の素子を実装した半導体装置には対応できていない。
【０００６】
別のモジュール型半導体装置としては、ダイパッドに半導体素子を固定し、リードフレームのインナーリード上に受動素子チップを固定した半導体装置が考えられる。このような半導体装置では、必要とする受動素子が増えると受動素子チップの数も増加し、その実装位置は、インナーリードがフレームに固定された固定部近傍から、その自由端部まで、各所に亘るようになる。
【０００７】
しかし、リードフレームをプレス加工する場合には、インナーリードの自由端部は、他方の中央部分に比べて平坦度が低くなりやすく、該先端部にチップをハンダ等で固定すると、その後の製造工程においてハンダ固定部に機械的な応力がかかることがあり、その結果、ハンダ固定部が剥離して断線するといった故障を生じる惧れがある。これを回避するには、リードフレームを大きくする必要があり、装置が大型化する欠点がある。
リードフレームの製造にエッチング加工を用いることにより、インナーリードの平坦度は向上するが、大量生産には適さず、半導体装置の製造コストが高くなる。
【０００８】
また、半導体素子チップ及び受動素子チップを、ハンダダイボンドで実装する場合、１つづリードフレームに固定され、ハンダ固定時の熱は、既に実装されたチップに伝播するので、実装するチップ数が増加すると、先に固定されたチップは、複数回の熱を受けて熱ストレスが蓄積されて、素子の性能に悪影響を与えることがある。特に、この実装方式では、１つの実装部品に対し１台のダイボンド施設が必要であり、実装部品が増える毎に、その分の設備が必要になる為、膨大な施設導入費と設置スペースが必要である。
【０００９】
そこで、本発明は、半導体とともに２つ以上の受動素子を備えて樹脂パッケージされた半導体装置であって、断線や素子性能の低下などが発生し難く、また、製造コスト及び設備導入費を抑えることが可能な半導体装置を提供する。
【００１０】
【課題を解決するための手段】
本発明の半導体装置は、ダイパッド、該ダイパッドの主面に接着搭載された半導体チップ、一端側がインナーリード部を他端側がアウターリード部を構成する複数のリード、インナーリード部に接着搭載され半導体チップと電気的に接続される複数の受動素子、及びダイパッドと半導体チップとインナーリード部と受動素子とを収納するパッケージを備えた半導体装置において、前記複数の受動素子を一体に構成したことを特徴とする。
【００１１】
本発明において、一体に形成した受動素子とは、個々に機能する複数の受動素子を適当な方法により一体化したものであり、例えばチップ部品化した多連チップなどが含まれる。各受動素子には、２つの電極が形成されて、外部と接続可能にされている。
本発明の半導体装置は、一体化した受動素子を用いることにより、複数の受動素子を隙間なく配置できるので、従来であれば大きなリードフレーム上に各所に分散させて配置するしかなかった受動素子を、小型のリードフレーム上に密集配置することができる。その結果、チップをインナーリードのフレーム固定部近傍に安定して実装することができ、断線に対して強い半導体装置を形成することができる。
【００１２】
本発明の半導体装置は、一体化した受動素子を用いるので、インナーリード上に実装する回数が減らすことができて、熱ストレスによる受動素子の性能低下が抑制される。
【００１３】
【発明の実施の形態】
本発明の半導体素子は、ダイパッドと、該ダイパッドに搭載された半導体チップと、インナーリードとアウターリードとを備えた複数のリードと、インナーリードに搭載された複数の受動素子と、パッケージと、で構成される。
一体化した受動素子は、２以上の受動素子を並列に配置して一体に形成されているが、それぞれの受動素子の電極は分離しているので、半導体回路に組み込む場合には、それぞれが独立した受動素子として利用される。また、各受動素子の電極間を導電性部材により接続することにより、チップ内の受動素子を直列に接続することができる。
【００１４】
本発明の半導体素子では、一体化した受動素子の各々が、該受動素子のインナーリードとの対向面に一対の電極対を備えて、受動素子のインナーリードへの接続搭載によって電極対とインナーリードとを電気的に接続することができる。１つの受動素子には２つの電極があるので、例えば３つの受動素子を含んだ多連チップであれば、１つのチップに６つの電極が形成され、それら全ての電極が、ハンダ等の導電性接合材によってインナーリードに固定される。そのため、一体化した受動素子は、１つの受動素子を含む単一受動素子チップに比べて、強固で安定した固定が可能で、インナーリードからチップが剥離しにくい。
【００１５】
また、本発明の半導体装置では、一体化した受動素子の各々が、該受動素子のインナーリードとの対向面に一対の電極対の一方の電極を設け、受動素子の対向面の反対面に他方の電極対を設け、前記一方の電極が受動素子のインナーリードへの接続搭載によってインナーリードと電気的に接続し、前記他方の電極が可撓性導電部材による配線によってインナーリードと接続することができる。詳しくは、この一体化した受動素子では、各受動素子が備える一対の電極対が、対向する２つの面に各々分配されて形成されており、例えば３つの受動素子を含んだ多連チップでは、対向面および反対面の各々に、３つのづつ電極が形成される。この一体化した受動素子は、対向面に形成された電極がリードに通電可能に固定され、反対面に形成された電極が導電性部材によりインナーリードと導通されて、実装される。
【００１６】
本発明の半導体装置は、パッケージの内部に、さらに、１つ又は２つ以上の別体の受動素子がインナーリード部に接着搭載されて半導体素子と電気的に接続することができるので、選択可能な受動素子の種類が増加し、種々の半導体回路の作製に適用可能な半導体装置を得ることができる。また、本発明の半導体装置は、一体化した受動素子や別体の受動素子の数に制限はなく、半導体装置の寸法や所望の半導体回路に合わせてチップ数を増減できる。
【００１７】
他方の電極とインナーリードとを接続する導電性部材には、金属細線を用いることができて、従来のワイヤボンディングの技術を用いて短時間で接続作業を完了することができる。金属細線には、金線、アルミニウム線、銅線及び軟銅線などの金属細線が利用できる。また、導電性部材には、可撓性基板を用いることもでき、外部応力による切断が起こりにくく、故障の少ない半導体装置を提供することができる。
【００１８】
本発明の半導体装置は、半導体素子として、パワー素子と該パワー素子制御用の半導体素子とを含むことができ、このような半導体装置は、高電圧制御用のパワーデバイスとして利用される。パワー素子としては、ＰｗＴｒやＭＯＳＦＥＴ、特にＩＧＢＴや、サイリスタ、その他専用のパワー素子などを用いることができる。
【００１９】
これらの半導体素子は、所定のダイパッドにダイボンドされ、リードフレームのインナーリードに、ワイヤボンディングなどにより導通されて実装されている。半導体素子は、インナーリード上に実装された受動素子と協働して、所望の性能を有する半導体装置を構成する。
【００２０】
本発明の受動素子には、コンデンサ、抵抗、コイル等を用いることができる。また、受動素子の代わりにダイオードを用いることもできる。受動素子の一体化において、受動素子は、直線配置、屈曲配置、曲線配置などの線状配置や、マトリクス状配置のような平面配置とすることができる。
【００２１】
本発明で用いられるリードフレームは、銅薄板から、プレス加工やエッチング加工によって成形され、特に、大量生産でのコスト低下のために、プレス加工で成形されるのが好ましい。リードフレームのインナーリードは、半導体素子および受動素子の数および配線、チップ形状等に合わせて、パターン設計される。また、ボンディング強度を向上するために、インナーリードに部分的に金属メッキを施すことができる。
リードフレームのアウターリードは、半導体装置を取り付けるソケット及び電極の規格に適合してプレス加工および折り曲げ加工がされている。
【００２２】
本発明の半導体装置は、半導体素子、受動素子、及びインナーリードがパッケージに封止されており、アウターリードのみが露出して、半導体装置内部と外部とを電気的に接続可能としている。パッケージとしては、封止用の樹脂を用いることができ、特に、絶縁性、高周波特性、強度、接着強度、耐吸湿性、成型性に優れ、特に高温下でのそれらの特性が優れた樹脂が選択され、例えば、エポキシ樹脂が利用できる。
【００２３】
【実施例】
実施例１．
本発明の半導体装置により、パワーデバイスを作成した例を以下に示す。パワーデバイス９は、樹脂モールド前は、図１に示すように、リードフレーム２に半導体素子１、４と受動素子７０、７１、７２、８とが配置固定される。
リードフレーム２には、２つのダイパッド１０、４０と、インナーリード２１〜２８とが形成されており、それらはアウターリード２９等を介して、フレーム２０に固定されている。リードフレームは、銅薄板から成形されている。
【００２４】
パワー素子１は、ダイパッド１０にダイボンディングによりハンダで固定され、さらに、ワイヤボンディングにより、金線から成るワイヤー３でインナーリード２１、２８に接続されている。
パワー素子制御用素子４は、ダイパッド４０にダイボンディングによりハンダで固定され、さらに、ワイヤボンドにより、アルミニウム線から成るワイヤー５でインナーリード２２〜２８に接続されている。
【００２５】
多連チップ８は、この例では３連コンデンサチップであるが、インナーフレームとの対向面に３対の電極８０を備えており、インナーフレーム２５〜２８にハンダで固定されている。
１つのコンデンサを含む単一コンデンサチップ７０、７１、７２は、両側に電極７０ａ、７１ａ、７２ａを備えており、電極７０ａがインナーリード２１、２２に、電極７１ａがインナーリード２２、２３に、電極７２ａがインナーリード２３、２４に、ハンダで固定されている。
【００２６】
制御用素子４と、多連コンデンサチップ８及び単一コンデンサチップ７０、７１、７２に含まれる６つのコンデンサ素子とにより、パワー素子の制御用回路が構成されて、パワー素子が制御される。
半導体装置９は、エポキシ樹脂から成る封止樹脂６（破線）により封止され、その後、破線Ａ及びＢでフレーム２が切断されて完成する。
【００２７】
本実施例のパワーデバイス９は、単一コンデンサチップ７０、７１、７２も、３連コンデンサチップ８に置き換えることができる。
【００２８】
実施例２．
本発明の半導体装置により、パワーデバイスを作成する。図２のパワーデバイスは、図１と等価回路であり、リードフレーム２及び半導体素子１、４は、実施例と同様である。
【００２９】
多連チップ８は、この例では３連コンデンサチップであるが、インナーフレームとの対向面に形成される第一の電極（図示せず）を、また対向面の背面に位置する反対面に第二の電極８１を、各々３つづつ備えている。第一の電極は、インナーフレーム２５〜２７にハンダで固定され、第二の電極８１は、ワイヤ８２でインナーフレーム２６〜２８と接続されている。
【００３０】
１つのコンデンサを含む単一コンデンサチップ７０、７１、７２は、第一の電極（図示せず）と第二の電極７０ｂ、７１ｂ、７２ｂを備えており、コンデンサ７０、７１の第一の電極がインナーリード２２に、コンデンサ７２の第一の電極がインナーリード２４に、ハンダで固定されている。第二の電極７０ｂ、７１ｂ、７２ｂは、金属細線８２でインナーフレーム２１、２３、２３とそれぞれ接続されている。
【００３１】
金属細線８２は、金線から成り、ワイヤボンディングにより第二の電極およびインナーリードと接続している。第二の電極８１、７０ｂ、７１ｂ、７２ｂには、ワイヤの接着固定を良好にするために、金の薄膜などが形成されている。
半導体装置９は、エポキシ樹脂から成る封止樹脂６（破線）により封止され、その後、破線Ａ及びＢでフレーム２が切断されて完成する。
本実施例のパワーデバイス９は、金属細線８２を、アルミニウムや銅のワイヤボンド及び軟銅線のハンダ付けに置きかえることができる。
【００３２】
本実施例の半導体装置９の変形例としては、図３に示すように、ワイヤ８２の代わりに、フレキシブル基板８３を用いることができる。フレキシブル基板８３は、細幅の帯状金属片を絶縁性樹脂膜で挟んで形成されており、電極およびインナーリードと接続する部分は、樹脂膜が剥離されて金属片が露出される。図２に示すように、フレキシブル基板８３は、単一コンデンサ７０とインナーリード２１とを接続するように、１本の金属片を樹脂膜で挟んだ形状で用いることができるが、多連チップ８とリード２６〜２８を接続するように、３本の金属片を樹脂膜で一体にした３連フレキシブル基板８３を用いることもできる。
【００３３】
本実施例のパワーデバイス９は、単一コンデンサチップ７０、７１、７２を、図１又は図２に示すような３連コンデンサチップに置き換えることができる。
【００３４】
【発明の効果】
本発明の半導体装置では、受動素子を一体化することにより、小型のリードフレーム上に受動素子を密集配置することができるので、受動素子をインナーリードのフレーム固定部近傍に安定して実装できて、断線しにくく信頼性の高い半導体装置を提供することができる。また、本発明の半導体装置は、ダイボンディングの回数を減らして受動素子にかかる熱ストレスを低減することができるので、受動素子の性能低下を抑制して、性能のよい半導体装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の実施例に係る半導体装置の樹脂被覆前の上面図である。
【図２】本発明の実施例に係る半導体装置の変形例の樹脂被覆前の上面図である。
【図３】本発明の実施例に係る半導体装置の変形例の樹脂被覆前の上面図である。
【符号の説明】
１ 半導体素子（パワー素子）、１０ ダイパッド（パワー素子）、
２ リードフレーム、２０ フレーム、２１〜２８ インナーリード、
２９ アウターリード、４ 半導体素子（パワー素子制御用素子）、
４０ ダイパッド（パワー素子制御用素子）、６ 封止樹脂、
７０、７１、７２ 受動素子（単一受動素子チップ）、
８ 受動素子（多連チップ）、８２ 金属細線、８３ フレキシブル基板、
９ 半導体装置。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device integrally including a semiconductor element and a plurality of passive elements, and more particularly to a semiconductor device for high voltage control.
[0002]
[Prior art]
Currently, a module type semiconductor device in which multiple chips such as semiconductor elements and passive elements are mounted on a circuit board and sealed with resin or the like is known as a small semiconductor device that can withstand high output. A resin-encapsulated semiconductor device using a lead frame has been developed.
[0003]
As a resin-encapsulated semiconductor device using a lead frame, a semiconductor device including a capacitor as a noise canceller is known along with a semiconductor integrated circuit chip. As an example of the structure, a chip of a semiconductor integrated circuit and a capacitor are attached to the surface of a die pad of a lead frame and a back surface, respectively, and then molded and packaged (see, for example, Patent Document 1).
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 61-35544
[Problems to be solved by the invention]
In order to cope with various functions required for semiconductor devices, semiconductor devices having more semiconductor elements and passive elements are required. However, in the above-described resin-encapsulated semiconductor devices, three or more elements are mounted. It is not compatible with the semiconductor device.
[0006]
As another module type semiconductor device, a semiconductor device in which a semiconductor element is fixed to a die pad and a passive element chip is fixed on an inner lead of a lead frame is conceivable. In such a semiconductor device, as the number of required passive elements increases, the number of passive element chips also increases, and the mounting positions thereof vary from the vicinity of the fixed portion where the inner lead is fixed to the frame to the free end thereof. It comes across.
[0007]
However, when pressing the lead frame, the free end portion of the inner lead tends to have a lower flatness than the other central portion, and if the chip is fixed to the tip portion with solder or the like, the subsequent manufacturing process In this case, mechanical stress may be applied to the solder fixing portion, and as a result, there is a possibility that the solder fixing portion may be broken and disconnected. In order to avoid this, it is necessary to enlarge the lead frame, and there is a disadvantage that the apparatus becomes larger.
By using an etching process for manufacturing the lead frame, the flatness of the inner lead is improved, but it is not suitable for mass production, and the manufacturing cost of the semiconductor device increases.
[0008]
Also, when mounting semiconductor element chips and passive element chips by solder die bonding, they are fixed to the lead frame one by one, and the heat at the time of solder fixation propagates to the already mounted chips, so the number of chips to be mounted increases The previously fixed chip may be subjected to heat a plurality of times and heat stress is accumulated, which may adversely affect the performance of the device. In particular, with this mounting method, one die bond facility is required for each mounted component, and as the number of mounted components increases, that amount of equipment is required, so huge facility installation costs and installation space are required. It is.
[0009]
Therefore, the present invention is a semiconductor device that is packaged with a semiconductor including two or more passive elements together with a semiconductor, and is less likely to cause disconnection or degradation of element performance, and suppresses manufacturing costs and equipment introduction costs. Provided is a semiconductor device capable of
[0010]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes a die pad, a semiconductor chip bonded and mounted on the main surface of the die pad, a plurality of leads forming one end side of the inner lead portion and the other end side forming an outer lead portion, and a semiconductor chip mounted on the inner lead portion. A plurality of passive elements electrically connected to the semiconductor device, and a semiconductor device including a package that accommodates a die pad, a semiconductor chip, an inner lead portion, and a passive element, wherein the plurality of passive elements are configured integrally. To do.
[0011]
In the present invention, the integrally formed passive elements are obtained by integrating a plurality of individually functioning passive elements by an appropriate method, and include, for example, multiple chips formed as chip parts. Each passive element is formed with two electrodes so that it can be connected to the outside.
In the semiconductor device of the present invention, since a plurality of passive elements can be arranged without gaps by using an integrated passive element, conventionally passive elements that had to be dispersed and arranged on a large lead frame in various places. It can be densely arranged on a small lead frame. As a result, the chip can be stably mounted in the vicinity of the frame fixing portion of the inner lead, and a semiconductor device that is strong against disconnection can be formed.
[0012]
Since the semiconductor device of the present invention uses an integrated passive element, the number of times of mounting on the inner lead can be reduced, and the performance degradation of the passive element due to thermal stress is suppressed.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor element of the present invention includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads including inner leads and outer leads, a plurality of passive elements mounted on the inner leads, and a package. Composed.
The integrated passive element is formed integrally by arranging two or more passive elements in parallel, but the electrodes of each passive element are separated, so each is independent when incorporated in a semiconductor circuit. Used as a passive element. Further, the passive elements in the chip can be connected in series by connecting the electrodes of each passive element with a conductive member.
[0014]
In the semiconductor element of the present invention, each of the integrated passive elements includes a pair of electrode pairs on the surface facing the inner lead of the passive element, and the electrode pair and the inner lead are connected and mounted on the inner lead of the passive element. Can be electrically connected. Since one passive element has two electrodes, for example, in a multiple chip including three passive elements, six electrodes are formed on one chip, and all of these electrodes are made of conductive materials such as solder. It is fixed to the inner lead by a bonding material. Therefore, the integrated passive element can be firmly and stably fixed as compared with a single passive element chip including one passive element, and the chip does not easily peel from the inner lead.
[0015]
In the semiconductor device of the present invention, each of the integrated passive elements is provided with one electrode of a pair of electrode pairs on the surface facing the inner lead of the passive element, and the other surface on the surface opposite to the surface facing the passive element. The electrode is electrically connected to the inner lead by connecting and mounting the passive element to the inner lead, and the other electrode is connected to the inner lead by wiring with a flexible conductive member. it can. Specifically, in this integrated passive element, a pair of electrodes provided in each passive element is formed by being distributed to two opposing surfaces, for example, in a multiple chip including three passive elements, Three electrodes are formed on each of the opposing surface and the opposite surface. The integrated passive element is mounted such that the electrode formed on the opposing surface is fixed to the lead so as to be energized, and the electrode formed on the opposite surface is electrically connected to the inner lead by the conductive member.
[0016]
The semiconductor device of the present invention is selectable because one or more separate passive elements can be bonded and mounted on the inner lead portion inside the package and electrically connected to the semiconductor element. As the number of passive elements increases, a semiconductor device applicable to manufacture of various semiconductor circuits can be obtained. In the semiconductor device of the present invention, the number of integrated passive elements or separate passive elements is not limited, and the number of chips can be increased or decreased in accordance with the dimensions of the semiconductor device and a desired semiconductor circuit.
[0017]
A thin metal wire can be used as the conductive member that connects the other electrode and the inner lead, and the connection work can be completed in a short time using a conventional wire bonding technique. As the fine metal wire, a fine metal wire such as a gold wire, an aluminum wire, a copper wire and an annealed copper wire can be used. In addition, a flexible substrate can be used as the conductive member, so that a semiconductor device that is less likely to be cut by external stress and has few failures can be provided.
[0018]
The semiconductor device of the present invention can include a power element and a semiconductor element for controlling the power element as semiconductor elements, and such a semiconductor device is used as a power device for high voltage control. As the power element, PwTr and MOSFET, in particular, IGBT, thyristor, and other dedicated power elements can be used.
[0019]
These semiconductor elements are die-bonded to a predetermined die pad, and are electrically connected to the inner leads of the lead frame by wire bonding or the like. The semiconductor element forms a semiconductor device having desired performance in cooperation with the passive element mounted on the inner lead.
[0020]
A capacitor, resistor, coil, or the like can be used for the passive element of the present invention. A diode can also be used instead of a passive element. In the integration of the passive elements, the passive elements can be in a linear arrangement such as a linear arrangement, a bent arrangement or a curved arrangement, or in a planar arrangement such as a matrix arrangement.
[0021]
The lead frame used in the present invention is molded from a copper thin plate by pressing or etching, and is particularly preferably molded by pressing for cost reduction in mass production. The inner lead of the lead frame is designed in a pattern according to the number of semiconductor elements and passive elements, wiring, chip shape, and the like. Further, in order to improve the bonding strength, the inner lead can be partially subjected to metal plating.
The outer lead of the lead frame is pressed and bent in conformity with the standard of the socket and electrode for mounting the semiconductor device.
[0022]
In the semiconductor device of the present invention, the semiconductor element, the passive element, and the inner lead are sealed in the package, and only the outer lead is exposed so that the inside and outside of the semiconductor device can be electrically connected. As the package, a sealing resin can be used, and in particular, a resin excellent in insulation, high frequency characteristics, strength, adhesive strength, moisture absorption resistance, moldability, and particularly excellent in those characteristics at high temperatures. For example, an epoxy resin can be used.
[0023]
【Example】
Example 1.
An example in which a power device is created using the semiconductor device of the present invention is shown below. In the power device 9, the semiconductor elements 1, 4 and the passive elements 70, 71, 72, 8 are arranged and fixed to the lead frame 2 before resin molding, as shown in FIG. 1.
Two die pads 10 and 40 and inner leads 21 to 28 are formed on the lead frame 2, and these are fixed to the frame 20 via outer leads 29 and the like. The lead frame is formed from a copper thin plate.
[0024]
The power element 1 is fixed to the die pad 10 by soldering by die bonding, and is further connected to the inner leads 21 and 28 by wires 3 made of gold wires by wire bonding.
The power element control element 4 is fixed to the die pad 40 by soldering by die bonding, and is further connected to the inner leads 22 to 28 by wires 5 made of aluminum wires by wire bonding.
[0025]
The multiple chip 8 is a triple capacitor chip in this example, but is provided with three pairs of electrodes 80 on the surface facing the inner frame, and is fixed to the inner frames 25 to 28 with solder.
Single capacitor chips 70, 71, 72 including one capacitor have electrodes 70a, 71a, 72a on both sides, the electrode 70a being the inner leads 21, 22, the electrode 71a being the inner leads 22, 23, the electrodes 72a is fixed to the inner leads 23, 24 with solder.
[0026]
The control element 4 and the six capacitor elements included in the multiple capacitor chip 8 and the single capacitor chips 70, 71, 72 constitute a power element control circuit to control the power element.
The semiconductor device 9 is sealed with a sealing resin 6 (broken line) made of an epoxy resin, and then the frame 2 is cut along the broken lines A and B to complete.
[0027]
In the power device 9 of the present embodiment, the single capacitor chips 70, 71, 72 can also be replaced with the triple capacitor chip 8.
[0028]
Example 2
A power device is produced by the semiconductor device of the present invention. The power device in FIG. 2 is an equivalent circuit to that in FIG. 1, and the lead frame 2 and the semiconductor elements 1 and 4 are the same as those in the embodiment.
[0029]
In this example, the multiple chip 8 is a triple capacitor chip, but the first electrode (not shown) formed on the surface facing the inner frame is provided on the opposite surface located on the back surface of the facing surface. Three each of the two electrodes 81 are provided. The first electrode is fixed to the inner frames 25 to 27 with solder, and the second electrode 81 is connected to the inner frames 26 to 28 with wires 82.
[0030]
A single capacitor chip 70, 71, 72 including one capacitor includes a first electrode (not shown) and second electrodes 70b, 71b, 72b, and the first electrodes of the capacitors 70, 71 are The first electrode of the capacitor 72 is fixed to the inner lead 22 by soldering to the inner lead 24. The second electrodes 70b, 71b, 72b are connected to the inner frames 21, 23, 23 by thin metal wires 82, respectively.
[0031]
The fine metal wire 82 is made of a gold wire, and is connected to the second electrode and the inner lead by wire bonding. The second electrodes 81, 70b, 71b, 72b are formed with a gold thin film or the like in order to improve the bonding and fixing of the wires.
The semiconductor device 9 is sealed with a sealing resin 6 (broken line) made of an epoxy resin, and then the frame 2 is cut along the broken lines A and B to complete.
In the power device 9 of the present embodiment, the thin metal wire 82 can be replaced with aluminum or copper wire bonding and annealed copper wire soldering.
[0032]
As a modification of the semiconductor device 9 of the present embodiment, a flexible substrate 83 can be used instead of the wire 82 as shown in FIG. The flexible substrate 83 is formed by sandwiching a narrow strip-shaped metal piece with an insulating resin film, and the resin film is peeled off at a portion connected to the electrode and the inner lead to expose the metal piece. As shown in FIG. 2, the flexible substrate 83 can be used in a shape in which one metal piece is sandwiched between resin films so that the single capacitor 70 and the inner lead 21 are connected. A triple flexible substrate 83 in which three metal pieces are integrated with a resin film so as to connect the leads 26 to 28 can also be used.
[0033]
In the power device 9 of this embodiment, the single capacitor chip 70, 71, 72 can be replaced with a triple capacitor chip as shown in FIG. 1 or FIG.
[0034]
【The invention's effect】
In the semiconductor device of the present invention, the passive elements can be densely arranged on a small lead frame by integrating the passive elements, so that the passive elements can be stably mounted near the frame fixing portion of the inner lead. Therefore, a highly reliable semiconductor device that is hard to be disconnected can be provided. In addition, since the semiconductor device of the present invention can reduce the thermal stress applied to the passive element by reducing the number of die bondings, it is possible to provide a semiconductor device with good performance by suppressing the performance degradation of the passive element. it can.
[Brief description of the drawings]
FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention before resin coating.
FIG. 2 is a top view of the modified example of the semiconductor device according to the embodiment of the present invention before resin coating.
FIG. 3 is a top view of the modified example of the semiconductor device according to the embodiment of the present invention before resin coating.
[Explanation of symbols]
1 semiconductor element (power element), 10 die pad (power element),
2 lead frames, 20 frames, 21-28 inner leads,
29 outer leads, 4 semiconductor elements (power element control elements),
40 die pad (power element control element), 6 sealing resin,
70, 71, 72 passive element (single passive element chip),
8 passive elements (multiple chips), 82 fine metal wires, 83 flexible substrates,
9 Semiconductor device.

Claims (4)

ダイパッド、該ダイパッドの主面に接着搭載された半導体チップ、一端側がインナーリード部を他端側がアウターリード部を構成する複数のリード、インナーリード部に接着搭載され半導体チップと電気的に接続される複数の受動素子、及びダイパッドと半導体チップとインナーリード部と受動素子とを収納するパッケージを備えた半導体装置において、
前記複数の受動素子を一体に構成したことを特徴とする半導体装置。A die pad, a semiconductor chip bonded and mounted on the main surface of the die pad, an inner lead portion on one end side, a plurality of leads constituting the outer lead portion on the other end side, and an adhesive lead mounted on the inner lead portion and electrically connected to the semiconductor chip In a semiconductor device including a plurality of passive elements, and a package that houses a die pad, a semiconductor chip, an inner lead portion, and a passive element,
A semiconductor device comprising the plurality of passive elements integrally formed. 受動素子のインナーリード部との対向面に一対の電極対を設け、受動素子のインナーリード部への接続搭載によって電極対とインナーリード部とを電気的に接続したことを特徴とする請求項１に記載の半導体装置。2. The electrode pair and the inner lead part are electrically connected by providing a pair of electrode pairs on a surface facing the inner lead part of the passive element and connecting the passive element to the inner lead part. A semiconductor device according to 1. ダイパッド、該ダイパッドの主面に接着搭載された半導体チップ、一端側がインナーリード部を他端側がアウターリード部を構成する複数のリード、インナーリード部に接着搭載され半導体チップと電気的に接続される複数の受動素子、及びダイパッドと半導体チップとインナーリード部と受動素子とを収納するパッケージを備えた半導体装置において、
前記複数の受動素子を一体に構成すると共に、受動素子のインナーリード部との対向面に一対の電極対の一方の電極を設け、受動素子の対向面の反対面に他方の電極対を設け、前記一方の電極が受動素子のインナーリード部への接続搭載によってインナーリード部と電気的に接続し、前記他方の電極が可撓性導電部材による配線によってインナーリード部と接続したことを特徴とする半導体装置。A die pad, a semiconductor chip bonded and mounted on the main surface of the die pad, an inner lead portion on one end side, a plurality of leads constituting the outer lead portion on the other end side, and an adhesive lead mounted on the inner lead portion and electrically connected to the semiconductor chip In a semiconductor device including a plurality of passive elements, and a package that houses a die pad, a semiconductor chip, an inner lead portion, and a passive element,
The plurality of passive elements are integrally configured, one electrode of a pair of electrode pairs is provided on the surface facing the inner lead portion of the passive element, and the other electrode pair is provided on the opposite surface of the passive element. The one electrode is electrically connected to the inner lead portion by connecting and mounting the passive element to the inner lead portion, and the other electrode is connected to the inner lead portion by wiring with a flexible conductive member. Semiconductor device. パッケージの内部に、さらに、１つ又は２つ以上の別体の受動素子がインナーリード部に接着搭載されて半導体素子と電気的に接続されていることを特徴とする請求項１ないし３のいずれかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein one or more separate passive elements are further bonded and mounted on the inner lead portion and electrically connected to the semiconductor element inside the package. A semiconductor device according to claim 1.
JP2003015891A 2003-01-24 2003-01-24 Semiconductor device Pending JP2004228402A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008545280A (en) * 2005-07-01 2008-12-11 オウヤング，キング Complete power management system mounted in a single surface mount package
JP2010135737A (en) * 2008-10-30 2010-06-17 Denso Corp Semiconductor device
JP2012009904A (en) * 2008-10-30 2012-01-12 Denso Corp Semiconductor device
US8928157B2 (en) 2000-06-09 2015-01-06 Vishay-Siliconix Encapsulation techniques for leadless semiconductor packages

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8928157B2 (en) 2000-06-09 2015-01-06 Vishay-Siliconix Encapsulation techniques for leadless semiconductor packages
JP2008545280A (en) * 2005-07-01 2008-12-11 オウヤング，キング Complete power management system mounted in a single surface mount package
US8471381B2 (en) 2005-07-01 2013-06-25 Vishay-Siliconix Complete power management system implemented in a single surface mount package
CN104183591A (en) * 2005-07-01 2014-12-03 维税-希力康克斯公司 Complete power management system implemented in a single surface mount package
US8928138B2 (en) 2005-07-01 2015-01-06 Vishay-Siliconix Complete power management system implemented in a single surface mount package
US9093359B2 (en) 2005-07-01 2015-07-28 Vishay-Siliconix Complete power management system implemented in a single surface mount package
JP2010135737A (en) * 2008-10-30 2010-06-17 Denso Corp Semiconductor device
JP2012009904A (en) * 2008-10-30 2012-01-12 Denso Corp Semiconductor device

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