JPH098037A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH098037A JPH098037A JP14922195A JP14922195A JPH098037A JP H098037 A JPH098037 A JP H098037A JP 14922195 A JP14922195 A JP 14922195A JP 14922195 A JP14922195 A JP 14922195A JP H098037 A JPH098037 A JP H098037A
- Authority
- JP
- Japan
- Prior art keywords
- film
- recessed part
- board
- projecting part
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にランプ加熱を用い凹凸を有する基板上に平坦
な絶縁膜や多結晶シリコン膜を形成する半導体装置の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a flat insulating film or a polycrystalline silicon film is formed on a substrate having unevenness by using lamp heating.
【0002】[0002]
【従来の技術】LSIの集積度が増すにつれ、配線を多
層に積層する必要が生じているが、各配線の段差部での
断線を防ぐために、層間絶縁膜を平坦化する技術が必要
となっている。2. Description of the Related Art As the degree of integration of LSI has increased, it has become necessary to stack wiring in multiple layers. However, in order to prevent disconnection at the step portion of each wiring, a technique for flattening an interlayer insulating film is required. ing.
【0003】従来、層間絶縁膜を平坦化する方法として
は、リンガラス(リンドープ酸化シリコン膜)を低温で
堆積させ、その後の高温熱処理による粘性流動を利用し
て基板表面を滑らかにする、いわゆるリフロー法や、図
5に示すように、凹凸のある層間絶縁膜を平坦に研磨す
る、いわゆるCMP(Chemical Mechan
ical Polishing)法が用いられている。Conventionally, as a method of flattening an interlayer insulating film, so-called reflow is performed in which phosphorous glass (phosphorus-doped silicon oxide film) is deposited at a low temperature and the substrate surface is smoothed by utilizing viscous flow due to subsequent high temperature heat treatment. Or a so-called CMP (Chemical Mechanical) method for flatly polishing an uneven interlayer insulating film as shown in FIG.
The chemical polishing method is used.
【0004】CMP法を用いた層間絶縁膜の平坦化法で
は、まず図5(a)に示すように、酸化シリコン膜2の
形成されたシリコン基板1上に容量の下部電極としての
第1の多結晶シリコン膜3と容量絶縁膜4及び上部電極
としての第2の多結晶シリコン膜5を形成する。次に図
5(b)に示すように、このような凹凸を有する基板上
に凹凸の段差以上の膜厚を有する酸化シリコン膜6Aを
堆積させ、その後、図5(c)に示すように、CMP法
で酸化シリコン膜6Aを平坦に研磨する。In the planarization method of the interlayer insulating film using the CMP method, first, as shown in FIG. 5A, a first electrode as a lower electrode of a capacitor is formed on a silicon substrate 1 on which a silicon oxide film 2 is formed. A polycrystalline silicon film 3, a capacitive insulating film 4, and a second polycrystalline silicon film 5 as an upper electrode are formed. Next, as shown in FIG. 5B, a silicon oxide film 6A having a film thickness equal to or larger than the step of the unevenness is deposited on the substrate having such unevenness, and thereafter, as shown in FIG. The silicon oxide film 6A is polished flat by the CMP method.
【0005】これに対し、特開平1−91441号公報
では、熱源としてレーザー光を使い、基板の凹部のみに
レーザー光が入射するようにパターンの描かれたマスク
を用い、CVD法によりまず基板の凹部のみに選択的に
薄膜を堆積させ、次でランプ光CVDにより基板全面に
薄膜を堆積させ、これにより平坦化を行う方法を用いて
いる。On the other hand, in Japanese Unexamined Patent Publication No. 1-91441, laser light is used as a heat source and a mask is used in which a pattern is drawn so that the laser light is incident only on the concave portion of the substrate. A method is used in which a thin film is selectively deposited only on the concave portion, and then a thin film is deposited on the entire surface of the substrate by lamp light CVD, thereby performing planarization.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上述の
従来技術では、それぞれ次のような問題があった。ま
ず、リンガラスを用いたリフロー法では、リフロー温度
として800℃程度の高温を必要とする。設計ルールが
サブミクロン以下であるような半導体デバイスでは、電
界効果トランジスタの短チャネル効果を抑制するため
に、ソースやドレインなどの接合深さを極めて浅くする
必要があるが、ドーパント原子(例えばリン、砒素、ボ
ロン)の熱拡散が生じてしまうような高温のリフロー処
理を行うと、この短チャネル効果を抑制することができ
なくなるという問題があった。さらに、層間絶縁膜の堆
積工程とリフロー工程のふたつの工程が必要であるた
め、製造コストが増大してしまうという問題があった。However, the above-mentioned conventional techniques have the following problems, respectively. First, the reflow method using phosphor glass requires a high temperature of about 800 ° C. as a reflow temperature. In a semiconductor device whose design rule is submicron or less, it is necessary to make the junction depth of the source and drain extremely shallow in order to suppress the short channel effect of the field effect transistor. When the high temperature reflow process that causes the thermal diffusion of arsenic and boron) occurs, there is a problem that it is impossible to suppress the short channel effect. Further, there is a problem in that the manufacturing cost increases because two steps, that is, the step of depositing the interlayer insulating film and the reflow step are required.
【0007】また、CMP法では、研磨工程が室温で可
能なため、上述のリフロー工程で問題となるようなドー
パントの熱拡散の問題はないものの、研磨工程で生じう
る基板損傷やゴミの発生などの問題があった。また、層
間絶縁膜の堆積工程と研磨工程のふたつの工程からなる
ため、上述のリフロー工程と同様、製造コストが増大し
てしまう問題があった。Further, in the CMP method, since the polishing step can be performed at room temperature, there is no problem of thermal diffusion of the dopant which is a problem in the above-mentioned reflow step, but substrate damage or dust generation which may occur in the polishing step. There was a problem. Further, since it includes two steps, that is, the step of depositing the interlayer insulating film and the step of polishing, there is a problem that the manufacturing cost is increased like the reflow step described above.
【0008】また、レーザー光を用いる特開平1−91
441号の方法では、基板凹部のみにレーザー光が照射
できるようにパターンの描かれたマスクを用いるため、
ステッパーなどの露光装置と同等の高精度な技術が必要
となる。また、シリコン基板一枚毎にレーザー光を掃引
するため、単位時間当たりの処理枚数が極めて少なくな
る。これらのことは、製造コストの増大という問題を生
じさせる。Further, Japanese Patent Laid-Open No. 1-91 which uses laser light.
In the method of No. 441, since a mask in which a pattern is drawn so that laser light can be irradiated only on the concave portion of the substrate,
High-precision technology equivalent to that of exposure equipment such as steppers is required. Further, since the laser beam is swept for each silicon substrate, the number of processed wafers per unit time becomes extremely small. These give rise to the problem of increased manufacturing costs.
【0009】本発明は上記問題に鑑みて、これらの問題
を解決し製造コストの低減された半導体装置の製造方法
を提供することを目的とする。In view of the above problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device which solves these problems and has a reduced manufacturing cost.
【0010】[0010]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、凸部及び凹部の形成された半導体基板上に所
定波長のランプ光を照射し、凸部に比べ凹部の基板温度
を高くしながらCVD法により、凸部に比べ凹部に比較
的厚い膜を形成することを特徴とするものである。According to a method of manufacturing a semiconductor device of the present invention, lamp light having a predetermined wavelength is irradiated onto a semiconductor substrate having a convex portion and a concave portion so that the substrate temperature of the concave portion is higher than that of the convex portion. However, it is characterized in that a relatively thick film is formed in the concave portion as compared with the convex portion by the CVD method.
【0011】[0011]
【実施例】次に、本発明の実施例について、図面を参照
して説明する。図1(a),(b)は本発明の一実施例
を説明する為の半導体チップの断面図である。Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B are sectional views of a semiconductor chip for explaining an embodiment of the present invention.
【0012】まず図1(a)に示すように、シリコン基
板1上に膜厚200nmの酸化シリコン膜2と容量の下
部電極となるパターニングされた膜厚600nmの第1
の多結晶シリコン膜3とこの第1の多結晶シリコン膜3
を覆うように厚さ5〜10nmの容量絶縁膜4及び上部
電極としての厚さ200nmの第2の多結晶シリコン膜
5を形成する。この場合、シリコン基板上の凹部Bと凸
部Aの間の段差は600nmである。また、本発明にお
いては、パターンの寸法、パターン間の寸法に制限はな
い。First, as shown in FIG. 1A, a silicon oxide film 2 having a film thickness of 200 nm and a patterned first film having a film thickness of 600 nm to be a lower electrode of a capacitor are formed on a silicon substrate 1.
Polycrystalline silicon film 3 and this first polycrystalline silicon film 3
Then, a capacitive insulating film 4 having a thickness of 5 to 10 nm and a second polycrystalline silicon film 5 having a thickness of 200 nm as an upper electrode are formed so as to cover the. In this case, the step between the concave portion B and the convex portion A on the silicon substrate is 600 nm. Further, in the present invention, there is no limitation on the dimension of the pattern and the dimension between the patterns.
【0013】このような凹凸を有する半導体基板上に、
ランプ加熱により層間絶縁膜となる酸化シリコン膜を、
例えばシランガスと亜酸化窒素ガスを原料ガスとして減
圧化学気相成長させるが、このとき、ランプ光の最大強
度波長を1.2μmとなるように設定し、シリコン基板
上1の凹部Bを凸部Aよりも高温になるように加熱し、
凹部Bに膜厚約1000nmの酸化シリコン膜6を堆積
させ、凸部Aに膜厚約400nmの酸化シリコン膜6を
堆積させることにより、図1(b)に示すように、シリ
コン基板上を平坦化する。On a semiconductor substrate having such irregularities,
The silicon oxide film that becomes the interlayer insulating film by heating the lamp,
For example, low pressure chemical vapor deposition is performed using silane gas and nitrous oxide gas as source gases. At this time, the maximum intensity wavelength of the lamp light is set to 1.2 μm, and the concave portion B on the silicon substrate 1 is formed into the convex portion A. Heat to a higher temperature than
By depositing a silicon oxide film 6 having a film thickness of about 1000 nm on the concave portion B and depositing a silicon oxide film 6 having a film thickness of about 400 nm on the convex portion A, as shown in FIG. Turn into.
【0014】このような平坦化をなし得る成膜原理につ
いて、図2を用いて説明する。ランプ光で半導体基板を
加熱した場合、基板温度は基板表面の反射率に依存し、
特にランプ光が最大強度となる波長での反射率に大きく
依存することになる。半導体基板にパターンが描かれて
いる場合、パターン内外で反射率が異なり、反射率の大
きい領域では光の吸収量が小さいために加熱されにく
く、逆に、反射率の小さい領域では、光の吸収量が大き
いために加熱されやすくなる。また、反射率は波長と膜
厚/膜構成により大きく変化するため、半導体基板上の
凹部での反射率が小さくなり、かつ凸部での反射率が大
きくなるような波長を選定することが可能である。した
がって、上述のような波長で光強度が最大となるように
ランプ光を設定し、凹凸を有する半導体基板を加熱する
ことにより、基板温度が、凹部で比較的高く、凸部で比
較的低くすることが可能となる。The principle of film formation capable of achieving such flattening will be described with reference to FIG. When the semiconductor substrate is heated by lamp light, the substrate temperature depends on the reflectance of the substrate surface,
In particular, the lamp light largely depends on the reflectance at the wavelength where the intensity is maximum. When a pattern is drawn on the semiconductor substrate, the reflectance is different inside and outside the pattern, and it is difficult to heat because the absorption amount of light is small in the area with high reflectance, and conversely, the absorption of light in the area with low reflectance Due to the large amount, it is easily heated. In addition, since the reflectivity greatly changes depending on the wavelength and the film thickness / film structure, it is possible to select a wavelength such that the reflectivity at the concave portion on the semiconductor substrate becomes small and the reflectivity at the convex portion becomes large. Is. Therefore, by setting the lamp light so as to maximize the light intensity at the wavelength as described above and heating the semiconductor substrate having irregularities, the substrate temperature is made relatively high at the concave portions and relatively low at the convex portions. It becomes possible.
【0015】図2は図1(a)に示したシリコン基板の
凸部Aと凹部Bにおける光の反射率の波長依存性を求め
た結果を示している。波長約1.15〜1.3μmまで
の波長領域では、凸部Aの反射率は、凹部Bの反射率に
比べ大きい。そして、このような凸部Aと凹部B上に酸
化シリコン膜が約1000nmの厚さに堆積しても、反
射率の変化は小さく、凸部Aと凹部Bの反射率の大小関
係が逆転しないことがわかる。したがって、約1.2μ
mの波長が最大強度となるようなランプ光でシリコン基
板を加熱することにより、、凹部Bの温度を凸部Aの温
度よりも高温になるような状態を維持しながら、酸化シ
リコン膜6を堆積することができる。減圧化学気相成長
による成膜速度は成長温度に大きく依存するため、凸部
Aに比較的薄い酸化シリコン膜を、凹部Bに比較的厚い
酸化シリコン膜を堆積させることが可能である。FIG. 2 shows the results of obtaining the wavelength dependence of the light reflectance in the convex portion A and the concave portion B of the silicon substrate shown in FIG. 1 (a). In the wavelength range from about 1.15 to 1.3 μm, the reflectance of the convex portion A is higher than that of the concave portion B. Even if a silicon oxide film is deposited on the convex portion A and the concave portion B to a thickness of about 1000 nm, the change in the reflectance is small and the magnitude relationship between the convex portion A and the concave portion B is not reversed. I understand. Therefore, about 1.2μ
By heating the silicon substrate with the lamp light such that the wavelength of m becomes maximum intensity, the silicon oxide film 6 is formed while maintaining the temperature of the concave portion B higher than that of the convex portion A. Can be deposited. Since the deposition rate by the low pressure chemical vapor deposition largely depends on the growth temperature, it is possible to deposit a relatively thin silicon oxide film on the convex portion A and a relatively thick silicon oxide film on the concave portion B.
【0016】所定の波長、すなわち実施例における1.
2μmのランプ光を得る為には、例えば図3に示すよう
に、原料ガス導入管14を有するチャンバ11上にハロ
ゲンランプ13を設け、このランプ13とシリコン基板
1との間に波長1.2μmの光を透過する干渉フィルタ
12を設ける。この干渉フィルタは薄膜による光の干渉
を利用して特定の波長領域の光のみを選択的に透過させ
るものであり、真空蒸着法等による非金属の多層膜や金
属と非金属の多層膜によって作成が可能である。A predetermined wavelength, that is, 1. in the embodiment.
In order to obtain a lamp light of 2 μm, for example, as shown in FIG. 3, a halogen lamp 13 is provided on a chamber 11 having a source gas introduction pipe 14, and a wavelength of 1.2 μm is provided between the lamp 13 and the silicon substrate 1. The interference filter 12 that transmits the light is provided. This interference filter selectively transmits only light in a specific wavelength range by utilizing the interference of light from a thin film, and is made of a non-metal multi-layer film or a metal-non-metal multi-layer film by a vacuum deposition method or the like. Is possible.
【0017】又図4に示すように、ハロゲンランプ13
Aの光15を分光プリズム16で分光してもよい。ハロ
ゲンランプ光15は波長1μmにピークを持ち、0.2
〜3μmに広がっているが、このランプ光15を分光プ
リズム16に照射し、この透過光15Aをスリット板1
7を介してシリコン基板1に照射する。ランプ光15と
分光プリズム16との相対的角度を変化させることによ
り、所望波長を有する光のみをシリコン基板1に照射さ
せることができる。尚、均一にランプ光を照射させる為
にシリコン基板1を水平方向に動かすようにしてもよ
い。Further, as shown in FIG. 4, the halogen lamp 13
The light 15 of A may be split by the spectral prism 16. Halogen lamp light 15 has a peak at a wavelength of 1 μm,
Although it spreads to 3 μm, the lamp light 15 is irradiated to the spectral prism 16, and the transmitted light 15A is transmitted to the slit plate 1.
The silicon substrate 1 is irradiated via 7. By changing the relative angle between the lamp light 15 and the spectral prism 16, only the light having the desired wavelength can be irradiated onto the silicon substrate 1. The silicon substrate 1 may be moved in the horizontal direction in order to irradiate the lamp light uniformly.
【0018】上記実施例では、ランプ加熱による減圧化
学気相成長により酸化シリコン膜6を層間絶縁膜として
堆積した場合について説明したが、窒化シリコン膜や酸
窒化シリコン膜などの他の絶縁膜や、多結晶シリコン膜
などをそれぞれ適した波長のランプ光を用いて堆積させ
てもよい。In the above embodiment, the case where the silicon oxide film 6 is deposited as the interlayer insulating film by the low pressure chemical vapor deposition by the lamp heating has been described. However, other insulating films such as a silicon nitride film and a silicon oxynitride film, A polycrystalline silicon film or the like may be deposited by using lamp light having an appropriate wavelength.
【0019】又上記実施例では、ランプ加熱による減圧
化学気相成長により薄膜を堆積していたが、薄膜形成法
としてはランプ加熱を用いるならば、常圧化学気相成長
法や、熱酸化法、熱窒化法、熱酸窒化法等でもよい。In the above embodiment, the thin film is deposited by low pressure chemical vapor deposition by lamp heating. However, if lamp heating is used as the thin film forming method, atmospheric pressure chemical vapor deposition method or thermal oxidation method is used. Alternatively, a thermal nitriding method, a thermal oxynitriding method, or the like may be used.
【0020】更に上記実施例では層間絶縁膜の形成につ
いて説明したが、本発明の方法はそれ以外にもトレンチ
素子分離における絶縁膜の埋め込みなど、凹凸を有する
基板上に平坦な膜を堆積する工程に適用することができ
る。Further, although the formation of the interlayer insulating film has been described in the above embodiment, the method of the present invention is not limited to this, and a step of depositing a flat film on a substrate having irregularities, such as embedding an insulating film in trench element isolation. Can be applied to.
【0021】[0021]
【発明の効果】以上説明したように本発明は、所定波長
のランプ光を照射することにより半導体基板を加熱し、
基板上の凹部に比較的厚い薄膜を、基板上の凸部に比較
的薄い薄膜を堆積させることにより平坦な膜堆積が可能
となる。As described above, according to the present invention, the semiconductor substrate is heated by irradiating the lamp light of the predetermined wavelength,
By depositing a relatively thick thin film on the concave portion of the substrate and a relatively thin thin film on the convex portion of the substrate, it becomes possible to deposit a flat film.
【0022】しかも堆積工程だけで基板表面が平坦化で
きるので工程が簡略となり、製造コストを低減すること
ができる。又リフロー工程が必要ないので、高温のリフ
ロー熱処理の必要がない。このため、基板中のドーパン
ト原子の熱拡散を低減できるため、ソース・ドレインの
接合深さを浅くでき、素子の微細化、高集積化が計れ
る。又CMP工程の必要がないので、研磨工程で生じう
る基板損傷、ゴミ発生の問題を回避できる。更に多層配
線の層間絶縁膜の形成に適用することにより、上層の配
線の断線が防止できる。また、多層配線を実現すること
により素子の高集積化が計れる。このように、本発明は
素子の高集積化、信頼性の向上、製造コストの低減に大
きく寄与するものである。Moreover, since the substrate surface can be flattened only by the deposition process, the process is simplified and the manufacturing cost can be reduced. Further, since a reflow process is not required, there is no need for high temperature reflow heat treatment. Therefore, thermal diffusion of the dopant atoms in the substrate can be reduced, so that the source / drain junction depth can be made shallow, and the device can be miniaturized and highly integrated. Further, since there is no need for the CMP process, it is possible to avoid the problems of substrate damage and dust generation that may occur in the polishing process. Further, by applying the method to the formation of the interlayer insulating film of the multi-layered wiring, it is possible to prevent disconnection of the upper wiring. In addition, the high integration of the device can be achieved by realizing the multilayer wiring. As described above, the present invention greatly contributes to high integration of elements, improvement of reliability, and reduction of manufacturing cost.
【図1】本発明の一実施例を説明する為の半導体チップ
の断面図。FIG. 1 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.
【図2】本発明における膜堆積の原理を説明する為の光
の波長と反射率との関係を示す図。FIG. 2 is a diagram showing the relationship between the wavelength of light and the reflectance for explaining the principle of film deposition in the present invention.
【図3】実施例に用いるランプ加熱式成膜装置の構成
図。FIG. 3 is a configuration diagram of a lamp heating type film forming apparatus used in Examples.
【図4】実施例に用いるランプ光の分離を説明する為の
構成図。FIG. 4 is a configuration diagram for explaining separation of lamp light used in an embodiment.
【図5】従来例を説明する為の半導体チップの断面図。FIG. 5 is a cross-sectional view of a semiconductor chip for explaining a conventional example.
1 シリコン基板 2 酸化シリコン膜 3 第1の多結晶シリコン膜 4 容量絶縁膜 5 第2の多結晶シリコン膜 6,6A 酸化シリコン膜 11 チャンバ 12 干渉フィルタ 13,13A ハロゲンランプ 14 ガス導入管 15 ランプ光 16 分光プリズム 17 スリット板 1 Silicon Substrate 2 Silicon Oxide Film 3 First Polycrystalline Silicon Film 4 Capacitance Insulating Film 5 Second Polycrystalline Silicon Film 6,6A Silicon Oxide Film 11 Chamber 12 Interference Filter 13,13A Halogen Lamp 14 Gas Inlet Tube 15 Lamp Light 16 Spectral prism 17 Slit plate
Claims (1)
に所定波長のランプ光を照射し、凸部に比べ凹部の基板
温度を高くしながらCVD法により、凸部に比べ凹部に
比較的厚い膜を形成することを特徴とする半導体装置の
製造方法。1. A semiconductor substrate on which a convex portion and a concave portion are formed is irradiated with a lamp light of a predetermined wavelength, and the substrate temperature of the concave portion is increased as compared with the convex portion by a CVD method, so that the concave portion is relatively comparatively compared with the convex portion. A method of manufacturing a semiconductor device, which comprises forming a thick film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14922195A JPH098037A (en) | 1995-06-15 | 1995-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14922195A JPH098037A (en) | 1995-06-15 | 1995-06-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH098037A true JPH098037A (en) | 1997-01-10 |
Family
ID=15470511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14922195A Pending JPH098037A (en) | 1995-06-15 | 1995-06-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH098037A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005113134A1 (en) * | 2004-05-21 | 2005-12-01 | Mitsubishi Gas Chemical Company, Inc. | Method for oxidizing substance and oxidation apparatus therefor |
JP2006329225A (en) * | 2005-05-23 | 2006-12-07 | Bridgestone Corp | Pipe joint |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6197912A (en) * | 1984-10-19 | 1986-05-16 | Hitachi Ltd | Cvd equipment |
JPS61191039A (en) * | 1985-02-20 | 1986-08-25 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1995
- 1995-06-15 JP JP14922195A patent/JPH098037A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6197912A (en) * | 1984-10-19 | 1986-05-16 | Hitachi Ltd | Cvd equipment |
JPS61191039A (en) * | 1985-02-20 | 1986-08-25 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005113134A1 (en) * | 2004-05-21 | 2005-12-01 | Mitsubishi Gas Chemical Company, Inc. | Method for oxidizing substance and oxidation apparatus therefor |
US7892404B2 (en) | 2004-05-21 | 2011-02-22 | Mitsubishi Gas Chemical Company, Inc. | Method for oxidizing substance and oxidation apparatus therefor |
JP2006329225A (en) * | 2005-05-23 | 2006-12-07 | Bridgestone Corp | Pipe joint |
JP4679240B2 (en) * | 2005-05-23 | 2011-04-27 | 株式会社ブリヂストン | Pipe fitting |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6180510B1 (en) | Method of manufacturing a substantially flat surface of a semiconductor device through a polishing operation | |
JP2640174B2 (en) | Semiconductor device and manufacturing method thereof | |
US5877045A (en) | Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition | |
US5750403A (en) | Method of forming multi-layer wiring utilizing hydrogen silsesquioxane resin | |
US5567661A (en) | Formation of planarized insulating film by plasma-enhanced CVD of organic silicon compound | |
US5880039A (en) | Method for forming interlayer insulating film of a semiconductor device | |
US6635568B2 (en) | Refractory metal roughness reduction using high temperature anneal in hydrides or organo-silane ambients | |
US8101452B2 (en) | Image sensor and method for manufacturing the same | |
KR20000057801A (en) | An integrated circuit device having a planar interlevel dielectric layer | |
US5904558A (en) | Fabrication process of semiconductor device | |
US20070128885A1 (en) | Method for fabricating a semiconductor device | |
JPH098037A (en) | Manufacture of semiconductor device | |
US6287948B1 (en) | Semiconductor device and method for making pattern data | |
JPH0936117A (en) | Multilayer wiring forming method | |
JPH06163523A (en) | Fabrication of semiconductor device | |
JP3127983B2 (en) | Method for manufacturing semiconductor device | |
KR20000004099A (en) | Method for forming an interlayer dielectric of semiconductor devices | |
JP3401322B2 (en) | Method for manufacturing semiconductor device having insulating film | |
KR0161467B1 (en) | Planerizing method of semiconductor device | |
JPS5827335A (en) | Manufacture of semiconductor device | |
JPS6091632A (en) | Thin film forming process | |
KR100248344B1 (en) | Method for manufacturing semiconductor device | |
US6277754B1 (en) | Method of planarizing dielectric layer | |
US6169026B1 (en) | Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer | |
KR0140736B1 (en) | A method planarization insulation oxied film of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19971125 |