JPH0974265A - Manufacture of wiring board - Google Patents

Manufacture of wiring board

Info

Publication number
JPH0974265A
JPH0974265A JP9334696A JP9334696A JPH0974265A JP H0974265 A JPH0974265 A JP H0974265A JP 9334696 A JP9334696 A JP 9334696A JP 9334696 A JP9334696 A JP 9334696A JP H0974265 A JPH0974265 A JP H0974265A
Authority
JP
Japan
Prior art keywords
thin film
layer
film layer
photoresist
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9334696A
Other languages
Japanese (ja)
Inventor
Takeshi Ono
大野  猛
Toshikatsu Takada
俊克 高田
Toshiharu Oshima
年治 大島
Koji Kanamori
孝司 金森
Tomomi Sonoda
友美 園田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP9334696A priority Critical patent/JPH0974265A/en
Publication of JPH0974265A publication Critical patent/JPH0974265A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To enhance the adhesion of a Ti thin film layer to a photo resist layer to obtain a high-accuracy wiring pattern by a method wherein a plating is applied to an exposed base thin film layer and the photoresist layer is removed to remove the Ti thin film layer and the base thin film layer, which are positioned under the lower part of the photoresist layer. SOLUTION: A polyimide precursor is cured on the whole surface of an alumina substrate 1 containing Al2 O3 to form as a polyimide resin layer 2 and a base thin film layer 3 for a Cr thin film 3a and a Pd thin film 3b and moreover, a Ti thin film layer 4 are subjected to sputtering in order on the layer 2. A novolak resin photoresist 5 is applied on the layer 4 and the layer 5 is exposed and is dried to provide apertures in a wiring pattern. After that, the layer 4 is removed and the layer 3 having the thin film 3b on its upper surface is made to expose. Then, the substrate is cleaned, subsequently an electrolytic Au plated film is formed on wiring pattern parts 6. Moreover, the left photoresist layer 5 and the thin film layers 4 and 3, which are positioned under the lower part of the layer 5, are respectively removed with an etching liquid.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、配線基板の製造
方法に関する。この方法によって製造された配線基板
は、高密度多層基板、サーマルプリンタヘッド等に好適
に利用されうる。
TECHNICAL FIELD The present invention relates to a method of manufacturing a wiring board. The wiring board manufactured by this method can be suitably used for a high-density multilayer board, a thermal printer head, and the like.

【0002】[0002]

【従来の技術】配線基板を高密度多層化又は小型化する
ために、フォトレジストを用いたフォトリソグラフィ技
術及び薄膜技術により微細な導体配線を形成することが
知られている。
2. Description of the Related Art It is known to form a fine conductor wiring by a photolithography technique and a thin film technique using a photoresist in order to make a wiring board have a high density and a multilayer structure.

【0003】例えば、特公平1−39236号公報で
は、絶縁基板上に薄膜を設け、フォトレジストを塗布
し、露光及び現像を経てパターンを形成し、貴金属メッ
キをした後、フォトレジストを除去し、更にメッキ部以
外の薄膜をエッチング除去することにより、高密度多層
基板を製造する方法が記載されている。この方法は、配
線パターンを薄膜で形成する基本的な技術を開示したも
ので、基材としてはガラスやセラミックのような無機材
料のみが例示されている。
For example, in Japanese Patent Publication No. 1-39236, a thin film is provided on an insulating substrate, a photoresist is applied, a pattern is formed through exposure and development, a noble metal is plated, and then the photoresist is removed. Furthermore, a method for producing a high-density multilayer substrate by etching away the thin film other than the plated portion is described. This method discloses a basic technique of forming a wiring pattern with a thin film, and only inorganic materials such as glass and ceramics are exemplified as the base material.

【0004】その後、基材としてポリイミドのような有
機材料でも適用可能なように種々改良がなされ、特開平
1−120094号公報において、絶縁基板上に順にC
r、Ti、CuもしくはAu及びCrの薄膜を形成し、
フォトレジストを塗布し、露光及び現像を経てパターン
を形成し、フォトレジストの存在しない部分のCrをエ
ッチングし、CuもしくはAuの薄膜上にCu、Auな
どの低抵抗金属をメッキすることにより、配線基板を製
造する方法が提案された。この方法は、フォトレジスト
やポリイミドとの密着性のよいCrを上下に形成してメ
ッキ液が薄膜と樹脂との隙間に潜り込むのを防止すると
ともに、メッキし易いCuやAuの薄膜を中間に介在さ
せてメッキ膜と薄膜との密着性をよくし、さらにCrエ
ッチング液が浸透して下側のCr薄膜まで侵さないよう
に遮蔽層としてTiを介在させたものである。
After that, various improvements were made so that an organic material such as polyimide can be applied as a base material. In JP-A-1-120094, C was sequentially formed on an insulating substrate.
forming a thin film of r, Ti, Cu or Au and Cr,
Wiring is performed by applying a photoresist, forming a pattern through exposure and development, etching Cr in the portion where the photoresist does not exist, and plating a thin film of Cu or Au with a low resistance metal such as Cu or Au. A method of manufacturing a substrate has been proposed. In this method, Cr, which has good adhesiveness to a photoresist or polyimide, is formed on the upper and lower sides to prevent the plating solution from penetrating into the gap between the thin film and the resin, and a thin film of Cu or Au that is easy to plate is interposed in the middle. In this way, the adhesion between the plating film and the thin film is improved, and further, Ti is interposed as a shielding layer so that the Cr etching solution does not permeate to the lower Cr thin film.

【0005】これらはいずれの場合も、ポジ型及びネガ
型の2種類のフォトレジストが適用可能である。ポジ型
は、紫外線照射部分が可溶となるもので、一般にノボラ
ック系樹脂からなる。ネガ型は、紫外線照射部分が不溶
となるもので、一般に環化ポリイソプレンからなる。パ
ターン精度としては本来ポジ型のほうが良いが、組み合
わせられる導体材料や絶縁材料とエッチング液との関係
で適切な方が選択される。
In any of these cases, two types of photoresists, positive type and negative type, can be applied. The positive type is one in which the portion irradiated with ultraviolet rays is soluble and is generally made of a novolac resin. The negative type is one in which the portion irradiated with ultraviolet rays is insoluble and is generally composed of cyclized polyisoprene. As for the pattern accuracy, the positive type is originally better, but an appropriate one is selected depending on the relationship between the conductor material or insulating material to be combined and the etching solution.

【0006】[0006]

【発明が解決しようとする課題】しかし、前記特公平1
−39236号公報記載の方法は、配線パターンを薄膜
で形成する基本的な技術を開示したに過ぎず、薄膜と最
終的に除去されるフォトレジストと密着性まで考慮され
ていない。実際、同公報に例示されているTiもしくは
Wの第1層及びPdもしくはPtの第2層からなる薄膜
のうち、上面をなす第2層とフォトレジストとは本質的
に密着性が悪い。また、そのような薄膜をポリイミドの
ような鏡面に近い基材の上に形成した場合、薄膜表面も
鏡面に近い平坦面となるので、フォトレジストとその直
下の薄膜との密着性が更に悪い。そして、密着性が悪い
と、フォトレジストと薄膜との間に隙間生じて、メッキ
液がその隙間に潜り込み、高い精度の配線パターンが得
られない。
SUMMARY OF THE INVENTION
The method described in Japanese Patent Publication No. 39236 only discloses a basic technique of forming a wiring pattern with a thin film, and does not consider the adhesiveness between the thin film, the photoresist to be finally removed, and the adhesiveness. In fact, among the thin films composed of the first layer of Ti or W and the second layer of Pd or Pt exemplified in the publication, the second layer forming the upper surface and the photoresist have essentially poor adhesion. Further, when such a thin film is formed on a base material such as polyimide which is close to a mirror surface, the surface of the thin film is also a flat surface close to the mirror surface, so that the adhesiveness between the photoresist and the thin film directly below it is even worse. If the adhesiveness is poor, a gap is created between the photoresist and the thin film, and the plating solution penetrates into the gap, and a highly accurate wiring pattern cannot be obtained.

【0007】一方、密着性を改良した前記特開平1−1
20094号公報記載の方法では、フェリシアン化カリ
ウムや水酸化カリウムを含むCrのエッチング液に対し
てノボラック系樹脂が浸食されてしまい、既述のように
本来パターン精度のよいポジ型レジストを適用すること
ができない。
On the other hand, the above-mentioned Japanese Patent Laid-Open No. 1-1 has improved adhesion.
According to the method described in Japanese Patent Publication No. 20094, the novolac resin is corroded with respect to the etching solution of Cr containing potassium ferricyanide or potassium hydroxide, and as described above, a positive resist having originally good pattern accuracy can be applied. Can not.

【0008】それ故、この発明の目的は、薄膜層とフォ
トレジスト層との密着性を向上することにより、メッキ
液の潜り込みを解消し、パターン精度の良い配線基板の
製造方法を提供することにある。
Therefore, an object of the present invention is to improve the adhesion between the thin film layer and the photoresist layer, thereby eliminating the penetration of the plating solution and providing a method of manufacturing a wiring board having a high pattern accuracy. is there.

【0009】[0009]

【課題を解決するための手段】その目的を達成するため
に、この発明の配線基板の製造方法は、基材上に形成さ
れ少なくとも上面が被メッキ可能な材質からなる下地薄
膜層上に、Ti薄膜層を形成する工程と、その上にフォ
トレジストを塗布し、露光現像工程を経て、該フォトレ
ジスト層に所定のパターンの開口部を設け、前記Ti薄
膜層を露出させる工程と、該露出したTi薄膜ををエッ
チングにより除去し、前記下地薄膜層を露出させる工程
と、該露出した下地薄膜層に、メッキを施す工程と、前
記フォトレジスト層を除去する工程と、該フォトレジス
ト層の下部に位置する前記Ti薄膜層および下地薄膜層
を除去する工程とを含むことを特徴とする。
In order to achieve the object, a method of manufacturing a wiring board according to the present invention is characterized in that a Ti film is formed on a base material, at least an upper surface of which is made of a material that can be plated. A step of forming a thin film layer, a step of applying a photoresist on the thin film layer, and a step of exposing and developing the thin film layer of Ti by providing an opening portion of a predetermined pattern in the photoresist layer through an exposure and development step. A step of removing the Ti thin film by etching to expose the underlying thin film layer; a step of plating the exposed underlying thin film layer; a step of removing the photoresist layer; and a step below the photoresist layer. A step of removing the Ti thin film layer and the underlying thin film layer which are located.

【0010】[0010]

【作用】上記方法によれば、被メッキ可能な材質からな
る下地薄膜層上に、Ti薄膜層を形成し、その上にフォ
トレジストを塗布し、露光現像工程を経て、該フォトレ
ジスト層に所定のパターンの開口部を設け、前記Ti薄
膜層を露出させ、該露出したTi薄膜をエッチングによ
り除去し、前記下地薄膜層を露出させ、該露出した下地
薄膜層に、メッキを施し、前記フォトレジスト層を除去
し、該フォトレジスト層の下部に位置する前記Ti薄膜
層および下地薄膜層を除去する。このとき、Tiのエッ
チング液は、Crのエッチング液と異なり硝酸やフッ酸
を含む酸性水溶液であるので、ネガ型フォトレジストは
もちろん、ポジ型フォトレジストをも浸食しない。従っ
て、エッチング前の高い配線パターンの精度が維持され
る。しかもTi薄膜とフォトレジストとの密着性は良い
から、その後にメッキする際、メッキ液の潜り込みが生
じない。よって、高精度の微細な配線が得られる。Ti
薄膜の厚さは、通常1nm〜500nm、好ましくは1
0nm〜100nmである。
According to the above method, a Ti thin film layer is formed on a base thin film layer made of a material that can be plated, a photoresist is applied on the Ti thin film layer, and an exposure and development process is performed to form a predetermined thickness on the photoresist layer. The opening of the pattern is exposed to expose the Ti thin film layer, the exposed Ti thin film is removed by etching, the underlying thin film layer is exposed, the exposed underlying thin film layer is plated, and the photoresist is applied. The layer is removed, and the Ti thin film layer and the underlying thin film layer located under the photoresist layer are removed. At this time, since the Ti etching solution is an acidic aqueous solution containing nitric acid and hydrofluoric acid unlike the Cr etching solution, it does not corrode not only the negative photoresist but also the positive photoresist. Therefore, the high accuracy of the wiring pattern before etching is maintained. In addition, since the adhesion between the Ti thin film and the photoresist is good, the plating solution does not sink when plating is performed thereafter. Therefore, highly accurate fine wiring can be obtained. Ti
The thickness of the thin film is usually 1 nm to 500 nm, preferably 1 nm.
It is 0 nm to 100 nm.

【0011】[0011]

【発明の実施の形態】基材としては、セラミック材料の
ほかポリイミド樹脂等の有機材料も適用可能であり、微
細配線には後者が望ましい。そのほか、シリコンウエハ
ーも適用可能である。いずれにしても、この発明の膜構
成は、表面が鏡面に近い平坦な基材との密着性に優れる
ので、そのような基材に有効である。
BEST MODE FOR CARRYING OUT THE INVENTION As a base material, an organic material such as a polyimide resin can be applied in addition to a ceramic material, and the latter is preferable for fine wiring. In addition, a silicon wafer is also applicable. In any case, the film structure of the present invention is excellent in adhesion to a flat substrate whose surface is close to a mirror surface, and is effective for such a substrate.

【0012】下地薄膜層は、上面が被メッキ可能な材質
で構成されていれば良い。被メッキ可能な材質として
は、Au、Cu、Pdが挙げられる。一方、下面につい
ては特に限定されないが、下面がCrで構成されていれ
ば、Crはポリイミド等の有機材料に対してもセラミッ
ク等の無機材料に対しても密着するので、基材の選定が
容易となり、好ましい。また、下地薄膜層として、C
u、Au、Pd及びNiのうちから1種以上を選ぶのも
好ましい。これらは被メッキ可能であるので、上面に配
線に必要な導体をメッキすることができるうえ、無電解
メッキ可能な材質であるので、無電解メッキによってセ
ラミック等の基材と密着させることができるからであ
る。また、フォトレジストとしては、ネガ型はもとよ
り、ノボラック系樹脂からなるポジ型も適用可能であ
り、高精度パターンのために好ましい。
The base thin film layer may be made of a material whose upper surface can be plated. Examples of the material that can be plated include Au, Cu, and Pd. On the other hand, the lower surface is not particularly limited, but if the lower surface is made of Cr, Cr adheres to both organic materials such as polyimide and inorganic materials such as ceramics, making it easy to select a base material. And is preferable. Further, as the underlying thin film layer, C
It is also preferable to select at least one of u, Au, Pd and Ni. Since these can be plated, conductors necessary for wiring can be plated on the upper surface, and since they are materials that can be electroless plated, they can be adhered to a base material such as ceramics by electroless plating. Is. As the photoresist, not only a negative type but also a positive type made of a novolac resin can be applied, which is preferable for a high precision pattern.

【0013】[0013]

【実施例】【Example】

−実施例1− この発明の第一の実施例を図面とともに説明する。図1
は、この発明の製造方法の第一実施例に従って製造され
る配線基板を工程順に示した断面図である。本例では、
ポリイミドを基材としている。
-Embodiment 1- A first embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 6A is a cross-sectional view showing, in the order of steps, a wiring board manufactured according to the first embodiment of the manufacturing method of the present invention. In this example,
The base material is polyimide.

【0014】Al23含有量92重量%のアルミナ基板
1上の全面にポリイミド前駆体をスピンコートし、温度
80℃でプリベークさせ、続いて窒素雰囲気中350℃
でポリイミド前駆体を硬化させてポリイミド樹脂層2と
し、その上に厚さ25nmのCr薄膜3aおよび厚さ3
00nmのPd薄膜3bからなる下地薄膜層3、更に厚
さ100nmのTi薄膜層4を順にスパッタリングした
(図1(a))。その上にヘキスト社製AZ−4620ノ
ボラック樹脂系フォトレジスト5を厚さ10μmに塗布
し、露光し現像液に浸漬して乾燥することにより幅25
μm、ピッチ50μmの配線パターンの開口部6を設け
た(図1(b))。開口部6の底面には、Ti薄膜層4が
露出している。
A polyimide precursor is spin-coated on the entire surface of an alumina substrate 1 having an Al 2 O 3 content of 92% by weight, prebaked at a temperature of 80 ° C., and subsequently 350 ° C. in a nitrogen atmosphere.
To cure the polyimide precursor to form a polyimide resin layer 2, on which a 25 nm thick Cr thin film 3a and a thickness of 3 are formed.
A base thin film layer 3 made of a Pd thin film 3b having a thickness of 00 nm and a Ti thin film layer 4 having a thickness of 100 nm were sequentially sputtered (FIG. 1 (a)). AZ-4620 novolac resin photoresist 5 manufactured by Hoechst Co., Ltd. is applied thereon to a thickness of 10 μm, exposed, immersed in a developing solution and dried to give a width of 25 μm.
An opening 6 having a wiring pattern of μm and a pitch of 50 μm was provided (FIG. 1 (b)). The Ti thin film layer 4 is exposed on the bottom surface of the opening 6.

【0015】その後、その配線パターン部(開口部)6
のTi薄膜層4をエッチング液(硝酸とフッ酸の混合
液)で除去し、Pd薄膜3bを上面にもつ下地薄膜層3
を露出させた(図1(c))。次いで、基板を洗浄し、続
いてAuメッキ液に浸漬して下地薄膜層3に通電するこ
とにより、下地薄膜層3の露出した配線パターン部6に
厚さ5μmの電解Auメッキ膜7を形成した(図1
(d))。更に、残ったフォトレジスト層5及びその下に
位置するTi薄膜層4および下地薄膜層3をそれぞれの
エッチング液で除去することによって、配線基板を製造
した(図1(e))。本実施例によって、ポリイミド樹脂
層2上にCr及びPdの薄膜3a,3bを下地としてA
uメッキ配線が形成されたことになる。
After that, the wiring pattern portion (opening) 6
Of the Ti thin film layer 4 is removed by an etching solution (mixed solution of nitric acid and hydrofluoric acid), and the underlying thin film layer 3 having the Pd thin film 3b on the upper surface is removed.
Was exposed (Fig. 1 (c)). Next, the substrate was washed, and subsequently, the substrate was immersed in an Au plating solution to energize the underlying thin film layer 3 to form an electrolytic Au plated film 7 having a thickness of 5 μm on the exposed wiring pattern portion 6 of the underlying thin film layer 3. (Fig. 1
(d)). Further, the remaining photoresist layer 5 and the Ti thin film layer 4 and the underlying thin film layer 3 located therebelow were removed by respective etching solutions to manufacture a wiring board (FIG. 1 (e)). According to the present embodiment, the thin films 3a and 3b of Cr and Pd are used as the bases on the polyimide resin layer 2 to form A.
This means that u-plated wiring has been formed.

【0016】得られた配線基板の表面を拡大鏡で観察し
たところ、配線間の短絡はもとより、にじみも生じてい
なかった。Ti薄膜層4とフォトレジスト層5との密着
性が高いため、Auメッキ液が両者の間に潜り込むこと
がなく、また、Ti薄膜層4をエッチング除去しても、
ノボラック系樹脂であるフォトレジストを侵すことがな
いので、配線パターンににじみが生じなかったからであ
る。
When the surface of the obtained wiring board was observed with a magnifying glass, not only a short circuit between wirings but also no bleeding occurred. Since the adhesion between the Ti thin film layer 4 and the photoresist layer 5 is high, the Au plating solution does not penetrate between the two, and even if the Ti thin film layer 4 is removed by etching,
This is because the photoresist, which is a novolac resin, is not attacked, so that the wiring pattern is not bleed.

【0017】なお、上記実施例においては、基材として
ポリイミド樹脂を用い、この基材上に薄膜層及びフォト
レジスト層を形成した例を示したが、その他、エポキシ
樹脂、BCB樹脂等の有機樹脂を基材として用いても良
いことは明らかである。さらに、アルミナ、ムライト、
AlN、ガラスセラミック、ガラス等の無機材料からな
る基板を基材として用いても良い。
In the above embodiments, the polyimide resin is used as the base material and the thin film layer and the photoresist layer are formed on the base material. However, other organic resins such as epoxy resin and BCB resin are also used. Obviously, may be used as a substrate. In addition, alumina, mullite,
A substrate made of an inorganic material such as AlN, glass ceramic, or glass may be used as the base material.

【0018】また、上記実施例では下地薄膜層としてC
r薄膜およびPd薄膜からなるものを用いたが、Crに
代えて基材との密着性の高い材質(例えば、Mo、Z
r、Ti、Ti−Mo等)を用いても良い。更に、上面
が被メッキ可能な材質であればよいので、Pdに代え
て、Cu、Au等を用いても良い。また、下地薄膜層
は、上記実施例では、Cr/Pdの2層からなるものを
示したが、上面が被メッキ可能なPd、Cu、Au等で
構成されていれば2層以上の層を重ねても良く、逆に基
材との密着性が得られるならばPd等の単一層であって
も良い。
In the above embodiment, C is used as the underlying thin film layer.
Although a thin film composed of an r thin film and a Pd thin film was used, a material having high adhesion to the base material (for example, Mo, Z
r, Ti, Ti-Mo, etc.) may be used. Furthermore, Cu, Au, or the like may be used instead of Pd as long as the upper surface can be plated. Further, the base thin film layer is shown to be composed of two layers of Cr / Pd in the above embodiment, but if the upper surface is composed of Pd, Cu, Au or the like which can be plated, two or more layers are formed. The layers may be stacked, or conversely, a single layer of Pd or the like may be used as long as the adhesion to the base material is obtained.

【0019】−比較例1− Ti薄膜層4に代えてCr薄膜を形成し、且つこのCr
薄膜のエッチング液としてフェリシアン化カリウム10
%を用いる以外は、上記実施例1と同一条件で配線基板
を製造しようとしたところ、配線パターン形成後の不要
のCr薄膜をエッチング液で除去する際、フォトレジス
トが溶けて配線パターンが崩れた。従って、その後のメ
ッキが不可能となった。ノボラック系樹脂はアルカリに
対して溶解するからである。
-Comparative Example 1-A Cr thin film was formed in place of the Ti thin film layer 4, and this Cr thin film was formed.
Potassium ferricyanide 10 as thin film etching solution
An attempt was made to manufacture a wiring board under the same conditions as in Example 1 except for using%. When the unnecessary Cr thin film after forming the wiring pattern was removed with an etching solution, the photoresist melted and the wiring pattern collapsed. . Therefore, the subsequent plating became impossible. This is because the novolac resin dissolves in alkali.

【0020】−比較例2− この例は、被メッキ可能な薄膜の上にTi薄膜層4も比
較例1で示したCr薄膜も形成することなく、直接フォ
トレジストを塗布する方法である。すなわち、Ti薄膜
層4の形成及びTiのエッチング液への浸漬を省略した
以外は、上記実施例と同一条件で配線基板を製造した。
-Comparative Example 2-This example is a method of directly coating a photoresist without forming the Ti thin film layer 4 or the Cr thin film shown in Comparative Example 1 on a thin film that can be plated. That is, a wiring board was manufactured under the same conditions as those of the above-described example except that the formation of the Ti thin film layer 4 and the immersion of Ti in the etching solution were omitted.

【0021】得られた配線基板の表面を拡大鏡で観察し
たところ、配線の縁ににじみが生じて隣接する配線間で
短絡していた。これは、フォトレジストとPd薄膜との
密着性が低いので、両者の間の隙間にメッキ液が潜り込
んだためと考えられる。
When the surface of the obtained wiring board was observed with a magnifying glass, bleeding occurred at the edge of the wiring and short-circuiting occurred between adjacent wirings. It is considered that this is because the adhesiveness between the photoresist and the Pd thin film is low, and thus the plating solution sunk into the gap between the two.

【0022】−実施例2− この発明の第二の実施例を図面とともに説明する。図2
は、この発明の製造方法の第二実施例に従って製造され
る配線基板を工程順に示した断面図である。本例では、
基板材質を兼ねるアルミナを基材としている。
Second Embodiment A second embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 6A is a sectional view showing a wiring board manufactured according to the second embodiment of the manufacturing method of the present invention in the order of steps. In this example,
The base material is alumina, which also serves as the substrate material.

【0023】Al23含有量92重量%のアルミナ基板
11上の全面に、厚さ50nmのCr薄膜13aおよび
厚さ500nmのPd薄膜13bからなる下地薄膜層1
3、更に厚さ100nmのTi薄膜層14を順にスパッ
タリングした(図2(a))。その上にヘキスト社製AZ
−4620ノボラック樹脂系フォトレジスト15を厚さ
10μmに塗布し、露光し現像液に浸漬して乾燥するこ
とにより幅25μm、ピッチ50μmの配線パターンの
開口部16を設けた(図2(b))。開口部16の底面に
は、Ti薄膜層14が露出している。
A base thin film layer 1 consisting of a Cr thin film 13a having a thickness of 50 nm and a Pd thin film 13b having a thickness of 500 nm is formed on the entire surface of an alumina substrate 11 having an Al 2 O 3 content of 92% by weight.
3. Then, a Ti thin film layer 14 having a thickness of 100 nm was sequentially sputtered (FIG. 2 (a)). AZ manufactured by Hoechst
-4620 Novolac resin photoresist 15 was applied to a thickness of 10 μm, exposed, immersed in a developing solution, and dried to provide an opening 16 of a wiring pattern having a width of 25 μm and a pitch of 50 μm (FIG. 2 (b)). . The Ti thin film layer 14 is exposed on the bottom surface of the opening 16.

【0024】その後、その配線パターン部(開口部)1
6のTi薄膜層4をエッチング液(硝酸とフッ酸の混合
液)で除去し、Pd薄膜13bを上面にもつ下地薄膜層
13を露出させた(図2(c))。次いで、基板を洗浄
し、続いてAuメッキ液に浸漬して下地薄膜層13に通
電することにより、下地薄膜層3の露出した配線パター
ン部16に厚さ5μmの電解Auメッキ膜17を形成し
た(図2(d))。更に、残ったフォトレジスト層15及
びその下に位置するTi薄膜層14および下地薄膜層1
3をそれぞれのエッチング液で除去することによって、
配線基板を製造した(図2(e))。本実施例によって、
アルミナ基板11上にCr及びPdの薄膜13a,13
bを下地としてAuメッキ配線が形成されたことにな
る。
After that, the wiring pattern portion (opening) 1
The Ti thin film layer 4 of No. 6 was removed with an etching solution (mixed solution of nitric acid and hydrofluoric acid) to expose the underlying thin film layer 13 having the Pd thin film 13b on the upper surface (FIG. 2 (c)). Then, the substrate was washed, and subsequently, the substrate was immersed in an Au plating solution to energize the underlying thin film layer 13 to form an electrolytic Au plating film 17 having a thickness of 5 μm on the exposed wiring pattern portion 16 of the underlying thin film layer 3. (Fig. 2 (d)). Furthermore, the remaining photoresist layer 15, the Ti thin film layer 14 and the underlying thin film layer 1 located thereunder
By removing 3 with each etchant,
A wiring board was manufactured (Fig. 2 (e)). According to this embodiment,
Cr and Pd thin films 13a, 13 on the alumina substrate 11
This means that the Au-plated wiring was formed using b as the base.

【0025】得られた配線基板の表面を拡大鏡で観察し
たところ、配線間の短絡はもとより、にじみも生じてい
なかった。Ti薄膜層14とフォトレジスト層15との
密着性が高いため、Auメッキが両者の間に潜り込むこ
とがなく、また、Ti薄膜層14をエッチング除去して
も、ノボラック系樹脂であるフォトレジストを侵すこと
がないので、配線パターンににじみが生じなかったから
である。
When the surface of the obtained wiring board was observed with a magnifying glass, no bleeding occurred as well as a short circuit between the wirings. Since the adhesion between the Ti thin film layer 14 and the photoresist layer 15 is high, Au plating does not penetrate between them, and even if the Ti thin film layer 14 is removed by etching, the photoresist which is a novolac resin can be removed. This is because there is no bleeding, and therefore no bleeding occurs in the wiring pattern.

【0026】更に、前記実施例1及び本例から、下地薄
膜層がCrからなる下面を有するときは、基材が実施例
1のようにポリイミド樹脂であろうと本例のようにセラ
ミックであろうと、下地薄膜層が基材と密着することが
明らかである。
Further, according to the first and the present examples, when the base thin film layer has the lower surface made of Cr, the base material may be the polyimide resin as in the first embodiment or the ceramic as in the present example. It is clear that the underlying thin film layer adheres to the substrate.

【0027】−実施例3− この発明の第三の実施例を図面とともに説明する。図3
は、この発明の製造方法の第三実施例に従って製造され
る配線基板を工程順に示した断面図である。本例でも、
基板材質を兼ねるアルミナを基材としている。
Third Embodiment A third embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 6A is a sectional view showing a wiring board manufactured according to a third embodiment of the manufacturing method of the present invention in the order of steps. Also in this example,
The base material is alumina, which also serves as the substrate material.

【0028】Al23含有量92重量%のアルミナ基板
21上の全面に、厚さ500nmのCuからなる下地薄
膜層23を無電解メッキし、その上に厚さ100nmの
Ti薄膜層24をスパッタリングした(図3(a))。そ
の上にヘキスト社製AZ−4620ノボラック樹脂系フ
ォトレジスト25を厚さ10μmに塗布し、露光し現像
液に浸漬して乾燥することにより幅25μm、ピッチ5
0μmの配線パターンの開口部26を設けた(図3
(b))。開口部26の底面には、Ti薄膜層24が露出
している。
On the entire surface of the alumina substrate 21 having an Al 2 O 3 content of 92% by weight, a 500 nm thick underlying thin film layer 23 of Cu is electrolessly plated, and a 100 nm thick Ti thin film layer 24 is formed thereon. It was sputtered (FIG. 3 (a)). AZ-4620 novolac resin photoresist 25 manufactured by Hoechst Co., Ltd. is applied thereon to a thickness of 10 μm, exposed to light, dipped in a developing solution and dried to give a width of 25 μm and a pitch of 5
An opening 26 having a wiring pattern of 0 μm is provided (see FIG. 3).
(b)). The Ti thin film layer 24 is exposed on the bottom surface of the opening 26.

【0029】その後、その配線パターン部(開口部)2
6のTi薄膜層4をエッチング液(硝酸とフッ酸の混合
液)で除去し、Cuからなる下地薄膜層3を露出させた
(図3(c))。次いで、基板を洗浄し、続いて下地薄膜
層23に通電しながらCuメッキ液、Niメッキ液及び
Auメッキ液に順に浸漬することにより、下地薄膜層2
3の露出した配線パターン部26に厚さ2μmのCu膜
27a、厚さ1μmのNi膜27b及び厚さ2μmのA
u膜27cからなるメッキ膜27を形成した(図3
(d))。更に、残ったフォトレジスト層25及びその下
に位置するTi薄膜層24および下地薄膜層23をそれ
ぞれのエッチング液で除去することによって、配線基板
を製造した(図3(e))。本実施例によって、アルミナ
基板1上にCuのメッキ膜を下地としてCu/Ni/A
u3層メッキ配線が形成されたことになる。
After that, the wiring pattern portion (opening) 2
The Ti thin film layer 4 of No. 6 was removed by an etching solution (mixed solution of nitric acid and hydrofluoric acid) to expose the underlying thin film layer 3 made of Cu (FIG. 3 (c)). Next, the substrate is washed, and subsequently, while being energized to the underlying thin film layer 23, the substrate is immersed in a Cu plating solution, a Ni plating solution, and an Au plating solution in this order, whereby
3 has a Cu film 27a with a thickness of 2 μm, a Ni film 27b with a thickness of 1 μm, and an A with a thickness of 2 μm.
A plating film 27 made of the u film 27c was formed (see FIG. 3).
(d)). Further, the remaining photoresist layer 25 and the Ti thin film layer 24 and the underlying thin film layer 23 located therebelow were removed by respective etching solutions to manufacture a wiring board (FIG. 3 (e)). According to this embodiment, Cu / Ni / A is formed on the alumina substrate 1 with a Cu plating film as a base.
This means that u3 layer plated wiring is formed.

【0030】得られた配線基板の表面を拡大鏡で観察し
たところ、配線間の短絡はもとより、にじみも生じてい
なかった。Ti薄膜層24とフォトレジスト層25との
密着性が高いため、Cuメッキ液、Niメッキ液及びA
uメッキ液のいずれも両者の間に潜り込むことがなく、
また、Ti薄膜層24をエッチング除去しても、ノボラ
ック系樹脂であるフォトレジストを侵すことがないの
で、配線パターンににじみが生じなかったからである。
When the surface of the obtained wiring board was observed with a magnifying glass, not only a short circuit between wirings but also no bleeding occurred. Since the adhesion between the Ti thin film layer 24 and the photoresist layer 25 is high, Cu plating solution, Ni plating solution and A
None of the u-plating liquid will sneak between the two,
Further, even if the Ti thin film layer 24 is removed by etching, it does not attack the photoresist which is a novolac resin, so that the wiring pattern does not have bleeding.

【0031】更に、本例では、下地薄膜層として、被メ
ッキ可能であると同時に自らもアルミナ基板に無電解メ
ッキ可能なCuを用いているので、Cu1層で上面に配
線に必要な導体をメッキすることができるばかりか、基
板とも密着し、膜構成及び工程が簡単である。
Further, in this example, since Cu which can be plated and at the same time can be electrolessly plated on the alumina substrate is used as the underlying thin film layer, the conductor required for wiring is plated on the upper surface with the Cu1 layer. Not only can it be done, but it is also in close contact with the substrate, and the film structure and process are simple.

【0032】[0032]

【発明の効果】以上のように、本発明の製造方法によれ
ば、メッキ液の種類に係わらず薄膜層とフォトレジスト
層との間にメッキ液が潜り込むのを防止することができ
る。その結果、ネガ型レジストはもとより、ポジ型レジ
ストによって形成された高い精度の配線パターンを有す
る配線基板を得ることができるので、配線基板の高密度
多層化及び小型化に寄与する。
As described above, according to the manufacturing method of the present invention, it is possible to prevent the plating solution from penetrating between the thin film layer and the photoresist layer regardless of the type of the plating solution. As a result, it is possible to obtain a wiring board having a highly accurate wiring pattern formed of a positive resist as well as a negative resist, which contributes to high density multi-layering and miniaturization of the wiring board.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例1の製造方法を工程順に説明する断面図
である。
1A to 1C are cross-sectional views illustrating a manufacturing method according to a first embodiment in the order of steps.

【図2】実施例2の製造方法を工程順に説明する断面図
である。
2A to 2D are cross-sectional views illustrating a manufacturing method according to a second embodiment in the order of steps.

【図3】実施例3の製造方法を工程順に説明する断面図
である。
FIG. 3 is a cross-sectional view illustrating the manufacturing method of the third embodiment in the order of steps.

【符号の説明】[Explanation of symbols]

1,11,21 アルミナ基板 2 ポリイミド樹脂層 3,13,23 下地薄膜層 4,14,24 Ti薄膜層 5,15,25 フォトレジスト層 6,16,26 開口部(配線パターン部) 7,17,27 Auメッキ膜 1,11,21 Alumina substrate 2 Polyimide resin layer 3,13,23 Base thin film layer 4,14,24 Ti thin film layer 5,15,25 Photoresist layer 6,16,26 Opening part (wiring pattern part) 7,17 , 27 Au plating film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 金森 孝司 愛知県名古屋市瑞穂区高辻町14番18号 日 本特殊陶業株式会社内 (72)発明者 園田 友美 愛知県名古屋市瑞穂区高辻町14番18号 日 本特殊陶業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koji Kanamori No. 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Nihon Special Ceramics Co., Ltd. (72) Inventor Tomomi 14 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi No. 18 Nihon Special Ceramics Co., Ltd.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基材上に形成され少なくとも上面が被メッ
キ可能な材質からなる下地薄膜層上に、Ti薄膜層を形
成する工程と、 その上にフォトレジストを塗布し、露光現像工程を経
て、該フォトレジスト層に所定のパターンの開口部を設
け、前記Ti薄膜層を露出させる工程と、 該露出したTi薄膜をエッチングにより除去し、前記下
地薄膜層を露出させる工程と、 該露出した下地薄膜層に、メッキを施す工程と、前記フ
ォトレジスト層を除去する工程と、 該フォトレジスト層の下部に位置する前記Ti薄膜層お
よび下地薄膜層を除去する工程とを含むことを特徴とす
る配線基板の製造方法。
1. A step of forming a Ti thin film layer on a base thin film layer formed on a base material and at least having an upper surface made of a material capable of being plated, a photoresist is applied thereon, and an exposure and development step is performed. A step of exposing the Ti thin film layer by providing an opening of a predetermined pattern in the photoresist layer, a step of removing the exposed Ti thin film by etching to expose the underlying thin film layer, and the exposed underlayer. A wiring comprising: a step of plating the thin film layer, a step of removing the photoresist layer, and a step of removing the Ti thin film layer and the underlying thin film layer located under the photoresist layer. Substrate manufacturing method.
【請求項2】前記基材がポリイミド樹脂等の有機材料で
ある請求項1に記載の配線基板の製造方法。
2. The method for manufacturing a wiring board according to claim 1, wherein the base material is an organic material such as a polyimide resin.
【請求項3】前記基材がセラミック材料である請求項1
に記載の配線基板の製造方法。
3. The substrate is a ceramic material.
A method for manufacturing a wiring board according to.
【請求項4】前記下地薄膜層がCrからなる下面を有す
る請求項1〜3のいずれかに記載の配線基板の製造方
法。
4. The method for manufacturing a wiring board according to claim 1, wherein the underlying thin film layer has a lower surface made of Cr.
【請求項5】前記下地薄膜層がCu、Au、Pd及びN
iのうちから選ばれる1種以上からなる請求項1〜3の
いずれかに記載の配線基板の製造方法。
5. The base thin film layer is Cu, Au, Pd and N.
The method for manufacturing a wiring board according to claim 1, comprising at least one selected from i.
【請求項6】前記フォトレジストがノボラック系樹脂で
ある請求項1〜5のいずれかに記載の配線基板の製造方
法。
6. The method for manufacturing a wiring board according to claim 1, wherein the photoresist is a novolac resin.
JP9334696A 1995-06-28 1996-03-21 Manufacture of wiring board Pending JPH0974265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9334696A JPH0974265A (en) 1995-06-28 1996-03-21 Manufacture of wiring board

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP18645595 1995-06-28
JP7-186455 1995-06-28
JP9334696A JPH0974265A (en) 1995-06-28 1996-03-21 Manufacture of wiring board

Publications (1)

Publication Number Publication Date
JPH0974265A true JPH0974265A (en) 1997-03-18

Family

ID=26434741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9334696A Pending JPH0974265A (en) 1995-06-28 1996-03-21 Manufacture of wiring board

Country Status (1)

Country Link
JP (1) JPH0974265A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108235578A (en) * 2018-01-02 2018-06-29 京东方科技集团股份有限公司 PCB silk-screens production method, PCB screen printing patterns and pcb board
JP2020072166A (en) * 2018-10-31 2020-05-07 京セラ株式会社 Printed-circuit board and method for manufacturing printed-circuit board
CN114447552A (en) * 2022-02-10 2022-05-06 西南应用磁学研究所(中国电子科技集团公司第九研究所) Novel micro-strip circulator based on MEMS (micro-electromechanical systems) process and processing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108235578A (en) * 2018-01-02 2018-06-29 京东方科技集团股份有限公司 PCB silk-screens production method, PCB screen printing patterns and pcb board
JP2020072166A (en) * 2018-10-31 2020-05-07 京セラ株式会社 Printed-circuit board and method for manufacturing printed-circuit board
CN114447552A (en) * 2022-02-10 2022-05-06 西南应用磁学研究所(中国电子科技集团公司第九研究所) Novel micro-strip circulator based on MEMS (micro-electromechanical systems) process and processing method thereof
CN114447552B (en) * 2022-02-10 2023-01-13 西南应用磁学研究所(中国电子科技集团公司第九研究所) Novel micro-strip circulator based on MEMS (micro-electromechanical systems) process and processing method thereof

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