JP2003179329A - Wiring pattern formation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of efficiently forming a desired wiring pattern in the case of applying a hard etching material such as platinum as a wiring material at the time of forming a wiring pattern on a substrate. <P>SOLUTION: In this invention, for a pattern formation method by a conventional additive method, the order of a catalyst imparting process, a resist applying process and a thin film forming process is changed and further a process of forming a protective layer shielding a catalyst layer is provided in order to prevent organic compounds from sticking to a catalyst surface at the time of immersion in a resist removal liquid. As the protective layer, Ti, Cr, Fe, Co, Ni, Cu, Ag, Au, Sn, In or the oxide, carbide and nitride can be applied. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring pattern on a printed wiring board used for electronic equipment or the like. In particular, the present invention relates to a method capable of efficiently forming a wiring pattern with a difficult-to-etch material.

[0002]

2. Description of the Related Art With the recent demand for miniaturization and high functionality of electronic devices, circuit boards are required to have higher density and thinner thickness. A method called an additive method is known as a method of forming a wiring pattern of this high-density circuit board.

An example of a pattern forming process by this additive method is shown in FIG. In FIG. 5, after the catalyst 2 such as a palladium compound is applied to the surface of the substrate 1 (see FIG.
(B)), a thin film 3 of the wiring material is formed on the entire surface of the insulating substrate by using a catalyst as a nucleus by a method such as electroless plating (FIG. 5C). Next, a resist 4 is applied to the surface of the thin film 3 (FIG. 5D), and exposed and developed to remove the resist so that only the resist on the wiring pattern remains (FIG. 5E). After the resist is removed, the substrate is etched to remove the thin film other than the wiring pattern (FIG. 5 (f)). Finally, the resist 4 is peeled off to form a predetermined wiring pattern on the substrate (FIG. 5G).

This conventional pattern forming method has an advantage that a fine circuit can be formed with high precision. However, when the pattern is formed using a material having a high corrosion resistance such as platinum or a platinum alloy. However, there is a problem that the etching process cannot be performed efficiently. At present, wiring materials for wiring boards are made of metals with good etching properties such as copper, but platinum and platinum alloys are materials with good electrical characteristics, especially good dielectric constant, and will be used as wiring materials for wiring boards in the future. Is being considered, and it is considered that it is necessary to efficiently form a pattern even when platinum or the like is used for that purpose.

In order to solve such a problem, the method shown in FIG. 6 can be considered as an improvement measure of the above method. In FIG. 6, this improved method is based on the step of applying a catalyst (FIG. 6 (b)).
After that, the resist 4 is applied (FIG. 6C), and the resist is removed along the wiring pattern (FIG. 6D).
Accordingly, since the thin film is formed only on the wiring pattern in the subsequent thin film forming step, a desired wiring pattern can be formed without considering the etching characteristics of the wiring material.

However, there is a problem with this improvement measure. That is, in this method, a thin film is formed in a state where the resist remains on a portion other than the wiring pattern after exposure / development. However, when the thin film is formed by a plating method, the resist may be peeled off by the plating solution. There is. In particular, since an alkaline solution is often used as the resist stripping solution, when an alkaline plating solution is used, the resist stripping becomes remarkable and the wiring pattern cannot be formed. Further, the peeling of the resist also causes contamination of the plating solution, which may reduce the plating efficiency. Therefore, this improved method is also not suitable.

[0007]

Therefore, the present invention provides a method for forming a desired wiring pattern in a method for forming a wiring pattern on a substrate, even when a highly corrosion resistant material such as platinum is used as the wiring material. An object is to provide a method that can be efficiently formed.

[0008]

Means for Solving the Problems The inventors of the present invention have made diligent studies and, as a condition for solving the above problems, a thin film forming step (a plating solution is applied to a substrate to prevent elution of the resist after coating the resist). The step of immersing in) is a post-step of resist application, and that a thin film can be formed only on the wiring pattern so that etching of the wiring material is not required. I thought.

Then, the present inventors have examined the method satisfying the above two conditions and found the method shown in FIGS. Hereinafter, these methods will be described.

In the method shown in FIG. 1, first, a resist 4 is applied on the substrate 1 (FIG. 1 (b)) and exposed and developed to remove the resist on the intended wiring pattern (see FIG. 1). (C)), the catalyst layer 2 is formed on the surface of this substrate (FIG. 1 (d)). Then, the remaining resist and catalyst layer other than the wiring pattern are removed (FIG. 1E), and a thin film made of a wiring material is formed on the catalyst layer on the wiring pattern (FIG. 1F). .

On the other hand, the method shown in FIG. 2 is different from the above method in that a catalyst layer is first formed on the surface of the substrate (FIG.
(B)) The resist 4 is applied onto the substrate (FIG. 2 (c)). Next, by exposing and developing this substrate, the resist is removed so that the resist on the predetermined wiring pattern remains (FIG. 2D), and the catalyst layer is further removed (FIG. 2E). Then, after removing the resist on the wiring pattern (FIG. 2 (f)), the wiring material is formed (FIG. 2 (g)).

These methods have the above-mentioned two conditions. In both cases, the elution of the resist is prevented by making the thin film forming step after the resist applying step, and at the time of forming the thin film, on the wiring pattern. By making the catalyst layer exist only in the wiring pattern, the wiring material is deposited only on the wiring pattern, and the etching step is unnecessary. However, when the present inventors tried to form a wiring pattern by these methods, they found that precipitation was unstable in the step of forming a wiring material thin film and a complete wiring pattern could not be formed.

The inventors of the present invention have studied this factor. In the above two methods, the catalyst is exposed on the surface of the catalyst when the substrate is immersed in a removing solution for removing the resist, and therefore the catalyst is removed on the surface of the catalyst. It was considered that this was because the organic compound in the liquid adhered and the catalyst was inactivated. Therefore, the present inventors are based on the above-mentioned two methods, and further, when removing the resist on the wiring pattern or at a portion other than the wiring pattern, when the catalyst surface in the liquid is immersed in the removal liquid. In order to prevent the adhesion of organic compounds, the present invention has been accomplished by incorporating a step of forming a protective layer that shields the catalyst layer.

The first method of the present application is a method of forming a wiring pattern on a substrate, which comprises the following steps.

(A) A step of removing a resist on a predetermined wiring pattern by applying a resist on a substrate and exposing and developing it. (B) A step of forming a catalyst layer on the surface of the substrate. (C) A step of forming a protective layer on the catalyst layer. (D) A step of removing the resist remaining in the area other than the wiring pattern. (E) A step of removing the protective layer. (F) A step of forming a thin film made of a wiring material by electroless plating.

The second method of the present application is a method of forming a wiring pattern on a substrate, which comprises the following steps.

(A) A step of forming a catalyst layer on the surface of the substrate. (B) A step of forming a protective layer on the catalyst layer. (C) A step of applying a resist on a substrate, exposing and developing the resist to remove the resist so that the resist on a predetermined wiring pattern remains. (D) A step of removing the protective layer and the catalyst layer. (E) A step of removing the resist on the wiring pattern. (F) A step of removing the protective layer. (G) A step of forming a thin film made of a wiring material by electroless plating.

The present invention is characterized in that the order of the step of applying a catalyst, the step of applying a resist, and the step of forming a thin film is different from that of the conventional method, and that it further comprises a step of forming a protective layer on the catalyst layer. . FIG. 3 shows each method according to the present invention.
And FIG. 4 will be described in detail.

FIG. 3 schematically shows a first method according to the present invention. First, the resist 4 is applied on the substrate (FIG. 3B), and the resist on the predetermined wiring pattern is removed by exposure and development (FIG. 3C). As the substrate, any of an insulating substrate such as glass epoxy and a semiconductor substrate such as a silicon wafer can be applied. Further, in the resist coating step here, either a method of laminating a dry film resist or a method of printing a liquid resist may be adopted, but it is necessary to use a positive type resist.

Next, the catalyst layer 2 is formed on the surface of the substrate (FIG. 3 (d)). For this catalyst, palladium, platinum, or the like used in the electroless plating method is used. Also,
The catalyst layer may be formed by either a wet method such as an immersion method or a dry film forming method such as sputtering.

The protective layer 5 is formed on the formed catalyst layer.
Are formed (FIG. 3E). This protective layer is a cash register
Erosion of alkaline solution used as strike removal liquid
It is necessary to not be subject to
As, Ti, Cr, Fe, Co, Ni, Cu, A
metals such as g, Au, Sn, In, or these
It is preferable to form the oxide, carbide, or nitride of the above. Concrete
Specifically, the oxide is Al_TwoO_Three, SiO_Two, Ti
O_Two, SnO_Two, Ta_TwoO₅, In_TwoO_Three, Fe
_TwoO_Three, Fe_ThreeO_Four, Cr_TwoO_Three, WO_ThreeBut with carbide
SiC, TiC, TaC, WC, and nitride
As Si_ThreeN_Four, TiN, AlN, TaN are protective layers
Can function as. In addition, as a method of forming this protective layer
Is a sputtering method, electroplating method, electroless plating method
Is preferred.

In this way, the resist remaining on portions other than the wiring pattern is removed from the substrate on which the protective layer has been formed (FIG. 3 (f)). This resist removal is performed by swelling the resist by immersing the substrate in an alkaline solution such as alkylammonium tetraacid or the like, as is usually done. Even when this alkaline solution is dipped, the surface of the catalyst layer is shielded by the protective film, so that the organic compound that deteriorates the catalyst performance does not adhere.

Through the above steps, only the catalyst layer and the protective layer on the surface of the catalyst layer remain on the wiring pattern of the substrate.
This protective layer is removed by immersing it in an acid such as hydrochloric acid, sulfuric acid, nitric acid (FIG. 3 (g)). Finally, a wiring material is formed by electroless plating (FIG. 3 (h)). A hard etching material such as a platinum group metal can be applied to this wiring material.

Next, the second method of the present application shown in FIG. 4 will be described. In the second method, first, the catalyst layer 2 is formed on the surface of the substrate 1 (FIG. 4 (b)). The type and formation method of the catalyst layer 2 at this time are the same as those of the first method.

Next, the protective layer 5 is formed on the catalyst layer 2 (FIG. 4 (c)). Regarding this protective layer, similar to the first method, Ti, Cr, Fe, Co, Ni, Cu, A
Thin films of single metals, oxides, carbides and nitrides of g, Au, Sn and In are preferable. Further, as a method of forming this protective layer, a sputtering method, an electroplating method, or an electroless plating method can be applied.

After forming the protective layer 5, the resist 4 is applied on the substrate (FIG. 4D) and exposed and developed to leave the resist only on the wiring pattern (FIG. 4).
(E)). Both positive and negative resists can be used at this time. After that, the protective layer 5 and the catalyst layer 2 are removed (FIG. 4 (f)), but this removing method can remove the catalyst layer together with the protective layer by immersing in an acid such as dilute aqua regia.

The step of removing the resist on the wiring pattern (FIG. 4 (g)) is the same as the first method, and a commonly used method such as immersion in an alkaline solution is employed. Also,
The subsequent removal of the protective layer 5 (FIG. 4 (h)) is also the same as in the first method, and is performed by immersion in an acid such as hydrochloric acid, sulfuric acid or nitric acid.

As described above, the catalyst layer exists on the substrate 1 along the wiring pattern. Finally, a thin film made of a wiring material is formed by electroless plating. This method is also the first
The method is the same as that of FIG. 4 (i).

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

First Embodiment : In this embodiment, a circuit pattern is formed based on the first method shown in FIG. A positive type dry film resist was laminated on a silicon substrate by thermocompression bonding, then selectively exposed to ultraviolet rays and developed in a sodium carbonate solution to remove the resist on the circuit pattern.

Next, a catalyst layer was formed by depositing platinum as a catalyst to a thickness of 10 μm by a sputtering method. Then, titanium was plated on the catalyst layer as a protective layer by a sputtering method to a thickness of 50 μm.

Then, the substrate was dipped in a sodium hydroxide solution to remove the remaining resist. The titanium film as the protective layer was immersed in sulfuric acid to be removed, and finally platinum was plated as a wiring material by electroless plating.

When the wiring board manufactured by the above steps was subjected to a defect inspection, it was confirmed that a wiring board of good quality without defects such as disconnection could be manufactured.

Second Embodiment : In this embodiment, circuit patterns are formed based on the second method shown in FIG. Here, first, a catalyst layer was formed by depositing 10 μm of palladium as a catalyst on a silicon substrate by a sputtering method. Then, copper was deposited on the catalyst layer as a protective layer by a sputtering method to a thickness of 50 μm.

Next, a dry film resist was thermocompression-bonded and laminated on the protective layer, then selectively exposed to ultraviolet rays and developed in a sodium carbonate solution to remove the resist other than the circuit pattern. .

Then, by immersing in a nitric acid solution,
The copper protective layer and the catalyst layer were removed, and then the substrate was dipped in a sodium hydroxide solution to remove the remaining resist. Finally, platinum was deposited by electroless plating.

When a defect inspection was performed on the wiring board manufactured by the above steps, it was confirmed that the wiring board manufactured by this embodiment also had good quality without defects such as disconnection.

[0038]

As described above, according to the two wiring pattern forming methods of the present invention, even if a material having a high corrosion resistance that is difficult to etch, such as platinum or a platinum alloy, is used as the wiring material, the efficiency is high. The wiring pattern can be formed effectively. INDUSTRIAL APPLICABILITY The present invention can expand the range of application of circuit board materials, and can realize a higher performance electronic circuit.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a first new wiring pattern forming method which is the basis of the present invention.

FIG. 2 is a diagram schematically showing a second new wiring pattern forming method which is the basis of the present invention.

FIG. 3 is a diagram schematically showing a first new wiring pattern forming method according to the present invention.

FIG. 4 is a diagram schematically showing a second new wiring pattern forming method according to the present invention.

FIG. 5 is a diagram schematically showing an example of a conventional wiring pattern forming method by an additive method.

FIG. 6 is a diagram schematically showing a wiring pattern forming method by an additive method in consideration of a wiring material.

[Explanation of symbols]

1 substrate 2 catalyst layer 3 wiring material 4 resist 5 protective layer

Claims (4)

[Claims] 1. A method for forming a wiring pattern on a substrate, which comprises the following steps. (A) A step of removing a resist on a predetermined wiring pattern by applying a resist on a substrate and exposing and developing the resist. (B) A step of forming a catalyst layer on the surface of the substrate. (C) A step of forming a protective layer on the catalyst layer. (D) A step of removing the resist remaining in the area other than the wiring pattern. (E) A step of removing the protective layer. (F) A step of forming a thin film made of a wiring material by electroless plating. 2. A method for forming a wiring pattern on a substrate, which comprises the following steps. (A) A step of forming a catalyst layer on the surface of the substrate. (B) A step of forming a protective layer on the catalyst layer. (C) A step of applying a resist on a substrate, exposing and developing the resist to remove the resist so that the resist on a predetermined wiring pattern remains. (D) A step of removing the protective layer and the catalyst layer. (E) A step of removing the resist on the wiring pattern. (F) A step of removing the protective layer. (G) A step of forming a thin film made of a wiring material by electroless plating. 3. Ti, Cr, Fe, C as a protective layer
The wiring pattern forming method according to claim 1 or 2, wherein a film of o, Ni, Cu, Ag, Au, Sn, In, or an oxide, carbide, or nitride thereof is formed. 4. The wiring pattern forming method according to claim 1, wherein the protective layer is formed by a sputtering method, an electroplating method, or an electroless plating method.