JPH0974226A - Peltier element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the Peltier element favorable in respect to the durability and cost capable of achieving high cooling efficiency meeting various radiating requirements. SOLUTION: Within the Peltier element fitted with an electrode 1 on the opposite surface of a Peltier material (chip), a layer in the electric conductivity degree and thermal conductivity level lower than those of a chip 4 is provided to the part close to the electrode in contact electric resistance and contact thermal resistance higher than those of the chip 4 is provided in the other electrode junction regions between the electrode and the chip 4 so that these layers may be arranged in almost symmetrical positions to the central part of the chip 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Peltier element used in an air conditioning system, a cold insulation / heat insulation system, local cooling, precision cooling and the like, and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a structure of a Peltier device, for example, Japanese Patent Laid-Open No. 6-169108 is known as a known technique.
For the chip, a molten material obtained by melting and solidifying a raw material or a sintered material obtained by firing raw material powder is used.

In general, in the case of Peltier cooling, if the heat radiation condition around the element is bad, the temperature of the entire element rises due to Joule heat generated inside the element. As a countermeasure against this, it is conceivable to use an element having a large shape factor (chip length through which current / heat flow passes / cross-sectional area of chip through which current / heat flow passes). This is because when the form factor is increased, the amount of heat radiation required by the chip at the time of maximum efficiency is reduced, and a predetermined cooling temperature can be achieved under limited heat radiation conditions.

[0004]

Since the material (chip) of the Peltier device generally has a fragile property, if the device or module is composed of a long and thin chip as in the known example, it may be damaged by impact. There are many. Further, at present, since the yield in manufacturing long and thin chips is not good, many chips are rectangular parallelepiped (generally cubic).
On the other hand, an element having a large form factor is desirable in order to achieve a predetermined capability (efficiency) of the element under the condition that the heat radiation amount is limited, but the element is damaged due to the lengthening of the chip and the cost is increased due to the poor yield. There was a problem. Also, the electrode
From the viewpoint of preventing damage to the chip joint portion, a long element in which the joint area cannot be increased is disadvantageous. Like this
With the conventional element structure, in terms of performance, durability and cost,
It was not possible to meet all the requirements for the device.

The cooling by the Peltier device is expected to be used in a wide range of applications in accordance with the non-CFC society information, and the original performance of the device can be sufficiently brought out under various (heat dissipation) conditions, and the durability is improved. There is a great need for devices that are excellent and cost effective. The first object of the present invention is to achieve high cooling efficiency under various (heat dissipation) conditions,
It is to provide an element that is advantageous in terms of durability and cost.

A second object of the present invention is to provide a means for manufacturing a device which can achieve high cooling efficiency under various (heat dissipation) conditions and is advantageous in terms of durability and cost.

[0007]

The first means (first invention) for solving the above-mentioned first problem is a Peltier element in which electrodes are mounted on opposite surfaces of a Peltier material (chip). A layer with lower electrical and thermal conductivity than the chip is provided in the vicinity of the chip, or a layer with higher electrical contact resistance and thermal contact to the chip is provided between the electrode and the chip compared to other electrode bonding areas. That is, these layers provided on the facing surfaces are arranged in substantially symmetrical positions with respect to the center of the chip.

A second means (second invention) for solving the above-mentioned first problem is a Peltier element in which electrodes are mounted on the same surface of a Peltier material (chip), and a portion closer to the electrodes than the chip is mounted. Also has a layer with low electrical and thermal conductivity, and an electrode is provided at a position approximately symmetrical to a straight line passing through the center of this layer, or contact between the electrode and the chip compared to other electrode bonding areas A layer having high electrical resistance and contact thermal resistance is provided, and these layers provided on the same plane are arranged at positions substantially symmetrical with respect to a straight line passing through the center of the chip.

A third means (third invention) for solving the first problem is a Seebeck coefficient α and an electric conductivity σ.
Alternatively, the output factor (α
² σ), or the figure of merit (α ² σ / κ), shows that the crystal orientation of a chip with a specific crystal orientation is excellent, and the electrical conductivity and thermal conductivity of the bonding material provided between the chip and the electrode are relatively high. This is to make it substantially coincide with the direction connecting the centers of the high parts or the direction connecting the centers of the parts where the contact electric resistance and the contact thermal resistance to the chip are relatively low.

A fourth means (fourth invention) for solving the first problem is the p-type addition of a layer having low electric conductivity or thermal conductivity in the first and second inventions. Thing and n
It is composed of a material containing both mold additives.

A fifth means (fifth invention) for solving the above-mentioned first problem is that, in the first and second inventions, a layer having a low electric conductivity or a low heat conductivity is made lighter. It is composed of a material containing an element.

A sixth means (sixth invention) for solving the above-mentioned first problem is that, in the above-mentioned first invention and second invention, a layer having low electric conductivity or thermal conductivity is formed on a chip. It is composed of a material that has almost the same composition as that of, and has a lower density than the chip.

The first means (seventh invention) for solving the above-mentioned second problem is a method of manufacturing a Peltier element in which electrodes are mounted on opposite surfaces of a Peltier material (chip), and the electrodes are arranged close to each other. A layer having a lower electrical conductivity and a lower thermal conductivity than the chip is provided in the part, or a layer having a higher contact electric resistance and a higher thermal contact resistance to the chip than the other electrode bonding area is provided between the electrodes and the chip to face each other. It is to arrange these layers provided on the surface in a position substantially symmetrical with respect to the center of the chip.

A second means (eighth invention) for solving the above-mentioned second problem is a Peltier element in which electrodes are mounted on the same surface of a Peltier material (chip). Also has a layer with low electrical and thermal conductivity, and an electrode is provided at a position approximately symmetrical with respect to a straight line passing through the center of this layer, or the contact electric power to the chip is increased between the electrode and the chip compared to other bonding areas. A layer having a high resistance and a high contact thermal resistance is provided, and these layers provided on the same plane are arranged in a substantially symmetrical position with respect to a straight line passing through the center of the chip.

A third means (9th invention) for solving the above-mentioned second problem is the above-mentioned 7th invention and 8th invention, wherein heat treatment is performed in a gas atmosphere containing a light element, and heat treatment is performed. That is, a part of the altered layer is removed to form a layer having low electric conductivity or thermal conductivity.

[0016]

The operation of the first invention will be described with reference to FIG. In the present invention, as shown in FIG. 1, a bonding material 2 and a layer having low electric conductivity and thermal conductivity (modified layer 3) are provided between the electrode 1 and the chip 4.
Are provided substantially symmetrically with respect to the center of the chip. After passing through the electrode 1 and the bonding material 2, electricity flows into the chip 4 while avoiding the modified layer 3. Therefore, the current in the chip 4 is mainly composed of the components from the lower left to the upper right of the chip of FIG. 1, and the current density is highest near the diagonal line. This is effectively the same as making the current path narrow and long. On the other hand, since the reformed layer 3 also has low thermal conductivity, the electrode 1 and the tip 4
Insulate between and. Therefore, the effective passage for the heat flow is narrow and long. In this way, by providing the modified layer, the same effect as increasing the form factor of the rectangular parallelepiped chip can be obtained, and the amount of heat radiation required by the element when operating at the maximum efficiency point is reduced, and the predetermined performance can be obtained. Can be achieved.

FIG. 2 is a diagram showing the relationship between the length of the modified layer obtained under the conditions of Table 1, the maximum coefficient of performance (COP) at each length, and the amount of heat radiation at that time.

[0018]

[Table 1]

From this figure, it can be seen that even if the same chip is used, if the length of the modified layer is changed, the heat radiation amount can be lowered while maintaining the maximum coefficient of performance (about 0.95) of the device. Further, as shown in Table 1, since the element is composed of cubic chips, the yield at the time of chip manufacturing is good and the cost is advantageous. Further, since the electrodes are bonded over the entire area of the two surfaces of the chip (including the modified layer), the stress generated by an external impact or the like is small. Therefore, the possibility of breakage at the joint is small.

On the other hand, as shown in FIG. 3, even if the bonding material 2a having a large contact thermal resistance and contact electric resistance with respect to the chip and the bonding material 2b having a small contact resistance are formed between the electrode 1 and the chip 4, the current,
The cross-sectional area that the heat flow crosses can be effectively reduced. Therefore,
In this case, the same effect can be expected in terms of performance. In addition, since the electrodes are bonded over the entire surface of the bonding portion between the electrode 1 and the chip 4, the possibility of breakage is small, and the device can be formed using chips with high yield, which is advantageous in terms of cost.

The operation of the second invention will be described with reference to FIG. FIG. 4 shows a Peltier element of the type in which electrodes are mounted on the same surface. A reforming layer 3 is provided on the side of the chip on which the electrode 1 is mounted, and a straight line passing through the center of this layer (in the case of FIG. 4, a vertical line). 2), the electrode 1 is provided at a substantially symmetrical position with the bonding material 2 interposed therebetween. In the configuration of FIG. 4 as well, the paths for current and heat flow are narrow and long. For example, in the case of an electric current, the electric current passes by avoiding the bonding material 3 having a high resistance.
Then, through the bonding material 2, it flows once upward in the right direction into the chip 4, then flows downward in the right direction, and then flows into the electrode 1 on the right side. Further, since the reformed layer 3 also has a low thermal conductivity, a flow similar to an electric current occurs even in the heat flow. Therefore, similar to the first invention, the same effect as when the shape factor is increased with the rectangular parallelepiped chip is obtained, and the possibility of breakage of the joint portion is small for the same reason as in the first invention, which is advantageous in cost. is there.

Further, in the second invention, even if the bonding material 2a having a large contact thermal resistance and contact electrical resistance and the bonding material 2b having a small contact resistance as shown in FIG. Can be effectively narrowed and lengthened, and the same effect can be obtained.

When the crystal orientation of the Peltier material exhibiting excellent characteristics in a specific crystal orientation is made to coincide with the orientation connecting the centers of the electrodes mounted on the opposite surfaces, most of the electric current and heat flow have relatively high conductivity. It flows in the direction connecting the centers of the higher layers. Therefore, as in the third aspect of the present invention, if these flow directions are made to coincide with the chip orientation showing excellent thermoelectric characteristics, the cooling capacity that can be achieved by the Peltier element becomes higher than in the case where they do not coincide. . Further, as shown in FIG. 6, even when the electrode 1 is mounted on the chip 4 by the bonding material 2a having a large contact thermal resistance and contact electric resistance and the bonding material 2b having a small contact resistance, the flow direction of the current and the heat flow (two It is possible to match the direction in which the center of the bonding material 2b is connected) with the chip orientation that exhibits excellent thermoelectric characteristics. Further, also in the present invention, as in the first and second inventions, the possibility of damage to the bonding portion is small, and the element can be formed using a chip with a high yield, which is also advantageous in terms of cost.

When the p-type additive and the n-type additive are mixed in the Peltier device, the impurity level formed by them acts as a trap level for electrons and holes. As a result, the concentration of carriers (electrons or holes) decreases. In addition, since the additive acts as a scattering center for carriers, the mobility decreases. Due to this decrease in carrier concentration and decrease in mobility, the electric conductivity of the layer in which the p-type additive and the n-type additive are mixed is low. On the other hand, the same thing occurs in the thermal conductivity, and when an additive is added to cancel the polarity of the chip, strains, defects and the like caused by the presence of the additive increase, and the thermal conductivity decreases. In this way, if a layer having low electrical conductivity and thermal conductivity is formed between the electrode and the chip, the same effect as increasing the form factor can be obtained for the reasons already described.
High performance characteristics can be obtained even when there are restrictions on heat dissipation conditions. Further, the amount of the additive mixed to erase the polarity of the chip is several%. The goodness of bonding of the electrode and the chip is almost determined by the combination of the base material of the chip and the bonding material,
It is rarely affected by a few% of additives. Therefore, the mechanical strength does not change, and the possibility of breakage of the joint is small. Further, as in the case of other inventions, elements can be formed using chips with high yield, which is advantageous in terms of cost.

According to the fifth invention, a layer having low electric conductivity and low thermal conductivity can be formed in the same manner as in the fourth invention. For example, when a few percent of oxygen is mixed into a Bi-Te-based material known as a Peltier material, the electric conductivity decreases by one digit or more, and the thermal conductivity also decreases to a fraction. Therefore, according to the present invention as well, it is possible to increase the form factor of the device and obtain high performance characteristics.

Also in the sixth aspect of the invention, since the low-density layer formed on the chip has low electric conductivity and low thermal conductivity, it is possible to increase the form factor of the element and obtain high-performance characteristics. In addition, since the main component of this layer is the same as that of the chip and the difference in mechanical strength from other parts is small, the possibility of breakage of the joint is small.

According to the seventh invention, as in the first invention shown in FIGS. 1 and 3, a layer having a low electrical conductivity and a low thermal conductivity is provided between the electrode and the chip, which has already been described. For the reason described above, it is possible to manufacture an element which has high performance, is less likely to be damaged, and is advantageous in terms of cost. According to the eighth invention, a layer having a low electrical conductivity and a low thermal conductivity is provided between the electrode and the chip as in the second invention shown in FIGS. 4 and 5, for the reasons already explained. It is possible to fabricate a device that has high performance, is less likely to be damaged, and is advantageous in terms of cost. According to the ninth aspect, by heat-treating the chip in a gas atmosphere containing a light element, a reformed layer having low electric conductivity and thermal conductivity can be formed, so that the device can have high performance.

[0028]

An embodiment of the present invention will be described with reference to FIG. The chip 4 is made of a Bi-Te based material, and the electrode 1 is made of a copper plate, an aluminum plate or a metal plate containing these elements as a main component. The plate thickness was set to 0.5 mm to 1.0 mm, and the bonding material 2 was a solidified paste of Sn—Pb based alloy (solder) or Ag. Chip 4 is 1
A cube having a side of 5 mm (including the reforming layer 3) was formed, and the reforming layer 3 was formed by mixing about 5 atom% of oxygen into the chip. The modified layer 3 has a width of 3 mm in the horizontal direction of FIG. 1, a thickness (length in the vertical direction of FIG. 1) of about 0.1 mm, and a depth direction of 5 mm, which is the same as the chip. With this configuration, the joint area between the electrode 1 and the chip 4 is effectively narrowed to about 2/5, and the current / heat flow path changes according to the principle already described.

When the amount of heat radiation is required to be 0.1 W or less per chip due to the restrictions on the usage conditions of the device, the coefficient of performance (C
OP) is 0.73 at the maximum, but in the case of the element of FIG. 1, the COP was about 0.95 with any combination of the electrode material and the bonding material. Further, since these elements have a cubic structure, they have excellent impact resistance and are easy to mass-produce, which is advantageous in terms of cost. Further, as in the case of the rectangular parallelepiped element, the electrode and the chip can be bonded over the entire surface, so that the bonded portion is strong against external impact.

Another embodiment of the present invention will be described with reference to FIG. This is an embodiment in which the electrodes are mounted on the chip 4 by using the bonding material 2a and the bonding material 2b, and the path of the current / heat flow is changed by the bonding material 2a having a large contact resistance to the chip. The bonding material 2a was a Sn-Pb based alloy, a bonding material containing Ag as a main component, and 2b was a solidified paste containing Ni and graphite as main components. Sn
The contact electric resistance of a Pb-based alloy or a bonding material containing Ag as a main component is about 20 μΩcm ² , and a contact electric resistance lower by 2 to 3 orders of magnitude than that of a main component containing Ni or graphite. Contact thermal resistance is also about an order of magnitude lower. The resistance of the chip is about 2 × 10 ^-3 Ω, and the contact resistance of the bonding material 2a is 4 ×.
It can be almost ignored because it is about 10 ⁻⁵ Ω, but Ni,
A material containing graphite as a main component has a contact electric resistance of two digits or more, which is higher than that of a chip.
Therefore, most of the electricity flows into the chip through the bonding material 2b. The same flow qualitatively occurs even with heat, and by these, a high COP can be achieved even in a place where the amount of heat radiation is small.
Further, in terms of impact resistance and cost, there was almost the same effect as the above-mentioned embodiment.

An embodiment of the present invention (second invention) will be described with reference to FIG. Also in the second invention, the basic material is the same as that of the embodiment of FIG. 1, a Bi-Te based material is used for the chip, and the electrode 1 is a copper plate, an aluminum plate or a metal plate containing these elements as a main component. Was used. The plate thickness is 0.5 mm to 1.0 mm, and Sn-Pb alloy (solder) or A is used as the bonding material.
A solidified paste containing g as a main component was used.
The chip was 5 mm on a side (including the modified layer), and oxygen was mixed into the chip at about 5 atomic% to form the Bi-Te-based modified layer 3. The modified layer 3 is 3 m in the horizontal direction of FIG.
m, thickness (vertical length in FIG. 1) is about 0.1 mm, and depth is 5 mm, which is the same as the chip. With this configuration, the joint area between the electrode and the chip is effectively narrowed to about 1/5, and the current / heat flow path changes according to the principle already described. In the case of this device, the COP was about 0.95 in the region where the heat radiation amount was 0.05 W or less. A modified example of the present invention is shown in FIG. 5, in which the bonding material 2b is a Sn—Pb alloy, a bonding material containing Ag as a main component, and 2a is a solidified paste containing Ni and graphite as main components. Using. Also in this case, most of electricity and heat flow into the chip through the bonding material 2b, so that a high COP can be achieved even in a place with a small amount of heat radiation. Further, in terms of impact resistance and cost, there was almost the same effect as the above-mentioned embodiment.

An embodiment of the third invention will be described with reference to FIG. In the case of the Bi-Te-based material, the a-axis direction is known as a direction having relatively excellent thermoelectric characteristics (output factor, figure of merit). In the present invention, the a-axis is aligned with the line connecting the middles of the bonding materials 2b having relatively low contact electric resistance and contact thermal resistance. For the reason described above, in the case of FIG. 6, most of the electric current / heat flow is on the line connecting the joining materials 2b, that is, Bi-
A high COP could be achieved because the Te crystals flow in the direction of excellent thermoelectric properties. In addition, the effect of effectively increasing the shape factor has made it possible to use it in a place where sufficient heat radiation cannot be obtained. Next, an embodiment of the fourth invention will be described. B
The p-type additive of the i-Te-based material generally includes Sb, Ti,
Pb, Cd, etc. are used, and the n-type additive is Ag, Se,
I, Cu or the like is used. Here, Sb is 1.5 atomic%
The added chips were mixed with 1.0 atomic% of Ag, and
When the modified layer 3 of FIG. 3 is formed, the additives (impurity levels) work as trap centers for carriers (electrons or holes) with each other, so that the electric conductivity decreases by two digits or more, and the presence of the additives The generated strains and defects increased, and as a result, the thermal conductivity also decreased by 20 to 50%. Even in this case, if a layer having low electrical conductivity and thermal conductivity is formed between the electrode and the chip, the same effect as increasing the form factor can be obtained for the reason already described, and the heat dissipation condition is restricted. However, high performance characteristics were obtained. In addition, since there is no change in mechanical strength, the possibility of damage to the joint is small, and as with other inventions, elements can be formed using chips with high yield, which is advantageous in terms of cost.

The fifth invention is also basically based on the structure shown in FIGS. 1 and 3, and the modified layer 3 is formed by mixing light elements such as oxygen, nitrogen, and carbon into a Bi-Te-based material to form a Bi-Te-based material. Form oxides, nitrides, and carbides of the elements that make up the Te-based material. Here, as a result of mixing about 5 atom% of oxygen into a part of the Bi-Te material, a layer having a low electric conductivity of two digits or more could be formed. On the other hand, since the thermal conductivity was also reduced by 20 to 50%, the same effect as increasing the form factor was obtained for the reasons already described, and high performance characteristics were obtained even when the heat dissipation conditions were restricted.

The sixth invention is also basically based on the structure shown in FIGS. 1 and 3, and the modified layer 3 is formed by using a low density Bi-Te based material. In the case of the Bi-Te sintered body chip, the one having a sintered density of less than 60% has a low electric conductivity of about one digit. On the other hand, since the thermal conductivity is also reduced by about 20 to 50%, the same effect as increasing the shape factor is obtained for the reasons already described, and high performance characteristics are obtained even when the heat radiation conditions are limited. .

An embodiment of the seventh invention will be described with reference to FIG. First, a Bi-Te-based material is used for the chip 4,
For example, a p-type additive (for example, Sb, T
i, Pb, Cd, etc.) and apply at 400 ℃
Heat treatment was performed at ˜500 ° C. to diffuse the p-type additive in the chip. Next, the electrode 1 was attached using a Sn-Pb alloy (solder) or a paste containing Ag as a main component as the bonding material 2. Further, as shown in FIG. 8, the bonding material 2a and the bonding material 2b were sequentially applied to the chip 4 and the electrode 1 was attached. Bonding material 2
As a, Sn-Pb type alloy, A
A bonding material containing g as a main component is used, and 2b is Ni,
A solidified paste containing graphite as the main component was used. In both cases of FIG. 7 and FIG. 8, a high COP can be achieved even if there are restrictions on the use conditions of the element, and since it has a cubic structure, it has impact resistance and is easy to mass-produce, which is advantageous in terms of cost. The device could be manufactured.

FIG. 9 shows an eighth embodiment of the invention, and like the embodiment of FIG. 7, Bi is used as the Peltier material (chip 4).
A powder containing a p-type additive was applied to the n-type chip using a -Te-based material and heat-treated at 400 ° C to 500 ° C to diffuse the p-type additive into the chip. Then Sn-P
The electrode 1 was attached using a b-based alloy (solder) or a paste containing Ag as a main component as the bonding material 2. Also in this case, electricity and heat pass through avoiding the reforming layer 3, and as a result, the shape factor can be effectively increased, so that a high COP can be achieved even in a place with a small amount of heat radiation. Further, in terms of impact resistance and cost, the same effects as the other examples were obtained.

FIG. 10 shows an embodiment of the ninth invention, in which the chip 4 is heated in an oxygen gas atmosphere for several tens of minutes to form the modified layer 3 on the entire chip, and then the modified layer 3 is formed. Was removed leaving a part thereof, and the bonding material 2 was applied thereon to form the electrode 1. In the case of this method, the same effect as other methods was obtained.

[0038]

According to the present invention, a high cooling efficiency can be achieved under various (heat dissipation) conditions, and an element advantageous in terms of durability and cost can be constructed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a basic configuration of a first invention (when a layer having low conductivity is provided).

FIG. 2 is an explanatory diagram showing the relationship between the length of the modified layer and the efficiency and the amount of heat radiation.

FIG. 3 First invention (when a layer having high contact resistance is provided)
Sectional drawing which shows the basic composition of.

FIG. 4 is a cross-sectional view showing the basic structure of the second invention (when a layer having low conductivity is provided).

FIG. 5: Second invention (when a layer having high contact resistance is provided)
Sectional drawing which shows the basic composition of.

FIG. 6 is a sectional view showing an embodiment of the third invention.

FIG. 7 is a sectional view showing an embodiment of the seventh invention.

FIG. 8 is a sectional view showing an embodiment of the seventh invention.

FIG. 9 is a sectional view showing an embodiment of the eighth invention.

FIG. 10 is an explanatory view showing an embodiment of the ninth invention.

[Explanation of symbols]

1 ... Power source, 2 ... Bonding material, 2a ... Bonding material (a), 2b ... Bonding material (b), 3 ... Modified layer, 4 ... Chip.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tomio Ishida 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (9)

[Claims] 1. In a Peltier element having electrodes mounted on opposite surfaces of a chip, a layer having lower electrical conductivity and thermal conductivity than that of the chip is provided at a portion adjacent to the electrode, or the Peltier element of the electrode and the chip are provided. Layers having high contact electric resistance and contact thermal resistance with respect to the chip as compared with other electrode bonding areas are provided between them, and these layers provided on the facing surface are arranged at substantially symmetrical positions with respect to the center of the chip. Is a Peltier element. 2. In a Peltier device having electrodes mounted on the same surface of a chip, a layer having lower electrical conductivity and thermal conductivity than that of the chip is provided in a portion close to the electrodes, and a straight line passing through the center of this layer is provided. The electrodes in a substantially symmetrical position, or a layer having a higher contact electric resistance and contact thermal resistance with respect to the chip than other electrode bonding areas is provided in a part between the electrode and the chip, and the electrodes are provided on the same surface. A Peltier device characterized in that these provided layers are arranged in substantially symmetrical positions with respect to a straight line passing through the center of the chip. 3. The output factor (α ² σ) or figure of merit (α ² σ / κ) defined by the Seebeck coefficient α, electrical conductivity σ or thermal conductivity κ according to claim 1, is a specific crystal orientation. In the direction of connecting the centers of the portions of the bonding material provided between the chip and the electrode having relatively high electric conductivity and thermal conductivity, or the contact electric resistance and the contact heat to the chip. A Peltier element that is roughly aligned with the direction connecting the centers of the parts where the resistance is relatively low. 4. The Peltier device according to claim 1, wherein the layer having low electrical conductivity or thermal conductivity is made of a material containing both a p-type additive and an n-type additive. 5. A Peltier device according to claim 1, wherein the layer having low electrical conductivity or thermal conductivity is made of a material containing a light element. 6. The layer according to claim 1, wherein the layer having low electrical conductivity or thermal conductivity has a component substantially similar to that of the chip and is made of a material having a lower density than the chip. 7. A method for manufacturing a Peltier device having electrodes mounted on opposite surfaces of a chip, wherein a layer having lower electric and thermal conductivity than that of the chip is provided in a portion close to the electrode, or the electrode and the chip are provided. Layers having high contact electric resistance and contact thermal resistance with respect to the chip as compared with other electrode bonding regions are provided between the layers, and these layers provided on the opposite surfaces are arranged at substantially symmetrical positions with respect to the center of the chip. A method of manufacturing a Peltier device, characterized in that 8. In a Peltier device having electrodes mounted on the same surface of a chip, a layer having lower electrical conductivity and thermal conductivity than the chip is provided in a portion close to the electrodes, and a straight line passing through the center of this layer is provided. These electrodes are provided on substantially the same plane, or a layer having higher contact electric resistance and contact thermal resistance with respect to the chip as compared with other electrode bonding areas is provided between the electrode and the chip, and these layers are provided on the same surface. Is placed in a substantially symmetrical position with respect to a straight line passing through the center of the chip. 9. A Peltier element according to claim 7 or 8, which is heat-treated in a gas atmosphere containing a light element to remove a part of the layer altered by the heat treatment to form a layer having low electric conductivity and thermal conductivity. Production method.