JPH0974226A - Peltier element and its manufacture - Google Patents
Peltier element and its manufactureInfo
- Publication number
- JPH0974226A JPH0974226A JP7229880A JP22988095A JPH0974226A JP H0974226 A JPH0974226 A JP H0974226A JP 7229880 A JP7229880 A JP 7229880A JP 22988095 A JP22988095 A JP 22988095A JP H0974226 A JPH0974226 A JP H0974226A
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- Prior art keywords
- chip
- layer
- electrode
- thermal conductivity
- conductivity
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は空調システム，保冷・保
温システム，局所冷却，精密冷却等で使われる、ペルチ
ェ素子とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Peltier element used in an air conditioning system, a cold insulation / heat insulation system, local cooling, precision cooling and the like, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】ペルチェ素子の構造として、例えば、特
開平6−169108 号公報が公知技術として知られており、
チップは原料を溶融・凝固して得られる溶製材もしくは
原料粉体を焼成して得られる焼結材が用いられる。2. Description of the Related Art As a structure of a Peltier device, for example, Japanese Patent Laid-Open No. 6-169108 is known as a known technique.
For the chip, a molten material obtained by melting and solidifying a raw material or a sintered material obtained by firing raw material powder is used.
【０００３】一般に、ペルチェ冷却の場合、素子周辺の
放熱条件が悪いと、素子内部で生じるジュール発熱によ
って素子全体の温度が上昇する。この対策として、形状
因子（電流・熱流の通過するチップ長さ／電流・熱流の
通過するチップの断面積）の大きな素子を用いることが
考えられる。これは、形状因子を大きくすると、最大効
率時にチップが必要とする放熱量が少なくなり、限られ
た放熱条件下において所定の冷却温度を達成できること
による。In general, in the case of Peltier cooling, if the heat radiation condition around the element is bad, the temperature of the entire element rises due to Joule heat generated inside the element. As a countermeasure against this, it is conceivable to use an element having a large shape factor (chip length through which current / heat flow passes / cross-sectional area of chip through which current / heat flow passes). This is because when the form factor is increased, the amount of heat radiation required by the chip at the time of maximum efficiency is reduced, and a predetermined cooling temperature can be achieved under limited heat radiation conditions.
【０００４】[0004]
【発明が解決しようとする課題】ペルチェ素子の材料
（チップ）は、一般にもろい性質を有しているため、公
知例の様な長細いチップで素子あるいはモジュールを構
成すると、衝撃による破損の可能性が少なくない。また
現状では、長細いチップを製造する際の歩留まりが良く
ないため、チップは直方体（概略立方体）の物が多い。
一方、放熱量が限定された条件下で素子に所定の能力
（効率）を達成させるには、形状因子の大きな素子が望
ましいが、チップの長尺化による素子破損，歩留まりの
悪さによるコストアップの問題があった。また、電極−
チップ接合部の破損防止の観点から考えると、接合面積
を大きくできない長尺の素子は不利である。この様に、
従来の素子構造で、性能，耐久性およびコストの面で、
素子に対する要求を全て満たすことはできなかった。Since the material (chip) of the Peltier device generally has a fragile property, if the device or module is composed of a long and thin chip as in the known example, it may be damaged by impact. There are many. Further, at present, since the yield in manufacturing long and thin chips is not good, many chips are rectangular parallelepiped (generally cubic).
On the other hand, an element having a large form factor is desirable in order to achieve a predetermined capability (efficiency) of the element under the condition that the heat radiation amount is limited, but the element is damaged due to the lengthening of the chip and the cost is increased due to the poor yield. There was a problem. Also, the electrode
From the viewpoint of preventing damage to the chip joint portion, a long element in which the joint area cannot be increased is disadvantageous. Like this
With the conventional element structure, in terms of performance, durability and cost,
It was not possible to meet all the requirements for the device.
【０００５】ペルチェ素子による冷却は、ノンフロン化
の社会情報に応じて、幅広い用途での利用が期待されて
おり、さまざまな（放熱）条件下で素子本来の性能を十
分に引き出せ、かつ耐久性に優れ、コスト的にも有利な
素子に対するニーズは高い。本発明の第１の目的は、さ
まざまな（放熱）条件下で、高い冷却効率を達成でき、
耐久性，コストの面でも有利な素子を提供することにあ
る。The cooling by the Peltier device is expected to be used in a wide range of applications in accordance with the non-CFC society information, and the original performance of the device can be sufficiently brought out under various (heat dissipation) conditions, and the durability is improved. There is a great need for devices that are excellent and cost effective. The first object of the present invention is to achieve high cooling efficiency under various (heat dissipation) conditions,
It is to provide an element that is advantageous in terms of durability and cost.
【０００６】本発明の第２の目的は、さまざまな（放
熱）条件下で高い冷却効率を達成でき、耐久性，コスト
の面でも有利な素子を製造する手段を提供することにあ
る。A second object of the present invention is to provide a means for manufacturing a device which can achieve high cooling efficiency under various (heat dissipation) conditions and is advantageous in terms of durability and cost.
【０００７】[0007]
【課題を解決するための手段】上記第１の課題を解決す
るための第１の手段（第１の発明）は、ペルチェ材料
（チップ）の対向する面に電極を装着したペルチェ素子
で、電極の近接した部分にチップよりも電気伝導度およ
び熱伝導度の低い層を設けるか、電極とチップの間に他
の電極接合領域に比べてチップに対する接触電気抵抗お
よび接触熱抵抗の高い層を設け、対向する面に設けたこ
れらの層をチップの中心に対して概略対称位置に配置す
ることである。The first means (first invention) for solving the above-mentioned first problem is a Peltier element in which electrodes are mounted on opposite surfaces of a Peltier material (chip). A layer with lower electrical and thermal conductivity than the chip is provided in the vicinity of the chip, or a layer with higher electrical contact resistance and thermal contact to the chip is provided between the electrode and the chip compared to other electrode bonding areas. That is, these layers provided on the facing surfaces are arranged in substantially symmetrical positions with respect to the center of the chip.
【０００８】上記第１の課題を解決するための第２の手
段（第２の発明）は、ペルチェ材料（チップ）の同一面
に電極を装着したペルチェ素子で、電極の近接する部分
にチップよりも電気伝導度および熱伝導度の低い層を設
け、この層の中心を通る直線に対してほぼ対称位置に電
極を設けるか、電極とチップの間に他の電極接合領域に
比べてチップに対する接触電気抵抗および接触熱抵抗の
高い層を設け、同一面上に設けたこれらの層をチップの
中心を通る直線に対して概略対称位置に配置することで
ある。A second means (second invention) for solving the above-mentioned first problem is a Peltier element in which electrodes are mounted on the same surface of a Peltier material (chip), and a portion closer to the electrodes than the chip is mounted. Also has a layer with low electrical and thermal conductivity, and an electrode is provided at a position approximately symmetrical to a straight line passing through the center of this layer, or contact between the electrode and the chip compared to other electrode bonding areas A layer having high electrical resistance and contact thermal resistance is provided, and these layers provided on the same plane are arranged at positions substantially symmetrical with respect to a straight line passing through the center of the chip.
【０００９】上記第１の課題を解決するための第３の手
段（第３の発明）は、ゼーベック係数α，電気伝導度σ
あるいは熱伝導度κにより定義される出力因子(α
2σ）、もしくは性能指数(α2σ／κ）が、特定の結晶
方位で優れたチップの結晶方位を、チップと電極間に設
けた接合材の電気伝導度および熱伝導度が相対的に高い
部分の中心を結ぶ方向、あるいはチップに対する接触電
気抵抗および接触熱抵抗が相対的に低い部分の中心を結
ぶ方向と概略一致させることである。A third means (third invention) for solving the first problem is a Seebeck coefficient α and an electric conductivity σ.
Alternatively, the output factor (α
2 σ), or the figure of merit (α 2 σ / κ), shows that the crystal orientation of a chip with a specific crystal orientation is excellent, and the electrical conductivity and thermal conductivity of the bonding material provided between the chip and the electrode are relatively high. This is to make it substantially coincide with the direction connecting the centers of the high parts or the direction connecting the centers of the parts where the contact electric resistance and the contact thermal resistance to the chip are relatively low.
【００１０】上記第１の課題を解決するための第４の手
段（第４の発明）は、上記第１および第２の発明で、電
気伝導度もしくは熱伝導度の低い層を、ｐ型添加物とｎ
型添加物の両方を含む材料により構成することである。A fourth means (fourth invention) for solving the first problem is the p-type addition of a layer having low electric conductivity or thermal conductivity in the first and second inventions. Thing and n
It is composed of a material containing both mold additives.
【００１１】上記第１の課題を解決するための第５の手
段（第５の発明）は、上記第１の発明および第２の発明
で、電気伝導度もしくは熱伝導度の低い層を、軽元素を
含む材料により構成することである。A fifth means (fifth invention) for solving the above-mentioned first problem is that, in the first and second inventions, a layer having a low electric conductivity or a low heat conductivity is made lighter. It is composed of a material containing an element.
【００１２】上記第１の課題を解決するための第６の手
段（第６の発明）は、上記第１の発明および第２の発明
で、電気伝導度もしくは熱伝導度の低い層を、チップと
ほぼ同様の成分を有し、チップに比べ密度の低い材料で
構成することである。A sixth means (sixth invention) for solving the above-mentioned first problem is that, in the above-mentioned first invention and second invention, a layer having low electric conductivity or thermal conductivity is formed on a chip. It is composed of a material that has almost the same composition as that of, and has a lower density than the chip.
【００１３】上記第２の課題を解決するための第１の手
段（第７の発明）は、ペルチェ材料（チップ）の対向す
る面に電極を装着したペルチェ素子の製造法で、電極の
近接した部分にチップよりも電気伝導度および熱伝導度
の低い層を設けるか、電極とチップの間に他の電極接合
領域に比べてチップに対する接触電気抵抗および接触熱
抵抗の高い層を設け、対向する面に設けたこれらの層を
チップの中心に対して概略対称位置に配置することであ
る。The first means (seventh invention) for solving the above-mentioned second problem is a method of manufacturing a Peltier element in which electrodes are mounted on opposite surfaces of a Peltier material (chip), and the electrodes are arranged close to each other. A layer having a lower electrical conductivity and a lower thermal conductivity than the chip is provided in the part, or a layer having a higher contact electric resistance and a higher thermal contact resistance to the chip than the other electrode bonding area is provided between the electrodes and the chip to face each other. It is to arrange these layers provided on the surface in a position substantially symmetrical with respect to the center of the chip.
【００１４】上記第２の課題を解決するための第２の手
段（第８の発明）は、ペルチェ材料（チップ）の同一面
に電極を装着したペルチェ素子で、電極の近接した部分
にチップよりも電気伝導度および熱伝導度の低い層を設
け、この層の中心を通る直線に対してほぼ対称位置に電
極を設けるか、電極とチップの間に他の接合領域に比べ
てチップに対する接触電気抵抗および接触熱抵抗の高い
層を設け、同一面上に設けたこれらの層をチップの中心
を通る直線に対して概略対称位置に配置することであ
る。A second means (eighth invention) for solving the above-mentioned second problem is a Peltier element in which electrodes are mounted on the same surface of a Peltier material (chip). Also has a layer with low electrical and thermal conductivity, and an electrode is provided at a position approximately symmetrical with respect to a straight line passing through the center of this layer, or the contact electric power to the chip is increased between the electrode and the chip compared to other bonding areas. A layer having a high resistance and a high contact thermal resistance is provided, and these layers provided on the same plane are arranged in a substantially symmetrical position with respect to a straight line passing through the center of the chip.
【００１５】上記第２の課題を解決するための第３の手
段（第９の発明）は、上記第７の発明および第８の発明
で、軽元素を含むガス雰囲気中で熱処理し、熱処理によ
って変質した層の一部を取り除き、電気伝導度もしくは
熱伝導度の低い層を形成することである。A third means (9th invention) for solving the above-mentioned second problem is the above-mentioned 7th invention and 8th invention, wherein heat treatment is performed in a gas atmosphere containing a light element, and heat treatment is performed. That is, a part of the altered layer is removed to form a layer having low electric conductivity or thermal conductivity.
【００１６】[0016]
【作用】第１の発明の作用を図１を用いて説明する。本
発明では、図１に示す様に電極１とチップ４の間に、接
合材２と電気伝導度および熱伝導度の低い層(改質層３)
をチップ中心に対してほぼ対称位置に設ける。電気は電
極１，接合材２を通過した後、改質層３を避けてチップ
４内へ流れ込む。そのため、チップ４内の電流は図１の
チップの左下から右上へ至る成分が主流になり、対角線
の近くで最も電流密度が高くなる。このことは、電流の
通路を狭くかつ長くしたのと実効的に同じである。一
方、改質層３は熱伝導度も低いため、電極１とチップ４
との間を断熱する。従って、熱流でも実効的な通路は狭
くかつ長くなる。この様に、改質層を設けることにより
直方体チップで形状因子を大きくしたのと同様の効果が
得られ、最大効率点で運転した際に素子が必要とする放
熱量を下げ、所定の性能を達成できる。The operation of the first invention will be described with reference to FIG. In the present invention, as shown in FIG. 1, a bonding material 2 and a layer having low electric conductivity and thermal conductivity (modified layer 3) are provided between the electrode 1 and the chip 4.
Are provided substantially symmetrically with respect to the center of the chip. After passing through the electrode 1 and the bonding material 2, electricity flows into the chip 4 while avoiding the modified layer 3. Therefore, the current in the chip 4 is mainly composed of the components from the lower left to the upper right of the chip of FIG. 1, and the current density is highest near the diagonal line. This is effectively the same as making the current path narrow and long. On the other hand, since the reformed layer 3 also has low thermal conductivity, the electrode 1 and the tip 4
Insulate between and. Therefore, the effective passage for the heat flow is narrow and long. In this way, by providing the modified layer, the same effect as increasing the form factor of the rectangular parallelepiped chip can be obtained, and the amount of heat radiation required by the element when operating at the maximum efficiency point is reduced, and the predetermined performance can be obtained. Can be achieved.
【００１７】図２は表１の条件下で求めた改質層の長さ
と、各長さにおける最大成績係数（ＣＯＰ）およびその
時の放熱量の関係を示す図である。FIG. 2 is a diagram showing the relationship between the length of the modified layer obtained under the conditions of Table 1, the maximum coefficient of performance (COP) at each length, and the amount of heat radiation at that time.
【００１８】[0018]
【表１】 [Table 1]
【００１９】この図から、同一チップを用いても改質層
の長さを変えれば、素子の最大成績係数(約０.９５）を
維持したまま、放熱量を下げられることがわかる。そし
て表１に示す様に、素子は立方体のチップで構成されて
いるため、チップ製造時における歩留まりも良く、コス
ト的にも有利である。また、チップ（改質層を含む）の
二つの面の全域にわたって電極が接合されるため、外部
からの衝撃等によって生じる応力は小さい。従って、接
合部で破損する可能性は小さい。From this figure, it can be seen that even if the same chip is used, if the length of the modified layer is changed, the heat radiation amount can be lowered while maintaining the maximum coefficient of performance (about 0.95) of the device. Further, as shown in Table 1, since the element is composed of cubic chips, the yield at the time of chip manufacturing is good and the cost is advantageous. Further, since the electrodes are bonded over the entire area of the two surfaces of the chip (including the modified layer), the stress generated by an external impact or the like is small. Therefore, the possibility of breakage at the joint is small.
【００２０】一方、図３の様にチップに対する接触熱抵
抗および接触電気抵抗の大きい接合材２ａと小さい接合
材２ｂとを電極１とチップ４の間に形成しても、電流，
熱流が横切る断面積を実効的に小さくできる。従って、
この場合も性能で同様の効果を期待できる。また、電極
１とチップ４の接合部では、面の全域にわたって電極が
接合されるため破損の可能性は小さく、歩留まりの高い
チップを用いて素子を形成できるためコスト的にも有利
である。On the other hand, as shown in FIG. 3, even if the bonding material 2a having a large contact thermal resistance and contact electric resistance with respect to the chip and the bonding material 2b having a small contact resistance are formed between the electrode 1 and the chip 4, the current,
The cross-sectional area that the heat flow crosses can be effectively reduced. Therefore,
In this case, the same effect can be expected in terms of performance. In addition, since the electrodes are bonded over the entire surface of the bonding portion between the electrode 1 and the chip 4, the possibility of breakage is small, and the device can be formed using chips with high yield, which is advantageous in terms of cost.
【００２１】第２の発明の作用を図４を用いて説明す
る。図４は同一面上に電極を装着するタイプのペルチェ
素子で、チップの電極１を装着する側に改質層３を設
け、この層の中心を通る直線（図４の場合、縦方向の
線）を中心に、ほぼ対称位置に電極１を接合材２を介し
て設けたものである。図４の構成でも、電流，熱流の通
路が狭くかつ長くなる。例えば電流を例にとると、電流
は高抵抗の接合材３を避けて通過するため、左の電極１
から接合材２を通して、一旦、右上がりにチップ４に流
れ込み、その後右下がりに流れ、右の電極１に流れ込
む。また、改質層３は熱伝導度も小さいため、熱流でも
電流と同様の流れが生じる。従って第１の発明と同様
に、直方体チップで形状因子を大きくした場合と同様の
効果が得られ、第１の発明と同様の理由により接合部破
損の可能性は小さく、コスト的にも有利である。The operation of the second invention will be described with reference to FIG. FIG. 4 shows a Peltier element of the type in which electrodes are mounted on the same surface. A reforming layer 3 is provided on the side of the chip on which the electrode 1 is mounted, and a straight line passing through the center of this layer (in the case of FIG. 4, a vertical line). 2), the electrode 1 is provided at a substantially symmetrical position with the bonding material 2 interposed therebetween. In the configuration of FIG. 4 as well, the paths for current and heat flow are narrow and long. For example, in the case of an electric current, the electric current passes by avoiding the bonding material 3 having a high resistance.
Then, through the bonding material 2, it flows once upward in the right direction into the chip 4, then flows downward in the right direction, and then flows into the electrode 1 on the right side. Further, since the reformed layer 3 also has a low thermal conductivity, a flow similar to an electric current occurs even in the heat flow. Therefore, similar to the first invention, the same effect as when the shape factor is increased with the rectangular parallelepiped chip is obtained, and the possibility of breakage of the joint portion is small for the same reason as in the first invention, which is advantageous in cost. is there.
【００２２】また、第２の発明では、図５の様に接触熱
抵抗および接触電気抵抗の大きな接合材２ａと、これら
の小さい接合材２ｂを用いても、チップ４内の電流，熱
流の通路を実効的に狭くかつ長くすることができるの
で、同様の効果が得られる。Further, in the second invention, even if the bonding material 2a having a large contact thermal resistance and contact electrical resistance and the bonding material 2b having a small contact resistance as shown in FIG. Can be effectively narrowed and lengthened, and the same effect can be obtained.
【００２３】特定の結晶方位で優れた特性を示すペルチ
ェ材料の結晶方位を、対向する面に装着した電極の中心
を結ぶ方位と一致させると、電流，熱流の大部分は伝導
度が相対的に高い層の中心を結ぶ方向に流れる。従っ
て、第３の発明の様に、これらの流れ方向と、優れた熱
電特性を示すチップ方位とを一致させれば、ペルチェ素
子で達成できる冷却能力は、一致していない場合に比べ
て高くなる。また、図６に示す様に、電極１を接触熱抵
抗および接触電気抵抗の大きな接合材２ａとこれらが小
さな接合材２ｂによりチップ４に装着した構成として
も、電流，熱流の流れ方向（二つの接合材２ｂの中心を
結ぶ方向）と、優れた熱電特性を示すチップ方位とを一
致させることができる。さらに、本発明でも、第１，第
２の発明と同様に接合部破損の可能性は小さく、歩留ま
りの高いチップを用いて素子を形成できるためコスト的
にも有利である。When the crystal orientation of the Peltier material exhibiting excellent characteristics in a specific crystal orientation is made to coincide with the orientation connecting the centers of the electrodes mounted on the opposite surfaces, most of the electric current and heat flow have relatively high conductivity. It flows in the direction connecting the centers of the higher layers. Therefore, as in the third aspect of the present invention, if these flow directions are made to coincide with the chip orientation showing excellent thermoelectric characteristics, the cooling capacity that can be achieved by the Peltier element becomes higher than in the case where they do not coincide. . Further, as shown in FIG. 6, even when the electrode 1 is mounted on the chip 4 by the bonding material 2a having a large contact thermal resistance and contact electric resistance and the bonding material 2b having a small contact resistance, the flow direction of the current and the heat flow (two It is possible to match the direction in which the center of the bonding material 2b is connected) with the chip orientation that exhibits excellent thermoelectric characteristics. Further, also in the present invention, as in the first and second inventions, the possibility of damage to the bonding portion is small, and the element can be formed using a chip with a high yield, which is also advantageous in terms of cost.
【００２４】ペルチェ素子にｐ型の添加物とｎ型の添加
物を混在させると、それらが形成する不純物準位が、電
子，正孔の捕獲準位として働く。その結果、キャリア
（電子あるいは正孔）の濃度が低下する。また、添加物
がキャリアに対する散乱中心として働くため、移動度が
低下する。このキャリア濃度の低下と移動度の低下によ
って、ｐ型添加物とｎ型添加物が混在している層の電気
伝導度は低い。一方、熱伝導度でも同様のことが起こ
り、チップの極性を打ち消すために添加物を添加する
と、添加物の存在によって生じる歪，欠陥等が増え、熱
伝導度が低下する。この様に、電気伝導度，熱伝導度の
低い層を電極とチップの間に形成すれば、すでに述べた
理由により形状因子を上げるのと同様の効果が得られ、
放熱条件に制約がある場合でも、高性能の特性が得られ
る。また、チップの極性を消すために混入する添加物の
量は数％である。電極とチップの接合の良し悪しは、チ
ップの母材と接合材の組み合わせによってほぼ決まり、
数％の添加物によって影響を受けることはほとんどな
い。従って、機械的強度で変化はなく、接合部破損の可
能性は小さい。また、他の発明と同様に歩留まりの高い
チップを用いて素子を形成できるため、コスト的に有利
である。When the p-type additive and the n-type additive are mixed in the Peltier device, the impurity level formed by them acts as a trap level for electrons and holes. As a result, the concentration of carriers (electrons or holes) decreases. In addition, since the additive acts as a scattering center for carriers, the mobility decreases. Due to this decrease in carrier concentration and decrease in mobility, the electric conductivity of the layer in which the p-type additive and the n-type additive are mixed is low. On the other hand, the same thing occurs in the thermal conductivity, and when an additive is added to cancel the polarity of the chip, strains, defects and the like caused by the presence of the additive increase, and the thermal conductivity decreases. In this way, if a layer having low electrical conductivity and thermal conductivity is formed between the electrode and the chip, the same effect as increasing the form factor can be obtained for the reasons already described.
High performance characteristics can be obtained even when there are restrictions on heat dissipation conditions. Further, the amount of the additive mixed to erase the polarity of the chip is several%. The goodness of bonding of the electrode and the chip is almost determined by the combination of the base material of the chip and the bonding material,
It is rarely affected by a few% of additives. Therefore, the mechanical strength does not change, and the possibility of breakage of the joint is small. Further, as in the case of other inventions, elements can be formed using chips with high yield, which is advantageous in terms of cost.
【００２５】第５の発明によれば、電気伝導度，熱伝導
度の低い層を、第４の発明と同様に形成できる。例え
ば、ペルチェ材料として知られているＢｉ−Ｔｅ系の材
料に酸素を数％混入すると、電気伝導度は１桁以上低下
し、熱伝導度も数分の１に低下する。従って、本発明に
よっても、素子の形状因子を上げることが可能で、高性
能の特性が得られる。According to the fifth invention, a layer having low electric conductivity and low thermal conductivity can be formed in the same manner as in the fourth invention. For example, when a few percent of oxygen is mixed into a Bi-Te-based material known as a Peltier material, the electric conductivity decreases by one digit or more, and the thermal conductivity also decreases to a fraction. Therefore, according to the present invention as well, it is possible to increase the form factor of the device and obtain high performance characteristics.
【００２６】第６の発明でも、チップに形成した密度の
低い層は電気伝導度，熱伝導度が共に低くなるため、素
子の形状因子を上げることが可能で、高性能の特性が得
られる。また、この層は主成分がチップと同じで機械的
強度で他の部分との相違は小さいので、接合部の破損の
可能性は小である。Also in the sixth aspect of the invention, since the low-density layer formed on the chip has low electric conductivity and low thermal conductivity, it is possible to increase the form factor of the element and obtain high-performance characteristics. In addition, since the main component of this layer is the same as that of the chip and the difference in mechanical strength from other parts is small, the possibility of breakage of the joint is small.
【００２７】第７の発明によれば、図１，図３に示す第
１の発明と同様に電極とチップとの間に電気伝導度およ
び熱伝導度の低い層を設けたことにより、すでに説明し
た理由により高性能で破損の可能性が小さく、コスト的
に有利な素子を作製できる。第８の発明によれば、図
４，図５に示す第２の発明と同様に電極とチップとの間
に電気伝導度および熱伝導度の低い層を設けたことによ
り、すでに説明した理由により高性能で破損の可能性が
小さく、コスト的に有利な素子を作製できる。第９の発
明によれば、軽元素を含むガス雰囲気中でチップを熱処
理することにより、電気伝導度，熱伝導度の低い改質層
を形成できるため素子を高性能化できる。According to the seventh invention, as in the first invention shown in FIGS. 1 and 3, a layer having a low electrical conductivity and a low thermal conductivity is provided between the electrode and the chip, which has already been described. For the reason described above, it is possible to manufacture an element which has high performance, is less likely to be damaged, and is advantageous in terms of cost. According to the eighth invention, a layer having a low electrical conductivity and a low thermal conductivity is provided between the electrode and the chip as in the second invention shown in FIGS. 4 and 5, for the reasons already explained. It is possible to fabricate a device that has high performance, is less likely to be damaged, and is advantageous in terms of cost. According to the ninth aspect, by heat-treating the chip in a gas atmosphere containing a light element, a reformed layer having low electric conductivity and thermal conductivity can be formed, so that the device can have high performance.
【００２８】[0028]
【実施例】本発明の実施例を図１を用いて説明する。チ
ップ４はＢｉ−Ｔｅ系の材料を用い、電極１としては銅
板，アルミ板あるいはこれらの元素を主成分とする金属
板を用いた。板厚は０.５mm〜１.０mmとし、接合材２と
してＳｎ−Ｐｂ系の合金（半田）またはＡｇを主成分と
するペーストを固化させたものを用いた。チップ４は１
辺５mmの立方体とし(改質層３を含む)、酸素をチップに
５原子％程度混入させることにより改質層３を形成し
た。改質層３は図１の横方向に３mm、厚さ（図１の縦方
向長さ）は０.１mm 程度とし、奥行方向はチップと同じ
５mmとした。この構成により電極１とチップ４との接合
面積は実効的に約２／５に狭められ、電流・熱流の通路
はすでに説明した原理により変化する。An embodiment of the present invention will be described with reference to FIG. The chip 4 is made of a Bi-Te based material, and the electrode 1 is made of a copper plate, an aluminum plate or a metal plate containing these elements as a main component. The plate thickness was set to 0.5 mm to 1.0 mm, and the bonding material 2 was a solidified paste of Sn—Pb based alloy (solder) or Ag. Chip 4 is 1
A cube having a side of 5 mm (including the reforming layer 3) was formed, and the reforming layer 3 was formed by mixing about 5 atom% of oxygen into the chip. The modified layer 3 has a width of 3 mm in the horizontal direction of FIG. 1, a thickness (length in the vertical direction of FIG. 1) of about 0.1 mm, and a depth direction of 5 mm, which is the same as the chip. With this configuration, the joint area between the electrode 1 and the chip 4 is effectively narrowed to about 2/5, and the current / heat flow path changes according to the principle already described.
【００２９】素子の使用条件の制約から、例えば放熱量
をチップ当たり０.１Ｗ 以下としなければならない場
合、従来素子（５mm立方で改質層なし）の成績係数（Ｃ
ＯＰ）は、最大で０.７３ であるが、図１の素子の場
合、いずれの電極材，接合材の組み合わせでもＣＯＰは
約０.９５ となった。また、これらの素子は立方体構造
をしているので耐衝撃性に優れ、かつ量産化しやすいの
でコスト的に有利である。さらに、直方体素子と同様
に、電極とチップとを面全域にわたって接合できるの
で、接合部は外部からの衝撃に対しては強い。When the amount of heat radiation is required to be 0.1 W or less per chip due to the restrictions on the usage conditions of the device, the coefficient of performance (C
OP) is 0.73 at the maximum, but in the case of the element of FIG. 1, the COP was about 0.95 with any combination of the electrode material and the bonding material. Further, since these elements have a cubic structure, they have excellent impact resistance and are easy to mass-produce, which is advantageous in terms of cost. Further, as in the case of the rectangular parallelepiped element, the electrode and the chip can be bonded over the entire surface, so that the bonded portion is strong against external impact.
【００３０】本発明の別の実施例を図３を用いて説明す
る。これは、チップ４に接合材２ａと接合材２ｂを用い
て電極を装着した実施例で、チップに対する接触抵抗の
大きな接合材２ａによって、電流・熱流の通路を変化さ
せる。接合材２ａは、Ｓｎ−Ｐｂ系の合金，Ａｇを主成
分とする接合材料を用い、２ｂはＮｉ，グラファイトを
主成分とするペーストを固化させたものを用いた。Ｓｎ
−Ｐｂ系の合金あるいはＡｇを主成分とする接合材料の
接触電気抵抗は約２０μΩcm2 程度で、Ｎｉ，グラファ
イトを主成分とするものに比べて、２〜３桁低い接触電
気抵抗が得られ、接触熱抵抗も約１桁低い。チップの抵
抗は２×１０-3Ω程度で、接合材２ａの接触抵抗は４×
１０-5Ω程度であるのでほとんど無視できるが、Ｎｉ，
グラファイトを主成分とするものは２桁以上接触電気抵
抗が高くなり、チップよりも大きな電気抵抗が生じる。
従って、電気のほとんどは接合材２ｂを通してチップに
流入する。熱でも定性的には同じ流れが生じ、これらに
より、放熱量の少ない所でも高いＣＯＰを達成できた。
また、耐衝撃性，コストの面で上述した実施例とほぼ同
様の効果があった。Another embodiment of the present invention will be described with reference to FIG. This is an embodiment in which the electrodes are mounted on the chip 4 by using the bonding material 2a and the bonding material 2b, and the path of the current / heat flow is changed by the bonding material 2a having a large contact resistance to the chip. The bonding material 2a was a Sn-Pb based alloy, a bonding material containing Ag as a main component, and 2b was a solidified paste containing Ni and graphite as main components. Sn
The contact electric resistance of a Pb-based alloy or a bonding material containing Ag as a main component is about 20 μΩcm 2 , and a contact electric resistance lower by 2 to 3 orders of magnitude than that of a main component containing Ni or graphite. Contact thermal resistance is also about an order of magnitude lower. The resistance of the chip is about 2 × 10 -3 Ω, and the contact resistance of the bonding material 2a is 4 ×.
It can be almost ignored because it is about 10 −5 Ω, but Ni,
A material containing graphite as a main component has a contact electric resistance of two digits or more, which is higher than that of a chip.
Therefore, most of the electricity flows into the chip through the bonding material 2b. The same flow qualitatively occurs even with heat, and by these, a high COP can be achieved even in a place where the amount of heat radiation is small.
Further, in terms of impact resistance and cost, there was almost the same effect as the above-mentioned embodiment.
【００３１】本発明（第２の発明）の実施例を図４を用
いて説明する。第２の発明も、図１の実施例と基本的な
材料は同じで、チップとしてはＢｉ−Ｔｅ系の材料を用
い、電極１は銅板，アルミ板あるいはこれらの元素を主
成分とする金属板を用いた。板厚は０.５mm〜１.０mmと
し、接合材としてＳｎ−Ｐｂ系の合金（半田）またはＡ
ｇを主成分とするペーストを固化させたものを用いた。
チップは１辺５mmとし（改質層を含む）、酸素をチップ
に５原子％程度混入させることによりＢｉ−Ｔｅベース
の改質層３を形成した。改質層３は図１の横方向に３m
m、厚さ（図１の縦方向長さ）は０.１mm 程度，奥行方
向はチップと同じ５mmとした。この構成により電極とチ
ップとの接合面積は実効的に約１／５に狭められ、電流
・熱流の通路はすでに説明した原理により変化する。こ
の素子の場合、放熱量０.０５Ｗ以下の領域でＣＯＰは
約０.９５ になった。本発明の変形例が図５で、接合材
２ｂは、Ｓｎ−Ｐｂ系の合金，Ａｇを主成分とする接合
材料を用い、２ａはＮｉ，グラファイトを主成分とする
ペーストを固化させたものを用いた。この場合も、電
気，熱のほとんどが接合材２ｂを通してチップに流入す
るため、放熱量の少ない所でも高いＣＯＰを達成でき
た。また、耐衝撃性，コストの面で上述した実施例とほ
ぼ同様の効果があった。An embodiment of the present invention (second invention) will be described with reference to FIG. Also in the second invention, the basic material is the same as that of the embodiment of FIG. 1, a Bi-Te based material is used for the chip, and the electrode 1 is a copper plate, an aluminum plate or a metal plate containing these elements as a main component. Was used. The plate thickness is 0.5 mm to 1.0 mm, and Sn-Pb alloy (solder) or A is used as the bonding material.
A solidified paste containing g as a main component was used.
The chip was 5 mm on a side (including the modified layer), and oxygen was mixed into the chip at about 5 atomic% to form the Bi-Te-based modified layer 3. The modified layer 3 is 3 m in the horizontal direction of FIG.
m, thickness (vertical length in FIG. 1) is about 0.1 mm, and depth is 5 mm, which is the same as the chip. With this configuration, the joint area between the electrode and the chip is effectively narrowed to about 1/5, and the current / heat flow path changes according to the principle already described. In the case of this device, the COP was about 0.95 in the region where the heat radiation amount was 0.05 W or less. A modified example of the present invention is shown in FIG. 5, in which the bonding material 2b is a Sn—Pb alloy, a bonding material containing Ag as a main component, and 2a is a solidified paste containing Ni and graphite as main components. Using. Also in this case, most of electricity and heat flow into the chip through the bonding material 2b, so that a high COP can be achieved even in a place with a small amount of heat radiation. Further, in terms of impact resistance and cost, there was almost the same effect as the above-mentioned embodiment.
【００３２】第３の発明の実施例を図６を用いて説明す
る。Ｂｉ−Ｔｅ系材料では、ａ軸方向が比較的熱電特性
（出力因子，性能指数）の優れた方位として知られてい
る。本発明では、接触電気抵抗および接触熱抵抗が相対
的に低い接合材２ｂの中間を結ぶ線上にａ軸を一致させ
た。すでに述べた理由により、電流・熱流のほとんどは
図６の場合、接合材２ｂを結ぶ線上、すなわち、Ｂｉ−
Ｔｅ結晶中の熱電特性の優れた方向に流れるため、高い
ＣＯＰを達成できた。また、実効的に形状因子を大きく
した効果により、放熱が十分に得られない所での使用も
可能になった。次に第４の発明の実施例を説明する。Ｂ
ｉ−Ｔｅ系材料のｐ型添加物は、一般に、Ｓｂ，Ｔｉ，
Ｐｂ，Ｃｄ等が用いられ、ｎ型添加物は、Ａｇ，Ｓｅ，
Ｉ，Ｃｕ等が用いられる。ここではＳｂを１.５ 原子％
添加したチップに、Ａｇを１.０ 原子％混入し、図１，
図３の改質層３を形成したところ、添加物（不純物準
位）が互いにキャリア（電子あるいは正孔）の捕獲中心
として働くため、電気伝導度が２桁以上低下し、添加物
の存在によって生じる歪，欠陥等が増え、その結果、熱
伝導度も２〜５割低下した。この場合でも、電気伝導
度，熱伝導度の低い層を電極とチップの間に形成すれ
ば、すでに述べた理由により形状因子を上げるのと同様
の効果が得られ、放熱条件に制約がある場合でも、高性
能の特性が得られた。また、機械的強度で変化はないた
め、接合部破損の可能性は小さく、他の発明と同様に歩
止まりの高いチップを用いて素子を形成できるためコス
ト的に有利である。An embodiment of the third invention will be described with reference to FIG. In the case of the Bi-Te-based material, the a-axis direction is known as a direction having relatively excellent thermoelectric characteristics (output factor, figure of merit). In the present invention, the a-axis is aligned with the line connecting the middles of the bonding materials 2b having relatively low contact electric resistance and contact thermal resistance. For the reason described above, in the case of FIG. 6, most of the electric current / heat flow is on the line connecting the joining materials 2b, that is, Bi-
A high COP could be achieved because the Te crystals flow in the direction of excellent thermoelectric properties. In addition, the effect of effectively increasing the shape factor has made it possible to use it in a place where sufficient heat radiation cannot be obtained. Next, an embodiment of the fourth invention will be described. B
The p-type additive of the i-Te-based material generally includes Sb, Ti,
Pb, Cd, etc. are used, and the n-type additive is Ag, Se,
I, Cu or the like is used. Here, Sb is 1.5 atomic%
The added chips were mixed with 1.0 atomic% of Ag, and
When the modified layer 3 of FIG. 3 is formed, the additives (impurity levels) work as trap centers for carriers (electrons or holes) with each other, so that the electric conductivity decreases by two digits or more, and the presence of the additives The generated strains and defects increased, and as a result, the thermal conductivity also decreased by 20 to 50%. Even in this case, if a layer having low electrical conductivity and thermal conductivity is formed between the electrode and the chip, the same effect as increasing the form factor can be obtained for the reason already described, and the heat dissipation condition is restricted. However, high performance characteristics were obtained. In addition, since there is no change in mechanical strength, the possibility of damage to the joint is small, and as with other inventions, elements can be formed using chips with high yield, which is advantageous in terms of cost.
【００３３】第５の発明も基本的には図１，図３の構造
をベースとしており、改質層３をＢｉ−Ｔｅ系材料に酸
素，窒素，炭素等の軽元素を混入し、Ｂｉ−Ｔｅ系材料
を構成する元素の酸化物，窒化物，炭化物等を形成す
る。ここでは、５原子％程度の酸素をＢｉ−Ｔｅ材料の
一部に混入した結果、電気伝導度が２桁以上低い層が形
成できた。一方、熱伝導度も２〜５割低下したため、す
でに述べた理由により形状因子を上げるのと同様の効果
が得られ、放熱条件に制約がある場合でも、高性能の特
性が得られた。The fifth invention is also basically based on the structure shown in FIGS. 1 and 3, and the modified layer 3 is formed by mixing light elements such as oxygen, nitrogen, and carbon into a Bi-Te-based material to form a Bi-Te-based material. Form oxides, nitrides, and carbides of the elements that make up the Te-based material. Here, as a result of mixing about 5 atom% of oxygen into a part of the Bi-Te material, a layer having a low electric conductivity of two digits or more could be formed. On the other hand, since the thermal conductivity was also reduced by 20 to 50%, the same effect as increasing the form factor was obtained for the reasons already described, and high performance characteristics were obtained even when the heat dissipation conditions were restricted.
【００３４】第６の発明も基本的には図１，図３の構造
をベースとしており、低密度のＢｉ−Ｔｅ系材料を用い
て改質層３を形成した。Ｂｉ−Ｔｅ焼結体チップの場
合、焼結密度が６０％を下回るものは電気伝導度が１桁
近く低い。一方、熱伝導度も２〜５割程度低下するた
め、すでに述べた理由により形状因子を上げるのと同様
の効果が得られ、放熱条件に制約がある場合でも、高性
能の特性が得られた。The sixth invention is also basically based on the structure shown in FIGS. 1 and 3, and the modified layer 3 is formed by using a low density Bi-Te based material. In the case of the Bi-Te sintered body chip, the one having a sintered density of less than 60% has a low electric conductivity of about one digit. On the other hand, since the thermal conductivity is also reduced by about 20 to 50%, the same effect as increasing the shape factor is obtained for the reasons already described, and high performance characteristics are obtained even when the heat radiation conditions are limited. .
【００３５】第７の発明の実施例を図７を用いて説明す
る。まず、チップ４としてＢｉ−Ｔｅ系の材料を用い、
例えば、ｎ型のチップにはｐ型添加物（例えばＳｂ，Ｔ
ｉ，Ｐｂ，Ｃｄ等）を含むパウダーを塗布し、４００℃
〜５００℃で熱処理し、チップ中にｐ型添加物を拡散さ
せた。次にＳｎ−Ｐｂ系の合金（半田）もしくはＡｇを
主成分とするペーストを接合材２として用い、電極１を
装着した。また、図８の様にチップ４に接合材２ａと接
合材２ｂを順々に塗布し、電極１を装着した。接合材２
ａとしては、すでに述べた様にＳｎ−Ｐｂ系の合金，Ａ
ｇを主成分とする接合材料を用い、２ｂとしてはＮｉ，
グラファイトを主成分とするペーストを固化させたもの
を用いた。図７，図８いずれの場合も、素子の使用条件
に制約がある場合でも、高いＣＯＰを達成でき、立方体
構造をしているので耐衝撃性があり、かつ量産化しやす
いのでコスト的に有利な素子を製造できた。An embodiment of the seventh invention will be described with reference to FIG. First, a Bi-Te-based material is used for the chip 4,
For example, a p-type additive (for example, Sb, T
i, Pb, Cd, etc.) and apply at 400 ℃
Heat treatment was performed at ˜500 ° C. to diffuse the p-type additive in the chip. Next, the electrode 1 was attached using a Sn-Pb alloy (solder) or a paste containing Ag as a main component as the bonding material 2. Further, as shown in FIG. 8, the bonding material 2a and the bonding material 2b were sequentially applied to the chip 4 and the electrode 1 was attached. Bonding material 2
As a, Sn-Pb type alloy, A
A bonding material containing g as a main component is used, and 2b is Ni,
A solidified paste containing graphite as the main component was used. In both cases of FIG. 7 and FIG. 8, a high COP can be achieved even if there are restrictions on the use conditions of the element, and since it has a cubic structure, it has impact resistance and is easy to mass-produce, which is advantageous in terms of cost. The device could be manufactured.
【００３６】図９は第８の発明の実施例を示し、図７の
実施例と同様に、ペルチェ材料（チップ４）としてＢｉ
−Ｔｅ系の材料を用い、ｎ型のチップにはｐ型添加物を
含むパウダーを塗布し、４００℃〜５００℃で熱処理
し、チップ中にｐ型添加物を拡散させた。次にＳｎ−Ｐ
ｂ系の合金（半田）もしくはＡｇを主成分とするペース
トを接合材２として用い、電極１を装着した。この場合
も、電気，熱が改質層３を避けて通過し、その結果、形
状因子を実効的に大きくできるので、放熱量の少ない所
でも高いＣＯＰを達成できた。また、耐衝撃性，コスト
の面で他の実施例と同様の効果があった。FIG. 9 shows an eighth embodiment of the invention, and like the embodiment of FIG. 7, Bi is used as the Peltier material (chip 4).
A powder containing a p-type additive was applied to the n-type chip using a -Te-based material and heat-treated at 400 ° C to 500 ° C to diffuse the p-type additive into the chip. Then Sn-P
The electrode 1 was attached using a b-based alloy (solder) or a paste containing Ag as a main component as the bonding material 2. Also in this case, electricity and heat pass through avoiding the reforming layer 3, and as a result, the shape factor can be effectively increased, so that a high COP can be achieved even in a place with a small amount of heat radiation. Further, in terms of impact resistance and cost, the same effects as the other examples were obtained.
【００３７】図１０は第９の発明の一実施例を示し、チ
ップ４をここでは酸素ガス雰囲気中で数十分加熱して改
質層３をチップ全体に形成し、その後、改質層３の一部
を残して削除し、その上に接合材２を塗布し、電極１を
形成した。この手法の場合も他の手法と同様の効果が得
られた。FIG. 10 shows an embodiment of the ninth invention, in which the chip 4 is heated in an oxygen gas atmosphere for several tens of minutes to form the modified layer 3 on the entire chip, and then the modified layer 3 is formed. Was removed leaving a part thereof, and the bonding material 2 was applied thereon to form the electrode 1. In the case of this method, the same effect as other methods was obtained.
【００３８】[0038]
【発明の効果】本発明によれば、さまざまな（放熱）条
件下で、高い冷却効率を達成でき、耐久性，コストの面
でも有利な素子を構成できる。According to the present invention, a high cooling efficiency can be achieved under various (heat dissipation) conditions, and an element advantageous in terms of durability and cost can be constructed.
【図１】第１の発明（伝導度の低い層を設ける場合）の
基本構成を示す断面図。FIG. 1 is a sectional view showing a basic configuration of a first invention (when a layer having low conductivity is provided).
【図２】改質層の長さと、効率および放熱量の関係を示
す説明図。FIG. 2 is an explanatory diagram showing the relationship between the length of the modified layer and the efficiency and the amount of heat radiation.
【図３】第１の発明（接触抵抗の高い層を設ける場合）
の基本構成を示す断面図。FIG. 3 First invention (when a layer having high contact resistance is provided)
Sectional drawing which shows the basic composition of.
【図４】第２の発明（伝導度の低い層を設ける場合）の
基本構成を示す断面図。FIG. 4 is a cross-sectional view showing the basic structure of the second invention (when a layer having low conductivity is provided).
【図５】第２の発明（接触抵抗の高い層を設ける場合）
の基本構成を示す断面図。FIG. 5: Second invention (when a layer having high contact resistance is provided)
Sectional drawing which shows the basic composition of.
【図６】第３の発明の一実施例を示す断面図。FIG. 6 is a sectional view showing an embodiment of the third invention.
【図７】第７の発明の一実施例を示す断面図。FIG. 7 is a sectional view showing an embodiment of the seventh invention.
【図８】第７の発明の一実施例を示す断面図。FIG. 8 is a sectional view showing an embodiment of the seventh invention.
【図９】第８の発明の一実施例を示す断面図。FIG. 9 is a sectional view showing an embodiment of the eighth invention.
【図１０】第９の発明の一実施例を示す説明図。FIG. 10 is an explanatory view showing an embodiment of the ninth invention.
１…電源、２…接合材、２ａ…接合材（ａ）、２ｂ…接
合材（ｂ）、３…改質層、４…チップ。1 ... Power source, 2 ... Bonding material, 2a ... Bonding material (a), 2b ... Bonding material (b), 3 ... Modified layer, 4 ... Chip.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 石田 富雄 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tomio Ishida 7-1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory
Claims (9)
チェ素子において、前記電極の近接する部分に前記チッ
プよりも電気伝導度および熱伝導度の低い層を設ける
か、前記電極と前記チップの間に他の電極接合領域に比
べて前記チップに対する接触電気抵抗および接触熱抵抗
の高い層を設け、対向する面に設けたこれらの層を前記
チップの中心に対して概略対称位置に配置したことを特
徴とするペルチェ素子。1. In a Peltier element having electrodes mounted on opposite surfaces of a chip, a layer having lower electrical conductivity and thermal conductivity than that of the chip is provided at a portion adjacent to the electrode, or the Peltier element of the electrode and the chip are provided. Layers having high contact electric resistance and contact thermal resistance with respect to the chip as compared with other electrode bonding areas are provided between them, and these layers provided on the facing surface are arranged at substantially symmetrical positions with respect to the center of the chip. Is a Peltier element.
素子において、電極の近接する部分に前記チップよりも
電気伝導度および熱伝導度の低い層を設け、この層の中
心を通る直線に対してほぼ対称位置に前記電極を設ける
か、前記電極と前記チップの間の一部に他の電極接合領
域に比べて前記チップに対する接触電気抵抗および接触
熱抵抗の高い層を設け、同一面上に設けたこれらの層を
前記チップの中心を通る直線に対して概略対称位置に配
置したことを特徴とするペルチェ素子。2. In a Peltier device having electrodes mounted on the same surface of a chip, a layer having lower electrical conductivity and thermal conductivity than that of the chip is provided in a portion close to the electrodes, and a straight line passing through the center of this layer is provided. The electrodes in a substantially symmetrical position, or a layer having a higher contact electric resistance and contact thermal resistance with respect to the chip than other electrode bonding areas is provided in a part between the electrode and the chip, and the electrodes are provided on the same surface. A Peltier device characterized in that these provided layers are arranged in substantially symmetrical positions with respect to a straight line passing through the center of the chip.
気伝導度σあるいは熱伝導度κにより定義される出力因
子（α2σ）もしくは性能指数（α2σ／κ）が、特定の
結晶方位において優れたチップの結晶方位を、前記チッ
プと前記電極間に設けた接合材の電気伝導度および熱伝
導度が相対的に高い部分の中心を結ぶ方向、あるいは前
記チップに対する接触電気抵抗および接触熱抵抗が相対
的に低い部分の中心を結ぶ方向と概略一致させたペルチ
ェ素子。3. The output factor (α 2 σ) or figure of merit (α 2 σ / κ) defined by the Seebeck coefficient α, electrical conductivity σ or thermal conductivity κ according to claim 1, is a specific crystal orientation. In the direction of connecting the centers of the portions of the bonding material provided between the chip and the electrode having relatively high electric conductivity and thermal conductivity, or the contact electric resistance and the contact heat to the chip. A Peltier element that is roughly aligned with the direction connecting the centers of the parts where the resistance is relatively low.
しくは熱伝導度の低い層を、ｐ型添加物とｎ型添加物の
両方を含む材料により構成したペルチェ素子。4. The Peltier device according to claim 1, wherein the layer having low electrical conductivity or thermal conductivity is made of a material containing both a p-type additive and an n-type additive.
しくは熱伝導度の低い層を、軽元素を含む材料により構
成したペルチェ素子。5. A Peltier device according to claim 1, wherein the layer having low electrical conductivity or thermal conductivity is made of a material containing a light element.
しくは熱伝導度の低い層を、前記チップとほぼ同様の成
分を有し、前記チップに比べ密度の低い材料で構成した
もの。6. The layer according to claim 1, wherein the layer having low electrical conductivity or thermal conductivity has a component substantially similar to that of the chip and is made of a material having a lower density than the chip.
チェ素子の製造法において、電極の近接した部分にチッ
プよりも電気伝導度および熱伝導度の低い層を設ける
か、前記電極と前記チップの間に他の電極接合領域に比
べて前記チップに対する接触電気抵抗および接触熱抵抗
の高い層を設け、対向する面に設けたこれらの層を前記
チップの中心に対して概略対称位置に配置したことを特
徴とするペルチェ素子の製造方法。7. A method for manufacturing a Peltier device having electrodes mounted on opposite surfaces of a chip, wherein a layer having lower electric and thermal conductivity than that of the chip is provided in a portion close to the electrode, or the electrode and the chip are provided. Layers having high contact electric resistance and contact thermal resistance with respect to the chip as compared with other electrode bonding regions are provided between the layers, and these layers provided on the opposite surfaces are arranged at substantially symmetrical positions with respect to the center of the chip. A method of manufacturing a Peltier device, characterized in that
素子において、電極の近接する部分に前記チップよりも
電気伝導度および熱伝導度の低い層を設け、この層の中
心を通る直線に対してほぼ対称位置に前記電極を設ける
か、前記電極と前記チップの間に他の電極接合領域に比
べて前記チップに対する接触電気抵抗および接触熱抵抗
の高い層を設け、同一面上に設けたこれらの層が前記チ
ップの中心を通る直線に対して概略対称位置に配置した
ことを特徴とするペルチェ素子の製造方法。8. In a Peltier device having electrodes mounted on the same surface of a chip, a layer having lower electrical conductivity and thermal conductivity than the chip is provided in a portion close to the electrodes, and a straight line passing through the center of this layer is provided. These electrodes are provided on substantially the same plane, or a layer having higher contact electric resistance and contact thermal resistance with respect to the chip as compared with other electrode bonding areas is provided between the electrode and the chip, and these layers are provided on the same surface. Is placed in a substantially symmetrical position with respect to a straight line passing through the center of the chip.
ガス雰囲気中で熱処理し、熱処理によって変質した層の
一部を取り除き、電気伝導度および熱伝導度の低い層を
形成するペルチェ素子の製造方法。9. A Peltier element according to claim 7 or 8, which is heat-treated in a gas atmosphere containing a light element to remove a part of the layer altered by the heat treatment to form a layer having low electric conductivity and thermal conductivity. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7229880A JPH0974226A (en) | 1995-09-07 | 1995-09-07 | Peltier element and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7229880A JPH0974226A (en) | 1995-09-07 | 1995-09-07 | Peltier element and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0974226A true JPH0974226A (en) | 1997-03-18 |
Family
ID=16899161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7229880A Pending JPH0974226A (en) | 1995-09-07 | 1995-09-07 | Peltier element and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0974226A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007275802A (en) * | 2006-04-07 | 2007-10-25 | Matsushita Electric Works Ltd | Electrostatic atomization device and assembling method thereof |
-
1995
- 1995-09-07 JP JP7229880A patent/JPH0974226A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007275802A (en) * | 2006-04-07 | 2007-10-25 | Matsushita Electric Works Ltd | Electrostatic atomization device and assembling method thereof |
| JP4670712B2 (en) * | 2006-04-07 | 2011-04-13 | パナソニック電工株式会社 | Electrostatic atomizer and assembly method thereof |
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