JPH0974179A - Photoelectric converter, photo sensor array, semiconductor device and facsimile device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a buried layer, a diffusion layer and an epitaxial layer, and attain cost reduction. SOLUTION: There are formed on a first conduction type semiconductor substrate 101; a first semiconductor region 107 of a second conduction type in which carriers formed by receiving light energy are collected, and a second semiconductor region 108 of a first conduction type which is in contact with the first semiconductor region and outputs a signal corresponding to the carriers. A control electrode 111 which is adjacent to the first semiconductor region and capable of potential control is formed on the semiconductor substrate via an insulating layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, a photo sensor array, a semiconductor device and a facsimile machine.

[0002]

2. Description of the Related Art Conventionally, photodiodes have been used as a reading device for facsimiles using single crystal silicon.
A MOS type line sensor and a CCD (charge coupled device) that are switched by an S transistor.
ce) etc. have been used. Furthermore, in recent years, a bipolar photoelectric conversion device (Base stored type) having a self-amplification function disclosed in Japanese Patent Laid-Open No. 210210/1990 and having a small output reduction due to a division capacity ratio is disclosed.
Image Sensor; hereinafter referred to as a bipolar sensor. ) Came to be used.

A schematic diagram of a bipolar sensor is shown in FIG.
0 is shown. A reading circuit of the bipolar sensor is shown in FIG. Here, the operation principle will be briefly described.
A depletion layer spreads from the base region 107 to the low concentration region 104 of the collector. When light is applied to this depletion region, electron-hole pairs are generated, and electrons move to the collector electrode and holes move to the base region 107. Here, the base region 10
If 7 is floating, the base potential will shift to the positive side,
A collector current flows between the collectors 102, 106 and the emitter 108. This becomes the signal current corresponding to the change in the base potential. Since the signal charge generated by light is not output as it is but is amplified and output by the bipolar transistor constituent portion once, there is no extreme decrease in output and it is resistant to noise.

Then, as shown in FIG. 11, the output from the bipolar sensor S is stored in the capacitor C _T via the MOS transistor Tr2 and further output via the MOS transistor Tr7. MOS transistor Tr
1, Tr3 and Tr6 are for resetting the base, emitter and output line of the bipolar type sensor, respectively.

[0005]

However, even in the above bipolar type sensor, there have been some points to be improved as described below.

First, as shown in FIG. 10, although the collector potential of the bipolar type sensor is common and the maximum collector current is a small value, as shown in FIG.
In addition, since the deep n-type diffusion layer 106 is required, as a result, a step of growing the epitaxial layer 104, which is an expensive manufacturing step, is also required. This is because holes generated by light are collected in the base region 107 as much as possible, and therefore it is necessary to form a potential barrier on the bottom 102 and the side surface 106 of the collector, and therefore, the diffusion layers 102 and 106 having a high concentration with respect to the epitaxial layer 104. It forms a container-shaped barrier to confine holes. As a result, the buried layer 102 and the epitaxial layer 104 are indispensable in terms of device structure, and a step of p-type buried layer is added to these two steps to manufacture 30% or more as compared with the MOS photoelectric conversion device. Costs are rising.

Second, in order to reduce the base-collector capacitance, it is usually necessary to make the concentration of the epitaxial layer 104 lower than that of the bipolar transistor by one digit or more.
That is, the depletion layer may be unnecessarily spread on the surface portion of No. 4 to induce the surface generated current. In order to suppress the surface generated current, it is possible to suppress the surface generated current by forming a medium-concentration shallow diffusion layer in the vicinity of the surface of the epitaxial layer 104. However, the addition of the diffusion layer forming step further increases the cost. Will be invited.

A first object of the present invention is to create a potential gradient in a substrate without depending on a buried layer or a deep diffusion layer,
This makes it possible to construct a bipolar photoelectric conversion device array without the need for manufacturing steps of the buried layer and the epitaxial layer.

A second object of the present invention is to control the surface potential of the collector with a control electrode.
The depletion layer is controlled so as not to expand except during the signal charge accumulation period, and an additional step such as formation of a diffusion layer is unnecessary.

[0010]

In the photoelectric conversion device of the present invention, a first conductivity type semiconductor substrate and a second conductivity type first semiconductor region in which carriers generated by receiving light energy are collected. A second conductivity type second contacting the first semiconductor region, which outputs a signal corresponding to the carrier.
And a control electrode capable of controlling the potential via an insulating layer is provided on the semiconductor substrate adjacent to the first semiconductor region.

The photosensor array of the present invention comprises a plurality of the photoelectric conversion devices described above.

In the semiconductor device of the present invention, at least the photosensor array and the readout circuit are formed in the same semiconductor substrate.

A facsimile apparatus of the present invention uses the above semiconductor device as a reader.

The semiconductor device of the present invention is the semiconductor device described above, wherein the read circuit is composed of an n-type MOS transistor and a p-type MOS transistor.

[0015]

The present invention provides a MIS (Metal-Insulator) at a position adjacent to the base of a bipolar type sensor.
A potential well is formed by providing a control electrode having a (Semiconductor) structure, and a barrier against carriers generated by light is formed without using a buried layer or a diffusion layer. As a result, the buried layer and the epitaxial layer are formed in the entire photosensor. Layer and a deep collector diffusion layer are not necessary. Further, in the above-mentioned bipolar type sensor, by using a read circuit which is composed of only MOS transistor elements on the same substrate and does not use MIS capacitance, the whole integrated circuit can be obtained. The buried layer, the epitaxial layer, and the deep diffusion layer having the same conductivity type as the collector can be omitted.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a vertical sectional view showing the structure of an embodiment of the photoelectric conversion device of the present invention. In the figure, 101 is an n-type substrate such as silicon, 107 is a p-type diffusion layer corresponding to the main part of the base region, 108 is an n-type diffusion layer corresponding to the emitter region, 109 is a part of the base region and is accumulated in the base region. And a shallow diffusion layer for forming the drain and source regions of the p-type MOS transistor for resetting the signal charge, 110 is a gate electrode of the p-type MOS transistor, and 111 is a control electrode for forming a potential well in the substrate 101. , 112 are potential wells (depletion regions) formed by the control electrode 111.

The principle of operation when an n-type silicon substrate is used as the base 101 will be described in detail below with reference to FIGS. In FIG. 2, the control electrode 111 and the base region 107,
The enlarged drawing of 109 parts is shown.

Here, a positive electrode is applied to the n-type semiconductor substrate 101.
Potential, for example, by applying a potential of 5 V as an example,
The state where 0V potential is applied to the control gate electrode 111.
Think about the situation. In this case, the area shown by the dotted line in FIG.
The depletion layer spreads and extends along the Y direction of the vertical line of the semiconductor substrate 101.
Therefore, the conduction band Ec and the valence band Ev are as shown in FIG.
There is a bend in the band. Then, this depletion layer region
When the light hν is incident on the electron, as shown in FIG.
Hole pairs are generated, and the holes are on the surface side of the semiconductor substrate 101, that is,
Collected on the potential control electrode 111 side,
The child escapes to the lower part of the base 101, that is, the lower side in FIG.
Good. At this time, the gate of the reset MOS transistor 121 is
And the base electrode 10 is in the off state at 5V.
It is assumed that 7,109 are in a floating state. Base
That the initial potentials of the regions 107 and 109 are near 0V
Then, the interface potential immediately below the control electrode 111.
X _sLower potential and control
The holes directly under the pole 111 are the bipolar base region 1
It flows into 07,109. Here, the base region 107,
Since 109 is in a floating state,
Due to the electric charge of the holes, the Fermi level EF and Fig. 3 (b)
The potential rises as indicated by arrow L. If you think quantitatively,
The potential change amount of the base regions 107 and 109 is ΔV_bage,
Q is the amount of charge of the holes that flowed in_PAnd

[0020]

## EQU1 ## ΔV _b = Q _P / (C _be + C _bc ) Equation (1) (where C _{be is the} base-emitter capacitance and C _{bc is the} base-collector capacitance).

As described above, a certain amount of holes are generated in the base region 1.
When accumulated in 07 and 109, the interface potential χ _{s under} the control electrode 111 and the bases 107 and 109 have the same potential as shown in FIG. 4B.
Up to this point, the depletion layer width W just below the control electrode 111 does not change as shown in FIGS. 3 and 4, and holes are continuously collected efficiently according to the light quantity hν.

When the holes generated by the light hν are further collected in this state, the interface potential χ _s directly under the control electrode 111 and the bases 107 and 109 are kept at the same potential, and the arrow L in FIG. 4B is used. , M, and the holes are immediately below the control electrode 111 and in the base region 1.
It is accumulated in both 07 and 109. At this time, in the depletion layer immediately below the control electrode 111, the width of the depletion layer shrinks from W to W ′ within the range in which the interface maintains the strong inversion state. The potential change in the base region at this time is

[0023]

## EQU2 ## ΔV _b = Q _P / (C _be + C _bc + C _3D ) Equation (2) (where C _3D is the depletion layer capacitance directly under the control electrode 111) and the potential rises slowly. I will do it.

In this way, after a certain accumulation time,
The potential relationship is as shown in FIG. this
From the state, the electric potential of the control electrode 111 is changed from 0V to the base.
The voltage is changed to + 5V which is the same potential as 101. Control
Ignoring the work function difference between the electrode 111 and the semiconductor substrate 101
And the interfacial potential χ of the control electrode 111 _s
Also becomes 5 V, and the potential indicated by the arrow M in FIG.
The rise happens all at once. As a result, the distribution of potential is
It changes to the state of 6 and is directly under the control electrode 109.
The positive holes flow into the base regions 107 and 109.

Here, of the holes accumulated directly under the control electrode 111, there is a problem as to what proportion of the holes flow into the base regions 107 and 109.
As shown in FIG. 1, when the metal wiring 114 for applying a potential to the control electrode 111 is arranged in a position as far as possible from the base regions 107 and 109, a potential gradient of the interface potential potential χ _s is transiently generated in the horizontal direction, Due to the difference in mobility between polycrystalline silicon and single crystal silicon, hole transfer at the single crystal interface is carried out more quickly than charge transfer on the control electrode 111 side, and almost all holes are transferred.
It flows into the base regions 107 and 109.

[0026] As a result, the potential change of the base region 107 and 109 with respect to the potential total amount Q _P of generated holes

[0027]

[Number 3] _{ΔV b = Q P / (C} be + C bc) ··· (3), and the same relationship is maintained with the formula (1).

[0028] This means that, regardless of the magnitude of the generated charge Q _P due to the light, the base 10 of the bipolar transistor
This means that the potential of 7,109 is determined only by the C _be and C _bc capacitances. Therefore,

[0029]

[Formula 4] V _b ∝Q _P ∝I _L · t _s Equation (4) (where V _{b is the} base potential, I _{L is the} light intensity, and t _{s is the} storage time). It holds.

Thus, when 0V is finally applied to the gate electrode 110 of the reset MOS transistor 121 to turn on the reset MOS transistor 121, the potentials of the base regions 107 and 109 return to around 0V (FIG. 7).

After that, the potential of the control electrode 111 is returned to 0 V, a voltage of 5 V is applied to the gate electrode 110 of the reset MOS transistor 121, and the reset MO transistor is reset again.
When the S transistor 121 is returned to the off state, the initial state of FIG. 3 is reproduced.

FIG. 8 shows an example of the readout circuit of the photoelectric conversion device of the present invention. As shown in the figure, the read circuit is MIS
It has no passive elements such as capacitors and is composed of only MOS transistors. The read circuit and the operation method will be described with reference to the timing chart of FIG. The terminal of the control electrode 111 described above is shown as T _C in FIG.

First, during the accumulation period of the signal charge, the potential well is formed at the Lo level at the control electrode terminal T _C as described above. At this time, the base reset PMOS
Gate T ₁ of the transistor Tr1 is in the off state at the Hi level. The gate of the transfer NMOS transistor Tr2 is in the ON state at the Hi level, and the emitter current of the bipolar sensor flows according to the fluctuation of the base potential and is accumulated in the gate electrode of the read transistor Tr4.

[0034]

(Equation 5) (Where V _{E is} the emitter potential of the bipolar sensor,
V _4G : Read, gate potential of MOS transistor Tr ₄ ) After the signal charges are accumulated, the gate of the transfer MOS transistor Tr 2 is lowered to Lo level and turned off. Next, the gate of the NMOS transistor Tr5 that gives the read timing is set to the Hi level,
Turn 4 on. At this time, the source potential of the read transistor Tr4 changes according to the gate potential, and the source potential becomes the output potential. After the reading is completed, the gate of the NMOS transistor Tr5 is lowered to Lo level and the reading transistor Tr4 is turned off.

Next, in order to reset the charges accumulated in the gate of the read MOS transistor Tr4, the gate of the gate resetting MOS transistor Tr6 is set to the Hi level and turned on. By this operation, the read MOS transistor Tr4 is initialized. Finally, in order to initialize the bipolar sensor, the complete reset MOS transistor Tr1 and the transient reset MOS transistor Tr3 are sequentially turned on to restore the base potential and the emitter potential to the state before signal accumulation.

By repeating the above operation, a line photo sensor can be constructed, and the read MOS transistor T
If the source of r4 is connected, it becomes a common read line.

Finally, the manufacturing process of one embodiment of the present invention will be briefly described. Basically, it is a well-known technology CM
It can be considered that the step of forming the base diffusion layer is added to the OS manufacturing step.

First, an n-type silicon substrate of about 20 to 30 Ω · cm is prepared. First, a P well is formed. Ion = 1 × 10 ¹³ ions / cm ^{2 of} boron by the ion implantation method
The driving for driving is performed at 1150 ° C. for 180 minutes. Next, impurities for channel stop are implanted. Phosphorus 2 × 10 ¹³ ions / cm ² , p for n-type channel stop
For the mold channel stop, boron is added at 4 × 10 ¹³ i
The condition is ons / cm ² . After that, a field oxide film is formed by using a selective oxidation method. The film thickness of the field oxide film is 8000Å. Next, a base diffusion layer is formed. Boron 6 × 10 ¹² ions / cm ² implantation 110
Drive at 0 ° C for 60 minutes.

Next, gate oxidation is performed at 350 Å, and boron is used as a channel dope at 1.8 × 10 ¹¹ ions / cm 2.
^{After 2} implantations, 4000 Å of polycrystalline silicon is deposited. After processing polycrystalline silicon into a predetermined shape, MOS
A high-concentration diffusion layer is formed in the source / drain portion of the transistor. Arsenic is added to the n-type high concentration layer at 7 × 10 ¹⁵ io.
ns / cm ² implantation, 1 × BF ₂ for p-type high concentration layer
10 ¹⁵ ions / cm ² has been applied. The drive is commonly used for n-type and p-type, and is performed at 1000 ° C for 5 minutes. The emitter and collector contact diffusion layers of the bipolar transistor are formed in the same process as the NMOS source = drain diffusion layer. Hereinafter, the wiring layer formation of aluminum or the like is exactly the same as the known semiconductor manufacturing technique.

A facsimile using the sensor IC described above will be described below. In the case of a facsimile, the reading width is required to be at least 21 cm for A4 size paper and at least 30 cm for A3 size paper. This length is currently not large enough to produce a single crystal silicon IC on a single chip. Therefore, a plurality of sensor array chips are connected to form a facsimile reader. As an example, FIGS. 12 and 13 show a cross-sectional configuration diagram and a plan conceptual diagram of a facsimile reader capable of reading up to A3 size paper by connecting 15 chips each having a width of 2 cm. The resolution is assumed to be 200 DPI (dots per inch), and an LED (light emitting diode) is used as a light source.

[0041]

As described above, according to the present invention,
By arranging the charge collecting mechanism of the MIS structure adjacent to the bipolar type sensor, it has become possible to form the barrier which was conventionally fixedly formed by the buried layer or the diffusion layer by applying a voltage. As a result, the buried layer, the deep diffusion layer, and the epitaxial layer are not essential in the photosensor structure, and the manufacturing cost is reduced to about 70% as compared with the conventional example.

The effect of reducing the manufacturing cost is not limited to the photosensor alone, but is also effective for a photosensor array using a bipolar sensor, and also for an integrated circuit in which a CMOS logic circuit is incorporated in the same substrate. There is.

Furthermore, when the integrated circuit according to the present invention is used in a facsimile reader, it contributes to cost reduction of the entire facsimile.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a configuration of an embodiment of a photoelectric conversion device of the present invention.

FIG. 2 is an enlarged view of a control electrode and a base region.

FIG. 3 is an energy band diagram under a control electrode and a base region.

FIG. 4 is an energy band diagram under a control electrode and a base region.

FIG. 5 is an energy band diagram under a control electrode and in a base region.

FIG. 6 is an energy band diagram under a control electrode and a base region.

FIG. 7 is an energy band diagram under a control electrode and in a base region.

FIG. 8 is an example of a readout circuit suitable for a photo sensor according to the present invention.

9 is a timing chart diagram for the circuit of FIG.

FIG. 10 is a sectional view of a sensor of a conventional example.

FIG. 11 is a photosensor readout circuit of a conventional example.

FIG. 12 is a cross-sectional configuration diagram of a facsimile reader unit using the present invention.

FIG. 13 is a plan configuration diagram of a facsimile reader unit using the present invention.

[Explanation of symbols]

Reference Signs List 101 semiconductor substrate such as silicon 102 buried layer 104 epitaxial layer 105 field oxide film 106 deep diffusion layer for collector plug 107 base region main part 108 emitter region 109 shallow p-type high concentration diffusion layer corresponding to part of base region 110 reset MOS Transistor gate electrode 111 Control electrode 112 Depletion layer (potential well) 114 Control electrode aluminum wiring 121 Complete reset p-type MOS transistor

Claims (5)

[Claims] 1. A first-conductivity-type semiconductor substrate, in which carriers generated by receiving light energy are collected, and a signal corresponding to the carrier is output to the first-conductivity-type semiconductor substrate. A second semiconductor region of the first conductivity type that is in contact with the first semiconductor region, and a control electrode capable of controlling the potential via an insulating layer on the semiconductor substrate, adjacent to the first semiconductor region. Photoelectric conversion device. 2. A photosensor array in which a plurality of photoelectric conversion devices according to claim 1 are arranged. 3. A semiconductor device in which at least the photosensor array and the readout circuit according to claim 2 are formed in the same semiconductor substrate. 4. A facsimile device using the semiconductor device according to claim 3 as a reader. 5. The semiconductor device according to claim 3,
The read circuit is an n-type MOS transistor and a p-type MOS
A semiconductor device composed of transistors.