JPH0897393A - Photoelectric converter, line sensor array and semiconductor device - Google Patents

Abstract

PURPOSE: To perform complete nondestructive readout and pure resistance readout without needing transferring capacity by a method where electric charge is accumulated in a gate part of a MOS transistor and the potential of a source of the MOS transistor according to the potential of a diffused layer and a gate electrode is read out as an output. CONSTITUTION: Diffused layers 106 having a conductivity opposite to that of the substrate is formed in a semiconductor substrate 101, the diffused layer 106 is directly connected with a gate electrode 107 of an output MOS transistor via a metal wire 112, and the diffused layer 106 and gate electrode 107 are set to a floating condition. Electric charges of holes or electrons generated by light in the semiconductor substrate 101 are accumulated in a region where the diffused layer 106 is coupled with the electrode 107, and a source potential 104 changing with respect to a potential of the gate electrode 107 generated thereby is read out as an output. Thus, it is possible to perform a complete nondestructive readout and an operation for maintaining a continuous source current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a photoelectric conversion device and a manufacturing method thereof, and more particularly to a photoelectric conversion device and a photoelectric conversion method for accumulating carriers generated by light incidence and reading a signal based on the accumulated carriers. It is a thing.

[0002]

2. Description of the Related Art Conventionally, various types of visible light photoelectric conversion devices, particularly line sensors in which photosensors are arranged in a line, have been proposed and used. There are two main types, CCD type and MOS type.
Among these two, as a document reading sensor for a facsimile, a large number of MOS type sensors in which a switching MOS transistor is individually connected to a photodiode are used. An example of the equivalent circuit diagram is shown in FIG. MOS transistors Tr1, Tr2, ..., T
Photodiodes D1, D2, ..., Dn are connected to the source side of rn, and are applied by applying a gate voltage to the gate electrode.
The S transistor is switching, and the photo signal of the original is obtained from the drain. However, the MOS type line sensor has the following drawbacks.

That is, in a photoelectric conversion device using, for example, a line sensor, a long wiring capacitance due to the source or drain of a MOS transistor is connected to a photodiode and acts as a load at the time of reading, and a large output reduction cannot be avoided. , S / N ratio tends to cause problems. In particular, as the demand for the resolution required of the sensor becomes higher and the resolution becomes higher, the sensor cell,
In other words, the area of the photodiode part is reduced and the carrier charge is reduced, and the S / N ratio becomes more difficult.

In view of these problems, in recent years, Japanese Patent Laid-Open No.
A bipolar type photosensor array as disclosed in Japanese Patent Application Laid-Open No. 0-12759 has been proposed, and an excellent method which has high sensitivity to light and is hardly influenced by wiring capacitance has come to be used.

FIG. 8 shows a sectional structural view thereof. Photosensor array element described above, the holes generated in the photon accumulated in the base portion, of the type which changes the emitter potential by the change of the base potential, BASIS (BA se
S tored type I mage S ensor)
is called. Hereinafter, the above-mentioned photosensor array element will be referred to as BASIS.

Here, referring to FIG.
Is an n-type or n ⁺ -type silicon substrate doped with impurities such as phosphorus (P), antimony (Sb), and arsenic (As), 202 is a buried layer, 203 is a silicon epitaxial layer, and 204 Is a deep diffusion layer that electrically insulates, 2
Reference numeral 05 is an n-type diffusion layer forming a base, 206 is a p-type diffusion layer forming an emitter, and 207 is a reset MO.
An n-type diffusion layer forming a source or drain of S, 20
8 is a reset MOS gate, 209 is a field insulating film, 210 is an interlayer insulating film, and 211 is a metal wiring such as aluminum (Al).

FIG. 9 is an equivalent circuit diagram including the sectional structure diagram of FIG. 8 described above. The sensor transistor 301 is responsible for carrier accumulation by the optical signal hν at the base, and the base reset MOS transistor 302 is for resetting the carrier accumulation. An emitter reset MOS transistor 303 for turning on / off the emitter potential of the sensor transistor 301, a transfer MOS transistor 304 for transferring the photoelectric conversion signal transferred to the emitter of the sensor transistor 301 to the next-stage capacitor CT, and a capacitor CT. The CT reset MOS transistor 305 that resets the accumulated transfer carriers, and the sensor transistor 301 temporarily.
C for accumulating the photoelectric conversion signal transferred to the emitter of
It is composed of T306. A partial cross-sectional structure of this circuit configuration is shown in FIG.

[0008]

By the way, this BAS
When the IS sensor is used as a line sensor, the element area can be reduced even if the number of elements in the array increases, and the output reduction is small even if the element area is reduced.
It has very excellent properties compared to those of the type line sensor. However, the following two problems remain and it is difficult to avoid.

One of them, as shown in FIG. 8, has a basic structure of a bipolar element, so that the buried layer 202 is
In addition, various diffusion layers such as the base 205 and the deep n-type diffusion layer 204 are required, and when a drive circuit is configured by MOS transistors, the chip manufacturing process becomes complicated, and the formation process of the epitaxial layer 203, which is a more expensive process, is performed. Up to need. Therefore, the manufacturing cost is about 30 to 40% higher than that of the MOS type, and there is a cost problem.

The second problem is the problem of the reading method. When the emitter current of the sensor transistor 301 flows, the holes accumulated in the base disappear as a recombination current or an emitter inflow current. Is. If the charge stored in the base is completely non-destructive, the emitter current can be kept flowing continuously, and the load on the emitter can be a pure resistance load. However, the accumulated charges are destroyed at a certain rate, and the emitter current cannot flow continuously.

Therefore, as shown in FIG. 9, the capacitance CT 306 is connected to the emitter of the sensor transistor 301, the photoelectric conversion signal is once transferred to the capacitance CT, and then the output is read. In principle, this transfer capacity is unavoidable, and in order to escape from the influence of the wiring capacity, the above-mentioned transfer capacity must be large. Since the transfer capacity itself is associated with each sensor, the transfer capacity equal to or more than the number of elements of the sensor is required. Even if the sensor area is reduced, the transfer capacity cannot be reduced due to the relationship between the wiring capacity and the transfer capacity, and the transfer capacity array may occupy a larger area than the sensor array. This means an increase in the chip area, which is added as a cost disadvantage.

As described above, the first object of the present invention is to provide a signal amplification mechanism by using a well-known CMOS manufacturing process without using an epitaxial layer or an additional diffusion layer. Is to enable the configuration of an image pickup device including.

A second object is to enable the sensor element to perform a complete nondestructive read-out for the signal charge generated by light, thereby enabling a pure resistance read-out without requiring a transfer capacitance. Is.

A third object is to use no buried layer,
Only by controlling the surface potential, carriers generated by light can be collected in the specific diffusion layer.

[0015]

In order to achieve the above-mentioned object, a first invention according to the present application is such that a metal is used for a gate electrode of a first MOS type transistor installed at a different location with respect to a diffusion layer of a predetermined conductivity type. A gate storage type image pickup device characterized in that the potential of the source of the MOS transistor according to the potentials of the diffusion layer and the gate electrode is read as an output by directly connecting the wiring to make the diffusion layer and the gate electrode in a floating state It is a photoelectric conversion device. In addition, as a component of the configuration, a second MOS transistor that resets the charges accumulated in the diffusion layer and the gate electrode is arranged, and a mechanism is provided so that an optical signal can be repeatedly read within a fixed time.

The second invention has a semiconductor substrate, a well of a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate, and a source of conductivity type opposite to the semiconductor substrate in the semiconductor substrate. 2MOS transistors, a first MOS transistor having a source having a conductivity type opposite to that of the well in the well, and a potential control electrode via an oxide film on the semiconductor substrate, and light generated between the potential control electrode and the semiconductor substrate. The charge of the reaction depletion layer is transferred to the source of the second MOS transistor and the metal wiring portion of the gate of the first MOS transistor and output from the source of the first MOS transistor.

[0017]

With the structure according to the first aspect of the invention, the output signal is
Is output as the source potential of the MOS transistor,
A complete non-destructive read-out and, accordingly, an action of holding a persistent source current is possible.

Further, the output element and the reset element are MOS
The use of the type transistor does not require a high-concentration diffusion layer at a deep position in the cross-sectional direction unlike a bipolar transistor and does not require an epitaxial layer, and thus has an effect of enabling significant process omission.

Further, according to the structure of the second invention, the potential control electrode is provided beside the storage diffusion layer directly connected to the gate electrode, so that the charges generated by the light hν can be efficiently collected and the photosensor manufacturing process can be performed. It has the effect of improving the sensitivity of the sensor without increasing it.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1A is a cross-sectional structure diagram according to this embodiment, and FIG. 1B is an equivalent circuit thereof. First, 101 is a semiconductor substrate of a specific conductivity type such as silicon, 102 is a well of a conductivity type opposite to the semiconductor substrate 101, and 103 is a well 102.
Of the output MOS transistor 123 of the opposite conductivity type to that of the well 102
Output MOS of the conductivity type opposite to that of the well 102 disposed inside
The source of the transistor 123, 105 is the drain of the reset MOS transistor 121 of the opposite conductivity type to the base 101, 106 is the source and carrier accumulation region of the reset MOS transistor 121 of the opposite conductivity type to the base 101, and 107 is made of polycrystalline silicon or the like. Is a gate electrode of the output MOS transistor 123, and 108 is a gate electrode of the reset MOS transistor 121 also made of polycrystalline silicon or the like.

Further, 109 is a control electrode for controlling the surface potential of the semiconductor substrate 101 made of polycrystalline silicon or the like, and 110 is silicon dioxide (SiO2).
Etc., a field insulating film 111, an interlayer insulating film made of silicon dioxide, etc. 112, a carrier accumulation region made of aluminum (Al) etc. and the output MOS transistor 12
The metal wiring connecting the gates of 1 and 113 is aluminum (A
l) and the like, a power wiring 114, a metal wiring 114 for sending a control signal to the potential control electrode 109, and a drain reset field effect (MOS) transistor 1
22 is a gate electrode, and 116 is a drain diffusion layer of the drain reset field effect transistor 122.

FIG. 1B is an equivalent circuit diagram of the cross-sectional configuration diagram. 120 is disposed below the potential control electrode 109 that receives photons and accumulates carriers,
A photosensor having a MOS diode structure that controls the main part of photoelectric conversion, 121 is a reset MOS transistor of a second field effect transistor that resets the accumulated carriers of the photosensor 120, and 122 is a drain reset MOS of a third MOS transistor that makes the output MOS transistor 123 conductive. Transistor 123 is an output MOS transistor of the first field effect transistor that outputs accumulated carriers. Therefore, the metal wiring 112 and the gate line 107 of the output MOS transistor 123 coincide with each other, and the power supply line 113 and the drain resetting MOS transistor 12 are aligned.
It also coincides with the second drain 116.

Next, the operation principle of the photoelectric conversion device having the above-mentioned structure and a simple manufacturing process will be described.

In considering the operation principle, the semiconductor substrate and the internal diffusion layer are assumed as follows in order to facilitate the explanation. That is, the semiconductor substrate 101 is an n-type silicon single crystal substrate, the well 102 is a p-type well, and an output MOS.
The drain 103 and the source 104 of the transistor 123
Is an n-type diffusion layer, and the drain 105 and the source 106 of the reset MOS transistor 121 are p-type diffusion layers. Here, the source diffusion layer 106 also serves as the source region of the reset MOS transistor and the p region of the photodiode.

FIG. 2 shows an enlarged view of the potential control gate 109 and the reset PMOS. here,
A positive potential is applied to the n-type semiconductor substrate 101, for example, 5 as an example.
Consider a state in which a potential of V is applied and a potential of 0V is applied to the potential control gate electrode 109. in this case,
The depletion layer spreads in the region shown by the dotted line in FIG. 2, and along the direction (a) of the vertical line of the semiconductor substrate 101, the conduction band Ec and the valence band Ev are shown in the left diagram of FIG. Such band bending occurs. Then, when the light hν enters the depletion layer region, electron-hole pairs are generated as shown in the left diagram of FIG. 3- (1), and the holes are on the surface side of the semiconductor substrate 101, that is, the potential control. Collected on the side of the electrode 109, the electrons escape to the lower part of the substrate 101, that is, the lower side in FIG. At this time, it is assumed that the gate electrode 108 of the reset MOS 121 is in the off state at 5V, the source region 106 is connected only to the gate electrode 107 of the output MOS transistor 123, and the source region 106 is in the floating state. If the initial potential of the source region 106 is near 0 V, the potential is lower than the interface potential χ _S immediately below the control electrode 109, and the holes immediately below the control electrode 109 flow into the source region 106 of the reset MOS 121.

Since the source region 106 and the gate electrode 107 of the output MOS are in a floating state, the potential of the Fermi level EF as shown by ↓ in the right diagram of FIG. Rises. Quantitatively, assuming that the amount of change in the potential of the source region 106 is ΔV _S and the amount of charge of holes that flowed in is Q _P , ΔV _S = Q _P / (C _1S + C _20X ) ... Equation (1) Here, C _{1S is} the source diffusion capacitance of the reset MOS, C _20X is the gate capacitance of the output MOS.

As described above, a certain amount of holes are generated in the source region 1.
When stored in 06, as shown in the right figure of FIG. 3- (2),
Interfacial potential χ under control electrode 109
_The potentials of _S and the source 106 become the same potential. Up to this point, the width W of the depletion layer just below the control electrode 109 is equal to
-(1), the light quantity h does not change as shown in FIG. 3- (2).
Continue to collect holes efficiently according to ν.

When the holes generated by the light hν are further collected in this state, the interface potential χ _S immediately below the control electrode 109 and the source 106 potential are kept at the same potential, while ↓ in the right diagram of FIG. 3- (2). As shown in (3), the holes are accumulated in both the region directly below the control electrode 109 and the source region 106. At this time, in the depletion layer immediately below the control electrode 109, the width of the depletion layer shrinks from W to W ′ within the range in which the interface maintains the strong inversion state. The potential change in the source region at this time is ΔV _S = Q _P / (C _1S + C _20X + C _3D ) .. (2) where C _3D is the depletion layer capacitance directly below the control electrode 109, and the potential rises slowly. I will do it.

In this way, after a certain accumulation time,
The potential relationship is in the state shown in Fig. 3- (3). From this state, the potential of the control electrode 109 is 0V
To +5 V, which has the same potential as the base 101. When the work function difference between the control electrode 109 and the semiconductor substrate 101 is ignored, the interface potential χ _S of the control electrode 109 also becomes 5 V, and the potential increase shown by ↓ in the right diagram of FIG. As a result, the potential distribution changes to the state of FIG. 3- (4), and the holes just below the control electrode 109 flow into the source region 106.

Here, of the holes accumulated directly under the control electrode 109, the problem is how much of the holes flow into the source region 106. However, as shown in FIG. If a metal wiring 114 for applying a potential to the electrode 109 is arranged in a position as far as possible from the source region 106, a potential gradient of the interface potential potential χ _S is transiently generated in the horizontal direction, and the mobility of polycrystalline silicon and single crystal silicon is increased. From the difference between the control electrode 10
The movement of holes at the single crystal interface is carried out more quickly than the movement of charges on the 9 side, and almost all the holes are transferred to the source region 106.
Flow into.

As a result, the potential change in the source region 106 with respect to the total potential Q _P of generated holes is ΔV _S = Q _P / (C _1S + C _20X ) ... Equation (3) The same relationship is maintained.

This means that the potential of the source 106 of the reset MOS transistor 121 and the output MOS transistor 123 are irrespective of the magnitude of the charge Q _P generated by light.
It means that the potential of the gate 107 is determined only by the capacitance. Therefore, the potential of the gate 107 of the output MOS 123 does not have an extreme bending point, and V _2G ∝ Q _P ∝ I _L · t _S (Equation (4)) where V _2G ;
Potential I _L ; light intensity t _S ; storage time.

Thus, finally, the reset MOS
When 0 V is applied to the gate electrode 108 of the transistor 121 to turn on the reset MOS transistor 121, the source region 106 is near 0 V (0.5 V to 0.6 V).
The potential returns to V) (Fig. 3- (5)).

After that, the potential of the control electrode 109 is returned to 0 V, and the gate electrode 10 of the reset MOS 121 is reset.
If the reset MOS transistor 121 is returned to the OFF state by applying the voltage 5V to the circuit 8, the initial state shown in FIG.
Will be reproduced.

Here, paying attention to each operating point other than the output M0S123, the change in potential is as follows. In the timing chart shown by each 1 of each electrode in FIG. 5, the fluctuation of the potential V _2G of the gate electrode 107 during the light accumulation period is connected to the source 106 of the reset MOS 121, and the potential of the source 106 of the reset MOS 121 is changed. It has the same potential as V _1S . Therefore, the potential changes due to the photovoltaic current,
As described above, the relationship of V _2G = V _1S = Q _P / (C _1S + C _20X ) ... Equation (5) holds.

During this accumulation period (when the potential control electrode 109 is in the low potential period), the drain of the output MOS 123 is the drain reset MOS 122 inserted between the output MOS 123 and the power supply, as shown in FIG.
Since the gate electrode of the drain reset MOS 122 has a low potential, the drain reset MOS 122 is in an off state, so that no current flows. After the potential control electrode 109 is set to the same potential as the semiconductor substrate 101 (high potential pulse in the figure) to end the storage operation, the gate potential of the drain reset MOS 122 on the drain side of the output MOS 123 is shifted to a high level, and the output MOS transistor 123 is output. Is turned on and output. As a result, a voltage near the supply voltage is supplied to the drain of the output MOS transistor 123, and a drain current according to the gate potential of the output MOS transistor flows.

Considering the potential of the source 104 of the output MOS transistor 123, no matter whether the load is a pure resistance load or a capacitive load, the source-follower type load state is established, and the source of the output MOS 123 is connected. 10
The potential of 4 becomes approximately V _2G −V _2th (where V _2th is the threshold voltage of the output MOS 123).

Here, considering that the photoelectric conversion devices as shown in FIG. 1 are arranged in a line on a line and the outputs are individually taken out as a line sensor array, the source 104 of the output MOS transistor 123 directly outputs a common output. It can be spliced to a line (Fig. 6). In this semiconductor device, the completion of reading is done by drain reset MOSs 1221, 1222.
The potential of the gate electrode 115 of 122n is lowered to the low potential side, and the output MOS transistors 1231, 1232, ...
When the drain power supply of 3n is turned off, the current does not flow from the output MOS 123, and if the reset MOS 124 is connected to one place of the common output line as a logic circuit, the source potentials of the common output line and the output MOS 123 are near 0V. It can be dropped and guarantees stable operation. Regarding resetting of the potential of the gate 107 of the output MOS 123, after resetting the common output line, the gate electrode of the gate reset MOS 121 may be set to a low potential and the timing may be shifted. Then, as shown in FIG. 5, the charge of holes of each element is output immediately before turning on the gate electrode of the common output line reset MOS 124, and then the reset MOS 124 is turned on to reset the common output line. To do.

In the above description of the operation, with respect to a specific 1 bit, accumulation → reading → reset is performed in time series. However, if the accumulation time is sufficiently long, reading of another bit → reset occurs during the accumulation period. All you have to do is sequentially.

What is important in the above description is that even if the load on the common output line is a resistive load, the output MOS 12
The charge due to the holes accumulated in the gate 107 of No. 3 is not destroyed, and complete nondestructive readout is possible. When a bipolar transistor is replaced in the output MOS 123 portion, holes accumulated in the base corresponding to the gate 107 of the output MOS 123 are injected into the emitter or partially disappear as a recombination current. Will end up. Therefore, in the case of a bipolar transistor, the load must be a capacitive load, which imposes a large restriction on the read circuit.

As described above, it can be understood that the source terminal 104 of the output MOS 123 becomes the output terminal from the potential relationship of each terminal as described above. Further, the output reduction due to the parasitic capacitance such as the wiring capacitance is hardly divided by the complete nondestructive reading, and can be suppressed to the minimum.

The manufacturing process of one embodiment using the present invention will be briefly described below with reference to FIG.

Initially, the concentration of the n-type semiconductor substrate 101 is selected, but this is an important parameter. The spread of the depletion layer immediately below the control electrode 109 is determined by the substrate concentration and the thickness of the gate oxide film. As an example, the depletion layer width required for a constant wavelength type line sensor having a light source wavelength of 550 nm used in a facsimile or the like is as follows. The absorption coefficient of silicon for light with a wavelength of 550 nm is a = 6.
It is 9 × 10 ³ cm ⁻¹ . Therefore, 95% of the light incident with a width of 4 μm is absorbed in silicon. Using this as a guide, the substrate concentration may be selected so that the depletion layer spreads by 4 μm or more.

In the strong depletion state (non-equilibrium) as shown in FIG. 3- (1), assuming that the gate oxide film 110 is 300,
If the concentration of the semiconductor substrate 101 is within 3 to 4 × 10 ¹⁴ cm ⁻¹ , a depletion layer of 4 μm or more, as shown by the dotted line in FIG.
It is confirmed to be formed immediately below the control electrode 109. Dry etching is used for etching, and chlorine (Cl ₂ ), methane difluoride, and sulfur hexafluoride (SF ₆ ) are used as reaction gases.

Next, the well 102 is formed by ion implantation or diffusion (FIG. 4A), and the source 104 and drain 103 of the n-type MOS transistor are formed by ion-implantation. Arsenic (As) 7
Implant with a dose amount of × 10 ¹⁵ / cm ² . Furthermore, p-type M
The source 106 and the drain 105 of the OS transistor are formed by an ion-implantation method. Boron difluoride is implanted at a dose of 1 × 10 ¹⁵ / cm ² ((b) in FIG. 4).

Next, an interlayer insulating film 111 is deposited 7000 by the atmospheric pressure DVD method, and a heat treatment is performed at a temperature of 950 ° C. for 10 minutes. Next, a contact hole is opened using a photolithography method. Dry etching is used for etching, and carbon tetrafluoride and methane trifluoride are used as reaction gases. Further, aluminum is deposited 8000, and aluminum wirings 112, 113 and 114 are formed by the photolithography method ((c) of FIG. 4).

Through the above steps, an element having a sectional structure as shown in FIG. 1 is formed. When a drive circuit for the above-mentioned elements is formed in the same substrate 101, a CMOS
If it is formed by a circuit, the light receiving element and the drive circuit can be formed in the same step without any additional step.

[0048]

As described above, according to the present invention,
By accumulating charges in the gate portion of the MOS transistor, it becomes possible to perform non-destructive reading and read without using the transfer capacitance, so that the chip size of the element can be reduced and an inexpensive sensor can be provided.

Further, as compared with the bipolar element, an expensive process such as an epitaxial layer is not required, and the cost can be reduced by about 30% as compared with the BASIS element which is the prior art.

Further, according to the present invention, accumulation, reading,
Since each reset operation can be performed by controlling the potential of each electrode, the units can be used as a line sensor when the units are arranged in a line and the operations between the units are performed in time series.

Further, according to the present invention, since the sensor portion can be manufactured by the well-known process of manufacturing the CMOS transistor, the driving logic circuit can be formed in the same substrate without adding any process. it can.

Further, according to the present invention, a read MOS
N transistors with the same size and high conductance
It becomes possible to select the type MOS transistor.

Further, according to the present invention, it is possible to use the diffusion layer for accumulation and the source of the reset MOS transistor as a common region because of the area reduction.

Further, according to the present invention, it is possible to use an n-type silicon substrate and to use a p-channel type MOS transistor for reset in order to drive it with a versatile positive potential power source.

Further, according to the present invention, by providing the potential control electrode having the MOS diode structure, the light having a wavelength of 550 nm can be emitted at 90% without using a buried layer or the like.
% Or more holes can be collected in the diffusion layer.

Further, according to the present invention, the potential control electrode can be formed simultaneously with the gate electrode, and can be formed without increasing the cost at all.

Further, according to the present invention, due to the difference in the amount of movement between polycrystalline silicon and single crystal silicon, simply arranging the metal connection of the potential control electrode on the opposite side of the storage diffusion layer transiently affects the integrated charge. A potential tendency can be given and holes can be efficiently accumulated.

Further, according to the present invention, it is suitable for a reading reader of a facsimile in which an inexpensive sensor is required,
Useful for low cost facsimile.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view and an equivalent circuit diagram of a photoelectric conversion element according to an embodiment of the present invention.

FIG. 2 is a partially enlarged sectional view of FIG. 1 according to the present invention.

FIG. 3 is a potential band diagram during each operation for explaining the operation of the embodiment according to the present invention.

FIG. 4 is a sectional view of each manufacturing process according to an embodiment of the present invention.

FIG. 5 is a timing chart explaining the operation of the embodiment according to the present invention.

FIG. 6 is a circuit diagram of an application example according to an embodiment of the present invention.

FIG. 7 is a conceptual diagram of a MOS type line sensor in the prior art.

FIG. 8 is a structural cross-sectional view of a base storage type image pickup device in the prior art.

FIG. 9 is an equivalent circuit diagram of a read circuit of a base storage type image pickup device in the prior art.

[Explanation of symbols]

101 semiconductor substrate 102 well 103 drain of output MOS transistor 104 source of output MOS transistor 105 drain of reset MOS transistor 106 source of reset MOS transistor 107 gate electrode of output MOS transistor 108 gate electrode of reset MOS transistor 109 potential control electrode 110 field oxidation Film 111 Interlayer insulating film 112, 113, 114 Metal wiring such as aluminum 120 Photoelectric conversion element 121 Reset MOS transistor 122 Drain reset MOS transistor 123 Output MOS transistor 201 Silicon substrate 202 Buried layer 203 Silicon epitaxial layer 204 Deep diffusion layer 205 Diffusion layer (base) Region) 206 diffusion layer (emitter region) 2 7 diffusion layer (reset MOS transistor source and drain) of 208 gate electrode 209 a field oxide film of the reset MOS transistor 210 interlayer insulating film 211 metal wires

Claims (13)

[Claims] 1. A semiconductor substrate has a diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and the diffusion layer and a gate electrode of a first field effect transistor arranged on the semiconductor substrate are metal. The first field-effect type device having a wired structure, storing charges of holes or electrons generated by light in the semiconductor substrate in a connected region of the diffusion layer and the gate electrode, and causing the accumulation action. A source electric potential that changes according to a change in the electric potential of the gate electrode of the transistor is output, and a mechanism for discharging the accumulated charge in a second field effect transistor different from the first field effect transistor is provided. And a photoelectric conversion device. 2. A line sensor array comprising a plurality of photoelectric conversion devices according to claim 1 arranged in the same semiconductor substrate. 3. A semiconductor device in which, in addition to the line sensor array according to claim 2, a logic circuit for driving the line sensor array is incorporated in the same semiconductor substrate. 4. A facsimile apparatus, wherein the semiconductor device according to claim 3 is used as an image reading sensor for reading a document. 5. The photoelectric conversion device according to claim 1,
A photoelectric conversion device, wherein the first field-effect transistor for reading having a gate for accumulating charges is composed of an n-type MOS transistor. 6. The photoelectric conversion device according to claim 1,
The photoelectric conversion device, wherein the diffusion layer and the source region of the second field effect transistor are formed of the same diffusion layer. 7. The photoelectric conversion device according to claim 1,
A photoelectric conversion device, wherein the semiconductor substrate is an n-type silicon substrate, and the second field effect transistor is a p-type MOS transistor. 8. The photoelectric conversion device according to claim 1, wherein
A potential control mechanism of a semiconductor surface having a MOS diode structure is provided in a region adjacent to the diffusion layer, which is metal-wired to the gate electrode of the first field effect transistor, to prevent holes or electrons generated by light. A photoelectric conversion device, characterized in that one is accumulated in the diffusion layer. 9. The photoelectric conversion device according to claim 7,
The metal wiring portion of the electrode region for controlling the potential,
A photoelectric conversion device, wherein the photoelectric conversion device is arranged at a position opposite to a gate electrode of the first field effect transistor with reference to the diffusion layer. 10. The semiconductor substrate has a diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and the diffusion layer and the gate electrode of the first field effect transistor arranged on the semiconductor substrate are metal. A semiconductor surface potential control mechanism having a MOS diode structure is provided in a region adjacent to the diffusion layer, which has a wired structure, and diffuses holes or electron charges generated by light in the semiconductor substrate. Accumulating in the metallized area of the layer and the gate electrode,
In the method of manufacturing a photoelectric conversion device in which the accumulated charges are output from the source of the first field effect transistor, the electrode part for controlling the potential is formed in the same step as the gate electrode of the first field effect transistor. And a method for manufacturing a photoelectric conversion device. 11. A second MOS having a semiconductor substrate, a well of a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate, and a source of a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate.
A first MOS transistor having a source of a conductivity type opposite to that of the well, and a potential electrode on the semiconductor substrate via an oxide film,
The charge of the photoreaction depletion layer generated between the potential electrode and the semiconductor substrate is transferred to the metal wiring portion of the source of the second MOS transistor and the gate of the first MOS transistor and output from the source of the first MOS transistor. And a photoelectric conversion device. 12. The photoelectric conversion device according to claim 11, wherein the second MOS transistor includes a gate electrode supplied with a control signal for discharging the charge of the photoreaction depletion layer. 13. The photoelectric conversion device according to claim 11, wherein a third MOS transistor connected to the drain of the first MOS transistor and having the same conductivity type as the drain of the first MOS transistor is provided in the well.