CN111448664B - Charge modulation element and solid-state image pickup device - Google Patents
Charge modulation element and solid-state image pickup device Download PDFInfo
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- CN111448664B CN111448664B CN201880078989.4A CN201880078989A CN111448664B CN 111448664 B CN111448664 B CN 111448664B CN 201880078989 A CN201880078989 A CN 201880078989A CN 111448664 B CN111448664 B CN 111448664B
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
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- H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
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Abstract
The device is provided with: a p-type photoelectric conversion layer (11); an n-type surface embedded region (13) embedded in the upper part of the photoelectric conversion layer (11); an n-type modulation region (14) embedded on the upper surface side of the photoelectric conversion layer (11) and forming a photodiode together with the photoelectric conversion layer (11); p-type potential control regions (15 a, 15 c) that divide the modulation region (14) into a plurality of regions, the potential control regions being disposed in the divided regions; and n-type charge accumulation regions (17 a, 17 c) for temporarily accumulating signal charges generated by the photodiodes and transferred along mutually independent transfer paths, respectively. The transmission paths are selected by controlling the potentials of the modulation region (14) and the surface buried region (13) by a path selection signal as a pulse voltage applied to the potential control regions (15 a, 15 c).
Description
Technical Field
The present invention relates to a charge modulation element capable of a time of flight (TOF) operation and a solid-state imaging device in which a plurality of charge modulation elements are arranged as imaging pixels, and more particularly, to a solid-state imaging device capable of a high-speed TOF operation.
Background
A photon mixer that performs an operation similar to that of a TOF type sensor has been proposed (see patent document 1). In the invention described in patent document 1, in order to inject a majority carrier current into p - A semiconductor substrate is provided with: a pair of p arranged separately + The optical device includes a pair of injection contact regions and a pair of detection unit regions disposed adjacent to positions outside the pair of injection contact regions and configured to collect photocurrent. A pair of detection part regions are respectively and locally configured by a pair of n - The semiconductor region of the type surrounds. n is n - Semiconductor region pass through p - Forming a pn junction between the semiconductor substrates to make n - The narrow region outside the semiconductor region is depleted and operated.
According to the principle of operation of the photon mixer described in patent document 1, it is difficult to operate a TOF type sensor targeting ultra-high speed in the sub-nanosecond range. That is, by alternately injecting majority carrier current from a pair of injection contact regions to p - The electric field control performed by the semiconductor substrate is accompanied by a great capacitance change, and is inefficient. In the invention described in patent document 1, p is - The occupied area of the neutral region in the semiconductor substrate is positively large. In the invention described in patent document 1, a slow carrier component that moves at a diffusion rate in the neutral region is used, and therefore, the slow component affects and makes it difficult to perform an ultra-high speed operation.
In the photon mixer described in patent document 1, a majority carrier current is injected from an injection contact region to p - The operation of the semiconductor substrate also has a problem of increased power consumption.
Prior art literature
Patent literature
Patent document 1: japanese patent application laid-open No. 2011-86904
Disclosure of Invention
Technical problem to be solved by the invention
In view of the above-described problems, an object of the present invention is to provide a charge modulation element capable of performing TOF-type high-speed operation with low power consumption, and a solid-state imaging device in which a plurality of charge modulation elements are arranged as imaging pixels.
Solution for solving the technical problems
In order to achieve the above object, a first aspect of the present invention provides a charge modulation element comprising: (a) a photoelectric conversion layer of a first conductivity type; (b) A surface buried region of the second conductivity type buried in a part of an upper portion of the photoelectric conversion layer, and forming a photodiode with the photoelectric conversion layer; (c) A modulation region of the second conductivity type, which is buried in a portion of the upper portion of the photoelectric conversion layer on the upper surface side of the surface buried region of the upper portion of the photoelectric conversion layer, and which forms a portion of the structure of the photodiode together with the photoelectric conversion layer, the modulation region having an impurity density lower than that of the surface buried region; (d) A potential control region dividing the modulation region into a plurality of regions with a center of the modulation region as a center of polar coordinates, the potential control regions being respectively arranged in the divided regions, the potential control region being of a first conductivity type, and an impurity density of the potential control region being higher than an impurity density of the photoelectric conversion layer; and (e) a charge accumulation region of the second conductivity type, which is disposed at a plurality of positions adjacent to the potential control region on the outer peripheral side of each of the divided regions, is separated from the potential control region, and temporarily accumulates signal charges generated by the photodiodes and transferred along mutually independent transfer paths, respectively. In the charge modulation element according to the first aspect of the present invention, the transmission path is selected by controlling the potentials of the modulation region and the surface-buried region by the path selection signal as the pulse voltage applied to the potential control region. Here, the first conductivity type and the second conductivity type are opposite conductivity types to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type.
A gist of a second aspect of the present invention is a solid-state imaging device in which (a) a pixel array section in which a plurality of pixels are arranged and (b) a peripheral circuit section that drives the pixels and processes signals from the pixels are integrated on the same semiconductor chip, the pixels having: a photoelectric conversion layer of a first conductivity type; a surface buried region of the second conductivity type buried in a part of an upper portion of the photoelectric conversion layer, and forming a photodiode with the photoelectric conversion layer; a modulation region of the second conductivity type, which is buried in a portion of the upper portion of the photoelectric conversion layer on the upper surface side of the surface buried region of the upper portion of the photoelectric conversion layer, and which forms a portion of the structure of the photodiode together with the photoelectric conversion layer, the modulation region having an impurity density lower than that of the surface buried region; a potential control region dividing the modulation region into a plurality of regions with a center of the modulation region as a center of polar coordinates, the potential control regions being respectively arranged in the divided regions, the potential control region being of a first conductivity type, and an impurity density of the potential control region being higher than an impurity density of the photoelectric conversion layer; and a second-conductivity-type charge accumulation region disposed at a plurality of positions adjacent to the potential control region on the outer peripheral side of each of the divided regions, respectively spaced apart from the potential control region, and temporarily accumulating signal charges generated by the photodiodes and transferred along mutually independent transfer paths, respectively. In each of the pixels of the solid-state imaging device according to the second aspect of the present invention, the potentials of the modulation region and the surface-embedded region are controlled by a path selection signal as a pulse voltage applied to the potential control region, and the transmission paths of the pixels are selected.
Effects of the invention
According to the present invention, a charge modulation element capable of performing TOF type high-speed operation with low power consumption and a solid-state imaging device in which a plurality of charge modulation elements are arranged as pixels for imaging can be provided.
Drawings
Fig. 1 is a schematic plan view schematically illustrating a configuration of a part of a planar pattern of a pixel of a solid-state imaging device according to a first embodiment of the present invention, omitting (transmitting) an interlayer insulating film shown in fig. 2.
Fig. 2 is a schematic structural view as viewed from a cross section corresponding to the II-II direction of fig. 1, but note that the structure of the planar pattern of fig. 1 does not correspond entirely with respect to the interlayer insulating film or the like.
Fig. 3 is a circuit diagram illustrating an outline of a readout circuit formed in a pixel of the solid-state image pickup element according to the first embodiment.
FIG. 4 is a graph shown with thick solid and dashed lines showing the horizontal direction (IV) along FIG. 2 A -IV A Direction), while the curves of the thin solid and dashed lines show the potential distribution at the level of fig. 2 along IV B -IV B A graph of the potential distribution at the level of the direction.
Fig. 5 is a diagram showing a potential distribution in a pixel of the solid-state image pickup device according to the first embodiment at a position along the longitudinal direction (V-V direction) of fig. 2.
Fig. 6 is a schematic cross-sectional view of a part of a pixel of a solid-state imaging device according to a modification of the first embodiment of the present invention.
Fig. 7 is a diagram showing a potential distribution in a pixel of the solid-state image pickup device according to the first embodiment at a position along the longitudinal direction (VII-VII direction) of fig. 6.
Fig. 8 is a schematic plan view schematically illustrating the structure of a part of a planar pattern of a pixel of a solid-state imaging device according to a second embodiment of the present invention through an interlayer insulating film or the like.
Fig. 9 is a schematic configuration view as seen from the direction IX-IX of fig. 8.
Fig. 10 is a schematic plan view schematically illustrating the structure of a part of a planar pattern of a pixel of a solid-state imaging device according to a third embodiment of the present invention through an interlayer insulating film or the like located at an upper layer.
Fig. 11 is a schematic configuration view as seen from the direction IX-XI of fig. 10.
Fig. 12 is a schematic plan view illustrating an outline of a layout on a semiconductor chip of a solid-state image pickup element according to a third embodiment.
Fig. 13 is a timing chart illustrating the operation of the four-output charge modulation element according to the third embodiment.
Fig. 14 is a schematic plan view schematically illustrating the structure of a part of a planar pattern of a pixel of a solid-state imaging device according to a fourth embodiment of the present invention through an interlayer insulating film or the like located at an upper layer.
Fig. 15 is a schematic configuration view as seen from the XV-XV direction in fig. 14.
Fig. 16 is a schematic plan view schematically illustrating the structure of a part of a planar pattern of a pixel of a solid-state imaging device according to a modification of the fourth embodiment of the present invention through an interlayer insulating film or the like located at an upper layer.
Fig. 17 is a schematic configuration view as seen from the XVII-XVII direction of fig. 16.
FIG. 18 is a solid line showing XVIII along FIG. 17 A -XVIII A The potential distribution at the horizontal level of the direction, while the dashed line shows XVIII along FIG. 17 B -XVIII B A graph of the potential distribution at the horizontal level of the direction.
Fig. 19 is a schematic configuration diagram (one of) illustrating a cross-sectional configuration of a pixel of a solid-state image pickup device according to another embodiment of the present invention.
Fig. 20 is a schematic configuration diagram (second) illustrating a cross-sectional configuration of another pixel of the solid-state imaging device according to the other embodiment.
Fig. 21 is a schematic configuration diagram (third) illustrating another cross-sectional configuration of a pixel of a solid-state imaging device according to another embodiment.
Fig. 22 is a schematic configuration diagram (fourth) illustrating a cross-sectional configuration of another pixel of the solid-state imaging device according to the other embodiment.
Fig. 23 is a schematic configuration diagram when viewed from a cross section corresponding to the XXIII-XXIII direction of a pixel of the solid-state image pickup device according to the other embodiment shown in fig. 22.
Fig. 24 is a schematic configuration diagram (fifth) illustrating a cross-sectional configuration of another pixel of the solid-state imaging device according to the other embodiment.
Fig. 25 is a schematic configuration diagram when viewed from a cross section corresponding to the XXV-XXV direction of a pixel of the solid-state imaging device according to another embodiment shown in fig. 24.
Fig. 26 is a schematic diagram illustrating first to fourth quadrants as a basis of arrangement of potential control regions for explaining a planar layout of potential control regions of pixels of a solid-state image pickup device according to first to fourth embodiments of the present invention.
Fig. 27 is a schematic configuration diagram (sixth) illustrating a cross-sectional configuration of another pixel of the solid-state imaging device according to the other embodiment.
Detailed Description
Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and it should be noted that the relationship of thickness to planar dimensions, the ratio of thicknesses of the layers, and the like are different from the actual case.
For example, in the description of the first to fourth embodiments of the present invention, the first quadrant Q1, the second quadrant Q2, the third quadrant Q3, and the fourth quadrant Q4 are defined as illustrated in fig. 26, and the arrangement positions of the potential control regions are described, but the description of the potential control regions into four quadrants is merely a definition for convenience. The method of dividing the region shown in fig. 26 is divided into four parts with respect to the coordinate center of the polar coordinate system, but more generally, k may be a positive integer of 2 or more, and the region of the polar coordinate system may be divided into k parts with respect to the coordinate center, so as to control the transmission paths of k signal charges. That is, in the description of the first to fourth embodiments, the topology of the fourth rotational symmetry is exemplified, but it should be understood that the topology can be applied to the k rotational symmetries more generally from the gist of the following description. Accordingly, the topology, orientation, position, number of positions, thickness, and size of the specific planar arrangement should be determined with reference to the gist of the technical idea of the present invention that will be apparent from the following description.
In the description of the drawings below, the element separation insulating film, the field insulating film, and the like are not illustrated, and the interlayer insulating film is not illustrated except fig. 2. The surface wiring of the present invention naturally includes a multilayer wiring structure, but the display of a complicated structure is omitted. These drawings are omitted for convenience in order to clarify the gist of the present invention and simplify the description. It is assumed that a structure such as an element separation insulating film known to those skilled in the art is appropriately added within an obvious range at the time of reading. The drawings include, of course, portions having different dimensional relationships and ratios from each other.
The first to fourth embodiments described below are examples of an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention is not limited to the following materials, shapes, structures, arrangements, and the like of the respective members and the like constituting the solid-state image pickup apparatus. In the following description, the case where the first conductivity type is p-type and the second conductivity type is n-type will be described by way of example, but the conductivity types may be selected in an inverse relationship, the first conductivity type being n-type and the second conductivity type being p-type. The expression "superscript" of +or-attached to n and p means a semiconductor region having a relatively higher or lower impurity density than a semiconductor region not labeled with +and-respectively. The technical idea of the present invention can be modified variously within the technical scope described in the claims.
(first embodiment)
A pixel array portion of a solid-state imaging device (two-dimensional image sensor) according to a first embodiment of the present invention has a large number of pixels Xij (i=1 to m; j=1 to n; m and n are positive integers of 2 or more, respectively) arranged in a two-dimensional matrix. Fig. 1 shows a plane pattern of an imaging region of a pixel Xij as a representative example thereof. The pixel Xij shown in fig. 1 receives an optical signal incident through a light shielding opening of a light shielding film, and converts the optical signal into a signal charge. In the region defined by the first quadrant Q1, the second quadrant Q2, the third quadrant Q3, and the fourth quadrant Q4 defined in fig. 26 as described above, four first conductivity types (p + Type) potential control regions 15a, 15b, 15c, 15d. The four potential control regions 15a, 15b, 15c, 15d are buried in a modulation region of the second conductivity type (n-type) as shown in FIG. 2Upper part of the domain 14.
As can be seen from fig. 1, four potential control regions 15a, 15b, 15c, 15d are spaced apart from each other, and are buried in the modulation region 14 as independent similar planar patterns, and the p-type well region (p-well) 12 surrounds the periphery of the modulation region 14. In fig. 1, the edge on the inner peripheral side of the p-well 12 is shown by a broken line (hidden line) denoted by reference numeral 12i, but as can be seen from fig. 2, the outer periphery of the modulation region 14 extends into the upper portion on the inner peripheral side of the p-well 12. In fig. 8, 10, 16, and the like, the edge 12i on the inner peripheral side of the p-well 12 is also shown by a broken line. As in the structures of fig. 8, 10, 16, etc., the inner peripheral edge 12i of the p-well 12 may be spaced from the outer peripheral side of the modulation region 14, or the inner peripheral edge 12i of the p-well 12 may be aligned with the outer periphery of the modulation region 14. Further, although the element isolation insulating film may be buried in the upper portion of the p-well 12 by a Shallow Trench Isolation (STI) technique or the like, the structure of the element isolation insulating film or the like known to those skilled in the art is omitted in fig. 2 as described above.
As is clear from fig. 2, an octagonal surface embedded region 13 shown by a broken line in fig. 1 is partially embedded in the bottom of the central portion of the modulation region 14. The cross-sectional view of fig. 2 can be explained as a manner in which a part of the upper portion of the surface-buried region 13 extends into the modulation region 14 so as to be included (enclosed) in the bottom portion of the central portion of the modulation region 14. The impurity density n2 of the surface buried region 13 is higher than the impurity density n1 of the modulation region 14 (n 2 > n 1). The four potential control regions 15a, 15b, 15c, and 15d each function as a pinning layer for capturing and discharging non-signal charges while directly controlling the potentials of the modulation region 14 of the embedded portion and the surface embedded region 13 directly below the modulation region, independently of each other. As shown in fig. 2, each pixel Xij of the solid-state imaging device according to the first embodiment is epitaxially grown on or above the semiconductor substrate itself - The photoelectric conversion layer 11 is a base body. An n-type modulation region 14 is disposed on the photoelectric conversion layer 11 through a surface buried region 13. A p-type well region (p-well) 12 surrounds the periphery of the modulation region 14.
As shown in fig. 1, the modulation region 14 is eight in shapeThe side shape, and the potential control regions 15a, 15b, 15c, 15d each have an octagonal shape in which the apexes of isosceles triangles are respectively chamfered. The reason why the three corners of the triangle are chamfered to form the octagon is that the corners at both ends of the base are formed in a chamfered shape of two layers. In the description of the potential control regions 15a, 15b, 15c, and 15d each approximately having an isosceles triangle shape, p is provided near the inner side of the bottom center portion of the first potential control region 15a arranged in the first quadrant Q1 + A first contact region 16a of the type. Similarly, p is provided near the inner side of the bottom center portion of the second potential control region 15b arranged in the second quadrant Q2 + A second contact region 16b of the type. Further, p is arranged near the inner side of the bottom center portion of the third potential control region 15c arranged in the third quadrant Q3 + A third contact region 16c having p arranged near the inner side of the bottom center portion of the fourth potential control region 15d arranged in the fourth quadrant Q4 + Fourth contact region 16d of the type.
The four potential control regions 15a, 15b, 15c, 15d are arranged in four quadrants on the upper portion of the modulation region 14, whereby the four potential control regions 15a, 15b, 15c, 15d control the potential distribution in the modulation region 14 and the surface buried region 13 along the time series, respectively, and sequentially determine the transmission paths of the signal charges. Then, the signal charges generated by the pixels Xij are transferred to the outside of the modulation region 14 through the transmission paths sequentially defined by the modulation region 14, respectively, by the electrostatic induction effect. Accordingly, as shown in fig. 1, four charge accumulation regions 17a, 17b, 17c, 17d for sequentially accumulating the signal charges transferred by the electrostatic induction effect through the four potential control regions 15a, 15b, 15c, 15d are arranged outside the four potential control regions 15a, 15b, 15c, 15d, respectively, as floating drain regions. N is provided near the outside of the bottom center portion of the first potential control region 15a arranged in the first quadrant Q1 + A first charge accumulation region 17a of the type. Similarly, n is provided near the outside of the bottom center portion of the second potential control region 15b arranged in the second quadrant Q2 + A second charge accumulation region 17b of the type. And is arranged at the firstN is arranged near the outside of the bottom center portion of the third potential control region 15c in the three-quadrant Q3 + A third charge accumulation region 17c having n arranged in the vicinity of the outer side of the bottom center portion of the fourth potential control region 15d arranged in the fourth quadrant Q4 + Fourth charge accumulation region 17d of the type.
A photodiode is constituted by the modulation region 14 functioning as a light-receiving cathode region (charge generation region), the surface buried region 13, and the photoelectric conversion layer 11 functioning as a light-receiving anode region immediately below the surface buried region 13. The signal charges (electrons) generated in the charge generation region (light receiving anode region) are injected into the surface buried region 13 directly above the charge generation region, and are introduced into the modulation region 14.
Fig. 2 is a cross-sectional view as seen from a cross-section corresponding to the direction II-II in fig. 1, and in fig. 2, a first contact region 16a buried to the right of the first potential control region 15a and a third contact region 16c buried to the left of the third potential control region 15c are exposed. Further, the first charge accumulation region 17a is exposed near the right side of the first potential control region 15a, and the third charge accumulation region 17c is exposed near the left side of the fourth potential control region 15 d. The interlayer insulating film 21 covers the modulation region 14 and the p-well 12, and the surface wiring 33 is connected to the first contact region 16a and the surface wiring 32 is connected to the third contact region 16c via a contact via penetrating the interlayer insulating film 21. Further, the surface wiring 34 is connected to the first charge accumulation region 17a, and the surface wiring 31 is connected to the third charge accumulation region 17c via a contact via penetrating the interlayer insulating film 21.
The surface wiring 34 located on the right side of fig. 2 is connected to a connection node S1 of the pixel Xij, and the connection node S1 is connected to the source electrode of the reset transistor QR1ij of the pixel Xij as shown in fig. 3. The drain electrode of the reset transistor QR1ij is connected to the power supply VDD, and a reset signal RT (i 1) of the i-th row of the horizontal line is input to the gate electrode of the reset transistor QR1ij from a vertical shift register (vertical driving circuit) 102 (see fig. 12 described later). The connection node S1 is also connected to the gate electrode of the readout transistor (amplifying transistor) QA1ij of the pixel Xij. The drain electrode of the readout transistor QA1ij is connected to the power supply VDD, and the source electrode is connected to the drain electrode of the switching transistor QS1ij for pixel selection of the pixel Xij. The source electrode of the switching transistor QS1ij is connected to the vertical signal line Bm1j of the j-column, and the selection signal SEL (i 1) of the i-th row is supplied from the vertical shift register 102 to the gate electrode of the switching transistor QS1 ij. By setting the selection signal SEL (i 1) to the high (H) level, the switching transistor QS1ij is turned on, and a current corresponding to the potential of the charge accumulation region 17a amplified by the readout transistor QA1ij flows to the vertical signal line Bm1j. On the other hand, the gate electrode of the reset transistor QR1ij is set to the high (H) level for the whole of the reset signal RT (i 1), and the charge accumulated in the charge accumulation region 17a is discharged to the power supply VDD side, and the charge accumulation region 17a is reset.
The surface wiring 31 located on the left side of fig. 2 is connected to the connection node S3 of the pixel Xij. This connection node S3 is connected to the source electrode of the reset transistor QR3ij of the pixel Xij as shown in fig. 3. The drain electrode of the reset transistor QR3ij is connected to the power supply VDD, and the reset signal RT (i 3) of the i-th row is input to the gate electrode of the reset transistor QR3 ij. The connection node S3 is also connected to the gate electrode of the readout transistor QA3ij of the pixel Xij. The drain electrode of the readout transistor QA3ij is connected to the power supply VDD, and the source electrode is connected to the drain electrode of the switching transistor QS3ij of the pixel Xij. The source electrode of the switching transistor QS3ij is connected to the vertical signal line Bm3j of the j-column, and the selection signal SEL (i 3) of the i-th row is supplied to the gate electrode of the switching transistor QS3 ij. By setting the selection signal SEL (i 3) to the high (H) level, the switching transistor QS3ij is turned on, and a current corresponding to the potential of the charge accumulation region 17c amplified by the readout transistor QA3ij flows to the vertical signal line Bm3j. On the other hand, the gate electrode of the reset transistor QR3ij is set to the high (H) level for the whole of the reset signal RT (i 3), and the charge accumulated in the charge accumulation region 17c is discharged to the power supply VDD side, and the charge accumulation region 17c is reset.
As the interlayer insulating film 21, an undoped silicon oxide film (SiO) which does not contain an impurity element such as phosphorus (P) or boron (B) called "NSG" can be used 2 A film). The interlayer insulating film 21 may be a phosphorus-doped silicon oxide film (PSG), a boron-doped silicon oxide film (BSG), or a silicon oxide film (BSG),Silicon oxide film (BPSG) added with boron and phosphorus, silicon nitride (Si 3 N 4 ) Films, and the like.
Although not shown in the cross-sectional view of fig. 2, as shown in fig. 1, the surface wiring 38 is connected to the second contact region 16b, and the surface wiring 35 is connected to the fourth contact region 16d. Further, as shown in fig. 1, the surface wiring 37 is connected to the second charge accumulating region 17b, and the surface wiring 36 is connected to the fourth charge accumulating region 17d. Note that the wiring layout of the surface wirings 31 to 38 shown in fig. 1 is merely an example, and in practice, a layout different from that of fig. 1 may be used in consideration of the relationship with other surface wirings not shown.
When the surface wirings 31 to 38 shown In fig. 1 are formed of transparent electrodes such as polycrystalline silicon, tin oxide (SnO 2), tin oxide (ITO) to which indium (In) is added, tin oxide (ZTO) to which zinc (Zn) is added, tin oxide (GTO) to which gallium (Ga) is added, and tin oxide (ATO) to which aluminum (Al) is added, it is possible to avoid a decrease In the aperture ratio of the pixel Xij of the solid-state imaging device according to the first embodiment.
The impurity density of the photoelectric conversion layer 11 as the charge generation region was set to be 6×10 11 ～2×10 15 cm -3 Left and right p - In the case of the semiconductor layer, the impurity density of the p-well 12 is set to 5×10 16 ～5×10 17 cm -3 The left and right p-type semiconductor regions are only required. For example, the impurity density of the photoelectric conversion layer 11 is set to 1×10 13 ～1.5×10 15 cm -3 In the left and right cases, the thickness of the photoelectric conversion layer 11 may be about 4 to 100 μm, and preferably about 6 to 20 μm. The impurity density of the modulation region 14 may be 5×10 14 ～1×10 17 cm -3 Left and right, typically e.g. 1X 10 16 cm -3 The depth of the modulation region 14 may be set to about 0.1 to 3 μm, preferably about 0.3 to 1.5 μm, depending on the value of the impurity density.
The position coordinates X1, X2, X3, … …, X18 in the plane direction (X direction) are shown on the upper side of fig. 2, and the curves shown with thick solid lines and thick broken lines of fig. 4 show the potential distribution at the level along the IVA-IVA direction of the pixel Xij shown in fig. 2. In addition, the curves of the thin solid line and the thin broken line of fig. 4 show the potential distribution at the level along the IVB-IVB direction of the pixel Xij shown in fig. 2. In a state where the first control voltage g1= -2V is applied to the first potential control region 15a of the first quadrant Q1 and the third control voltage g3=0v is applied to the third potential control region 15c of the third quadrant Q3, a potential distribution cut in the horizontal direction along the IVA-IVA direction on the upper surface side of the pixel near the position of the inter-layer insulating film 21 is shown as a thick solid line, a substantially constant zero potential is shown in a range (between coordinates x11-x 12) at the p-well 12 on the left side, and a potential well is shown at the position (between coordinates x12-x 13) of the third charge accumulation region 17 c.
Further, after the potential distribution in the horizontal direction at the shallow position in the IVA-IVA direction shows a substantially constant zero potential at the position (between coordinates x13-x 14) of the third potential control region 15c, a potential valley is shown at the gap position (between coordinates x14-x 15) between the third potential control region 15c and the first potential control region 15 a. Then, the X-axis is shifted rightward, and after a substantially constant peak voltage of-2V is shown at the position of the first potential control region 15a (between coordinates X15 to X16), a potential well is shown at the position of the first charge accumulation region 17a (between coordinates X16 to X17). Then, the X-axis is shifted further rightward, and a substantially constant zero potential is again shown in the range of the right p-well 12 (between the coordinates X17 to X18). As shown by the thick solid line in fig. 4, when the first control voltage g1= -2V is applied to the first potential control region 15a and the third control voltage g3=0v is applied to the third potential control region 15c, the same potential distribution as that of a hook structure (BJT) of a pnp Bipolar Junction Transistor (BJT) having the third potential control region 15c as a p-type emitter and the first potential control region 15a as a p-type collector is formed on the upper surface side of the pixel near the position of the inter-layer insulating film 21. The gap position (between coordinates x14 to x 15) between the third potential control region 15c as the base position of the BJT and the first potential control region 15a is a potential valley for electrons, but becomes a potential barrier for holes (hole) of hook type. Holes that are non-signal charges collected and trapped in the first potential control region 15a are discharged via the surface wiring 33.
On the other hand, in a state where the first control voltage g1=0v is applied to the first potential control region 15a of the first quadrant Q1 and the third control voltage g3= -2V is applied to the third potential control region 15c of the third quadrant Q3, the potential distribution along the IVA-IVA direction and cut in the horizontal direction is hidden by the thick dotted line, but a substantially constant zero potential is shown in the range of the left p-well 12 (between the coordinates x11-x 12), and a potential well is shown at the position of the third charge accumulation region 17c (between the coordinates x12-x 13). When the X-axis is shifted rightward in the IVA-IVA direction, as indicated by a thick dotted line, a potential valley is shown at a position (between coordinates X13-X14) of the third potential control region 15c, and after a substantially constant peak voltage of-2V is shown, a gap position (between coordinates X14-X15) between the third potential control region 15c and the first potential control region 15 a. Further shifting the X-axis to the right, as indicated by the thick dotted line at the position of the first potential control region 15a (between coordinates X15-X16), a potential well is shown at the position of the first charge accumulation region 17a (between coordinates X16-X17) after showing a substantially constant zero potential. When the X-axis is moved further rightward, the thick dotted line is hidden under the shadow of the thick solid line, but shows a substantially constant zero potential again in the range of the p-well 12 on the right side (between the coordinates X17 to X18).
As shown by the thick dotted line in fig. 4, in a state where the first control voltage g1=0v is applied to the first potential control region 15a and the third control voltage g3= -2V is applied to the third potential control region 15c, the same potential distribution as that of the hook structure of the pnp type BJT having the first potential control region 15a as the p-type emitter and the third potential control region 15c as the p-type collector is formed on the upper surface side of the pixel near the position of the inter-layer insulating film 21. The potential valley for electrons shown in the gap position (between coordinates x14 to x 15) between the third potential control region 15c as the base position of the BJT and the first potential control region 15a means that a hook-shaped potential barrier is constituted for holes. Holes that are non-signal charges collected and trapped in the third potential control region 15c are discharged via the surface wiring 32.
On the other hand, the potential distribution of the horizontal direction of the deep position in the IVB-IVB direction along the inter-layer insulating film 21 is also the same as the potential distribution of the shallow position in the IVA-IVA direction on the left side of the position (coordinate x 13) of the third charge accumulation region 17c and the right side of the position (coordinate x 16) of the first charge accumulation region 17 a. Therefore, the description will be focused on the position (coordinate x 13) of the third charge accumulation region 17c and the position (coordinate x 16) of the first charge accumulation region 17 a.
In a state where the first control voltage g1= -2V is applied to the first potential control region 15a of the first quadrant Q1 and the third control voltage g3=0v is applied to the third potential control region 15c of the third quadrant Q3, the potential distribution sectioned in the horizontal direction along the IVB-IVB direction is also reduced from +1.7v to +1.3v at the position of the third potential control region 15c (between coordinates x13-x 14) after showing the potential gradient rising upward to the right from +3V to +1.7v or so at the gap position between the third potential control region 15c and the first potential control region 15a (between coordinates x14-x 15) as shown by a thin solid line. Then, the X-axis is further shifted rightward, and after being reduced to 1V of the extremely small voltage at the position of the first potential control region 15a (between coordinates X15 to X16), is increased toward the potential well at the position of the first charge accumulation region 17a (between coordinates X16 to X17). It is understood that, when the first control voltage g1= -2V is applied to the first potential control region 15a of the first quadrant Q1 and the third control voltage g3=0v is applied to the third potential control region 15c of the third quadrant Q3, a current path toward the third charge accumulation region 17c is formed in the lower portion of the modulation region 14 and the surface buried region 13 as shown by a thin solid line in fig. 4, and the signal charge generated in the photoelectric conversion layer 11 is guided to the third charge accumulation region 17c of the third quadrant Q3.
In a state where the first control voltage g1=0v is applied to the first potential control region 15a of the first quadrant Q1 and the third control voltage g3= -2V is applied to the third potential control region 15c of the third quadrant Q3, the potential distribution sectioned in the horizontal direction along the IVB-IVB direction is shown by a thin broken line, showing a downward-right falling potential gradient which decreases to a minimum voltage of 1V at the position (between coordinates x13-x 14) of the third potential control region 15c and then increases to about +1.5v, and thereafter increases from +1.5v to about +1.7v at the gap position (between coordinates x14-x 15) between the third potential control region 15c and the first potential control region 15a with a downward-right potential gradient. Then, the X-axis is shifted further rightward, and becomes a potential distribution that increases toward the potential well at the position of the first charge accumulation region 17a (between coordinates X16 to X17) after continuing to increase at the position of the first potential control region 15a (between coordinates X15 to X16). When the first control voltage g1=0v is applied to the first potential control region 15a of the first quadrant Q1 and the third control voltage g3= -2V is applied to the third potential control region 15c of the third quadrant Q3, a transmission path of the potential distribution toward the first charge accumulation region 17a as shown by a thin broken line in fig. 4 is formed in the lower part of the modulation region 14 and the surface buried region 13, and the signal charge generated in the photoelectric conversion layer 11 is guided to the first charge accumulation region 17a of the first quadrant Q1.
Although not shown in the drawings, it can be easily understood from the above description that when the second control voltage g2=0v is applied to the second potential control region 15b of the second quadrant Q2 and the fourth control voltage g4= -2v is applied to the fourth potential control region 15d of the fourth quadrant Q4, the transmission path of the potential distribution toward the second charge accumulation region 17b is formed in the lower part of the modulation region 14 and the surface buried region 13 as in fig. 4, and the signal charges generated in the photoelectric conversion layer 11 are guided to the second charge accumulation region 17b of the second quadrant Q2. It is also understood that when the second control voltage g2= -2V is applied to the second potential control region 15b of the second quadrant Q2 and the fourth control voltage g4=0v is applied to the fourth potential control region 15d of the fourth quadrant Q4, a current path toward the fourth charge accumulation region 17d of the fourth quadrant Q4 is similarly formed in the lower portion of the modulation region 14 and the surface buried region 13, and the signal charge generated in the photoelectric conversion layer 11 is guided to the fourth charge accumulation region 17d.
As is apparent from an examination of the change in the potential distribution in fig. 4, by sequentially applying individual voltage pulses (path selection signals) to the four potential control regions 15a, 15b, 15c, 15d shown in fig. 1 in accordance with the pulse application pattern determined by the predetermined time chart, the transmission paths formed in the lower portion of the modulation region 14 and the surface-buried region 13 can be controlled so that the signal charges are sequentially accumulated in the four charge accumulation regions 17a, 17b, 17c, 17d, thereby realizing the TOF-type high-speed operation efficiently.
The position coordinates Z0, Z1, Z2, Z3 in the depth direction (Z direction) are shown on the left side of fig. 2, and the curves shown in fig. 5 show the potential distribution at the level along the longitudinal direction (V-V direction) of fig. 2. As shown in fig. 5, the potential of the interlayer insulating film 21, the modulation region 14, the surface embedded region 13, and the photoelectric conversion layer 11 cut in the depth direction gradually increases in the forward direction from the level of the depth of the lower surface of the interlayer insulating film 21 (coordinate z 0) to the level of the depth of the upper surface of the surface embedded region 13 (coordinate z 1), and reaches a maximum value of about 2V in the vicinity of the level of the depth of the lower surface of the surface embedded region 13 (coordinate z 2). Then, if the depth is further increased, the maximum value tends to decrease from the vicinity of the lower surface of the surface embedded region 13, and if the depth exceeds the level (coordinate z 3) of the depth of the lower surface of the p-well 12, the potential in the longitudinal direction (V-V direction) decreases to a negative value as shown in fig. 5, further deeper toward the rear surface in the depth direction in the photoelectric conversion layer 11.
The potential distribution showing the maximum value of the potential of around 2V in the vicinity of the level (coordinate z 2) of the depth of the lower surface of the surface buried region 13 shown in fig. 5 corresponds to the potential distribution showing about 2V in the vicinity of the center between the third potential control region 15c and the first potential control region 15a (between coordinates x14 to x 15) shown in the thin solid line and the broken line of fig. 4. The potential distribution shown in fig. 5, which is cut in the longitudinal direction (V-V direction) at the center between the third potential control region 15c and the first potential control region 15a (between coordinates x14 to x 15), is the same hook-shaped potential distribution as that of the electrostatic induction transistor (SIT) having the third potential control region 15c and the first potential control region 15a as p-type buried gate electrodes.
However, since the TOF type operation is performed, the transmission path of the signal charges is controlled by sequentially applying voltage pulses to the four potential control regions 15a, 15b, 15c, and 15d over time so that the signal charges are sequentially distributed to the four charge accumulation regions 17a, 17b, 17c, and 17d and accumulated, which is strictly different from the saddle point type potential having symmetry exhibited by the SIT. That is, when pulses of an application pattern in which the potential of a specific one of the four potential control regions 15a, 15b, 15c, and 15d is set to 0V and the potential of the remaining three potential control regions is set to-2V are sequentially applied, the potential of the specific quadrant with respect to electrons becomes low, whereas the potential of the specific quadrant with respect to holes becomes high in an asymmetric shape.
In short, according to the structure of the pixel Xij of the solid-state imaging device according to the first embodiment, the four potential control regions 15a, 15b, 15c, 15d shown in fig. 1 directly control the potential of the surface embedded region 13 immediately below in the vertical direction (depth direction), and thus the TOF type operation can be realized at an extremely high speed. That is, it is possible to efficiently and rapidly control at the center positions of the four potential control regions 15a, 15b, 15c, 15d shown in fig. 1 so that asymmetric potentials in which the potential barrier for holes in a specific quadrant is higher than other image limits are formed at high speed at the depth level near the lower surface of the surface buried region 13. According to the structure of the pixel Xij of the solid-state imaging device according to the first embodiment, an operation of rotating an asymmetrically-shaped potential on a plan view shown in fig. 1 together with a pulse voltage according to a time chart (see fig. 13 described later) on design can be realized at high speed and high efficiency. In addition, since there is no need to inject majority carriers such as the technology described in patent document 1, power consumption is low.
Variation of the first embodiment
Although the planar pattern is not illustrated, the solid-state imaging device according to the modification of the first embodiment has four pixels Xij of p + The pattern of the arrangement of the potential control regions 15a, 15b, 15c, 15d is common to the topology of the solid-state imaging device according to the first embodiment shown in fig. 1. However, the topology of the solid-state imaging device according to the first embodiment is different from that of the solid-state imaging device according to the first embodiment in thatThe center of coordinates in Q1 to fourth quadrant Q4 is provided with a p-type central embedded control region 15m. Impurity density p of central buried control region 15m a At a concentration of 10 at 15m depletion of the central buried control region 16 ～10 17 cm -3 Left and right. P is arranged near the inner side of the central part of the side arranged outside the first potential control region 15a in the first quadrant Q1 + A first contact region 16a having p arranged in the vicinity of the inner side of the central portion of the side outside the third potential control region 15c in the third quadrant Q3 + A third contact region 16c of the type. Although not shown, as in fig. 1, there is a contact region between the second potential control region 15b and the fourth potential control region 15 d. As shown in fig. 6, the four potential control regions 15a, 15b, 15c, 15d are buried in the upper portion of the n-type modulation region 14 so that the upper surfaces thereof are shared with the modulation region 14, but the upper surface of the central buried control region 15m is on the same level as the lower surfaces of the first contact region 16a and the third contact region 16c. The lower surface of the central embedded control region 15m is on the same level as the lower surfaces of the four potential control regions 15a, 15b, 15c, 15 d.
The left side of fig. 6 shows position coordinates Z0, Z1, Z2, Z3 in the depth direction (Z direction), and the graph shown in fig. 7 shows the potential distribution at a position along the longitudinal direction (VII-VII direction) of fig. 6. The potential of the interlayer insulating film 21, the modulation region 14, the surface buried region 13, and the photoelectric conversion layer 11 sectioned in the depth direction along the VII-VII direction is about 1.5V at the level of the depth (coordinate z 0) of the lower surface of the interlayer insulating film 21 as shown in fig. 7, but decreases to about 1.0V as going forward in the depth direction, and increases again in the forward direction, forming a trough of the potential distribution. Then, the depth of the upper surface of the surface embedded region 13 reaches about 1.5V at the level (coordinate z 1), and the depth increases in the forward direction as the depth increases, and the maximum value reaches about 2.0V in the vicinity of the level (coordinate z 2) of the depth of the lower surface of the surface embedded region 13. Then, if the depth is further increased, the maximum value near the lower surface of the surface embedded region 13 tends to decrease, and the hook-shaped potential distribution is exhibited. If the layer exceeding the depth of the lower surface of the p-well 12 (coordinate z 3) is further deep in the photoelectric conversion layer 11 toward the rear surface in the depth direction, the potential in the longitudinal direction (VII-VII direction) decreases to a negative value as shown in fig. 7.
As shown in fig. 7, by forming the trough of the potential distribution at the surface (coordinates z0 to z 1), the dark current component caused by the interface state can be concentrated to the surface. Therefore, according to the pixel Xij of the solid-state imaging device according to the modification of the first embodiment, the dark current component can be discharged to the drain via the interface of the surface, and the dark current component is prevented from being mixed with the signal charge. In particular, in the case of a solid-state image pickup device mainly using near-infrared light, the amount of electric charge absorbed by light and generated in the vicinity of the surface is small, and therefore, it is effective to remove dark current components caused by interface states in consideration of the influence on sensitivity.
(second embodiment)
The pixel array section of the solid-state imaging device according to the second embodiment of the present invention is similar to the first embodiment in that a large number of pixels Xij are also arranged in a two-dimensional matrix. Fig. 8 shows a plane pattern of an imaging region of a pixel Xij as a representative example, and in fig. 8, the region defined by the first quadrant Q1, the second quadrant Q2, the third quadrant Q3, and the fourth quadrant Q4 defined in fig. 26 is also taken as a base. The solid-state imaging device according to the second embodiment has five pixels Xij of five p + The pattern of the arrangement of the potential control regions 18a, 18b, 18c, 18d, 18e of the type is different from the solid-state imaging device according to the first embodiment.
Note that the planar layout in which the first potential control region 18a is arranged in the first quadrant Q1, the second potential control region 18b is arranged in the second quadrant Q2, the third potential control region 18c is arranged in the third quadrant Q3, and the fourth potential control region 18d is arranged in the fourth quadrant Q4 is similar to the topology of the solid-state imaging device according to the first embodiment shown in fig. 1. However, the topology of the solid-state imaging device according to the first embodiment is different from that of the first to fourth quadrants Q1 to Q4 in that a central potential control region 18e is arranged at the coordinate center. These five potential control regions 18a, 18b, 18c, 18d, 18e are buried in the upper portion of the n-type modulation region 14 as shown in fig. 9. As can be seen from fig. 8, the four potential control regions 18a, 18b, 18c, 18d are buried in the modulation region 14 as similar independent planar patterns so as to surround the central potential control region 18e with a space therebetween.
As is clear from fig. 9, an octagonal surface embedded region 13 shown by a broken line in fig. 8 is partially embedded in the bottom of the central portion of the modulation region 14. The impurity density n2 of the surface buried region 13 is higher than the impurity density n1 of the modulation region 14 (n 2 > n 1). The five potential control regions 18a, 18b, 18c, 18d, and 18e each function as a pinning layer for directly controlling the potentials of the modulation region 14 of the embedded portion and the surface embedded region 13 directly below the modulation region, and capturing and discharging the non-signal charges, independently of each other. As shown in fig. 9, the pixel Xij of the solid-state imaging device according to the second embodiment is epitaxially grown on or above the semiconductor substrate itself as p - The photoelectric conversion layer 11 is a base body. An n-type modulation region 14 is disposed on the photoelectric conversion layer 11 through a surface buried region 13. A p-type well region (p-well) 12 surrounds the periphery of the modulation region 14.
As shown in fig. 8, the modulation region 14 has an octagonal shape, and the central potential control region 18e disposed at the center thereof has an octagonal shape that is rotationally symmetrical 4 times, but has a different shape from the modulation region 14. The shape of each of the four potential control regions 18a, 18b, 18c, 18d around the central potential control region 18e is different from the topology of the solid-state imaging device according to the first embodiment in that it is in the shape of an elongated octagon. P is provided near the inner side of the central portion of the side arranged outside the first potential control region 18a in the first quadrant Q1 + A first contact region 16a of the type. Similarly, p is provided in the vicinity of the inner side of the center portion of the side arranged outside the second potential control region 18b in the second quadrant Q2 + A second contact region 16b of the type. Further, p is disposed in the vicinity of the inner side of the central portion of the side disposed outside the third potential control region 18c in the third quadrant Q3 + A third contact region 16c for controlling a fourth potential in the fourth quadrant Q4 P is arranged near the inner side of the central part of the side outside the region 18d + Fourth contact region 16d of the type.
A fixed potential of, for example, -1V is applied to the central potential control region 18e, and the potential immediately below the central potential control region 18e is maintained at a fixed potential. Pulses driven at 0V and-2V are sequentially applied to the four potential control regions 18a, 18b, 18c, 18d in four quadrants so that the four potential control regions 18a, 18b, 18c, 18d control the potential distribution in the modulation region 14 and the surface buried region 13 along the time series, respectively, in the upper portion of the modulation region 14 so as to divide into four quadrants, and the transmission paths of the signal charges are sequentially determined. Then, the signal charges generated by the pixels Xij are transferred to the outside of the modulation region 14 through the transmission paths sequentially defined by the modulation region 14, respectively, by the electrostatic induction effect.
As shown in fig. 8 and 9, four charge accumulation regions 17a, 17b, 17c, 17d for sequentially accumulating the signal charges transferred by the electrostatic induction effect through the four potential control regions 18a, 18b, 18c, 18d are arranged outside the four potential control regions 18a, 18b, 18c, 18d as floating drain regions, respectively. N is provided near the outside of the first potential control region 18a arranged in the first quadrant Q1 + A first charge accumulation region 17a of the type. Similarly, n is provided near the outside of the second potential control region 18b arranged in the second quadrant Q2 + A second charge accumulation region 17b of the type. Further, n is arranged in the vicinity of the outside of the third potential control region 18c arranged in the third quadrant Q3 + A third charge accumulation region 17c having n arranged in the vicinity of the outer side of the fourth potential control region 18d arranged in the fourth quadrant Q4 + Fourth charge accumulation region 17d of the type.
A photodiode is constituted by the modulation region 14 functioning as a light-receiving cathode region (charge generation region), the surface buried region 13, and the photoelectric conversion layer 11 functioning as a light-receiving anode region immediately below the surface buried region 13. The signal charges (electrons) generated in the charge generation region (light receiving anode region) are injected into the surface buried region 13 directly above the charge generation region, and are introduced into the modulation region 14.
Fig. 9 is a cross-sectional view as seen from the direction IX-IX of fig. 8, and in fig. 9, the first contact region 16a buried in the right side of the first potential control region 18a, the central contact region 16e buried in the center of the central potential control region 18e, and the third contact region 16c buried in the left side of the third potential control region 18c are exposed. Further, the first charge accumulation region 17a is exposed near the right side of the first potential control region 18a, and the third charge accumulation region 17c is exposed near the left side of the third potential control region 18 c. In the cross-sectional structure of fig. 9, similarly to fig. 2, an interlayer insulating film covers the modulation region 14 and the p-well 12, but the interlayer insulating film, a contact plug penetrating the interlayer insulating film, and a surface wiring connected to the first contact region 16a and the like via the contact plug are omitted.
Although the wiring layout of the surface wirings 31 to 38 and the like shown in fig. 1 is omitted in fig. 8, the surface wirings having the layout shown by way of example in fig. 1 or a layout different from that of fig. 1 are naturally connected to the surface wirings including the surface wirings connected to the central contact region 16e of the central potential control region 18 e. In addition, if these surface wirings are made of transparent electrodes such as polysilicon, it is possible to avoid a decrease in the aperture ratio of the pixels Xij, as in the first embodiment.
Although the display of the potential distribution as shown in fig. 4 of the first embodiment is omitted, in a state in which the first control voltage g1= -2V is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3=0v is applied to the third potential control region 18c, the potential distribution on the upper surface side of the horizontal split pixel is such that the hook structure of the pnp type BJT having the third potential control region 18c as the emitter and the central potential control region 18e as the collector is connected in series with the hook structure of the pnp type BJT having the central potential control region 18e as the emitter and the first potential control region 18a as the collector (see fig. 18 described later). A hook-shaped potential barrier for holes is formed between the third potential control region 18c and the central potential control region 18e, and between the central potential control region 18e and the first potential control region 18a, which are base positions of the BJTs. The non-signal charges (holes) collected and trapped in the central potential control region 18e and the first potential control region 18a are discharged through surface wiring (not shown).
Similarly, in a state where the first control voltage g1=0v is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3= -2V is applied to the third potential control region 18c, the potential distribution on the upper surface side of the horizontal split pixel is a potential distribution in which the hook structure of the pnp type BJT having the first potential control region 18a as the emitter, the central potential control region 18e as the collector and the hook structure of the pnp type BJT having the central potential control region 18e as the emitter and the third potential control region 18c as the collector are connected in series. A hook-shaped potential barrier for holes is formed between the third potential control region 18c and the central potential control region 18e, and between the central potential control region 18e and the first potential control region 18a, which are base positions of the BJT, and non-signal charges (holes) collected and trapped in the central potential control region 18e and the third potential control region 18c are discharged through surface wiring (not shown).
On the other hand, regarding the potential distribution along the deep horizontal plane of the horizontal cut surface embedded region 13, when the first control voltage g1=0v is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3= -2V is applied to the third potential control region 18c of the third quadrant Q3, a transmission path of the potential distribution toward the first charge accumulation region 17a is formed in the lower part of the modulation region 14 and the surface embedded region 13, and the signal charge generated in the photoelectric conversion layer 11 is guided to the first charge accumulation region 17a of the first quadrant Q1. When the second control voltage g2=0v is applied to the second potential control region 18b, the fixed potential g0= -1V is applied to the central potential control region 18e, and the fourth control voltage g4= -2V is applied to the fourth potential control region 18d, a transmission path of the potential distribution toward the second charge accumulation region 17b is formed in the lower portion of the modulation region 14 and the surface buried region 13, and the signal charge generated in the photoelectric conversion layer 11 is guided to the second charge accumulation region 17b of the second quadrant Q2.
Similarly, regarding the potential distribution along the deep horizontal plane of the horizontal cut surface embedded region 13, when the first control voltage g1= -2V is applied to the first potential control region 15a of the first quadrant Q1, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3=0v is applied to the third potential control region 15c of the third quadrant Q3, a current path toward the third charge accumulation region 17c is formed in the lower part of the modulation region 14 and the surface embedded region 13, and the signal charge generated in the photoelectric conversion layer 11 is guided to the third charge accumulation region 17c of the third quadrant Q3. When the second control voltage g2= -2V is applied to the second potential control region 18b, the fixed potential g0= -1V is applied to the central potential control region 18e, and the fourth control voltage g4=0v is applied to the fourth potential control region 18d of the fourth quadrant Q4, a current path toward the fourth charge accumulation region 17d is formed in the lower portion of the modulation region 14 and the surface buried region 13, and the signal charge generated in the photoelectric conversion layer 11 is guided to the fourth charge accumulation region 17d.
That is, it is understood that by applying a fixed potential to the central potential control region 18e shown in fig. 8 and sequentially applying a path selection signal to the four potential control regions 18a, 18b, 18c, 18d around the central potential control region in accordance with a pulse application pattern determined by a predetermined time chart (see fig. 13 described later), the transmission paths formed in the lower portion of the modulation region 14 and the surface-embedded region 13 can be controlled so that signal charges are sequentially accumulated in the four charge accumulation regions 17a, 17b, 17c, 17d, and that a TOF-type high-speed operation can be efficiently realized. The other matters are substantially the same as those of the solid-state imaging device according to the first embodiment described above, and therefore, duplicate description is omitted.
(third embodiment)
The pixel Xij of the solid-state imaging device according to the third embodiment of the present invention is configured to have five p as shown in fig. 10 + The patterns of the potential control regions 18a, 18b, 18c, 18d, 18e are based on the patterns according to the second embodimentThe planar layout of the pixels Xij of the solid-state image pickup device is common. As in the second embodiment, these five potential control regions 18a, 18b, 18c, 18d, 18e are buried in the upper portion of the n-type modulation region 14 as shown in fig. 11. As is clear from fig. 10, the four potential control regions 18a, 18b, 18c, 18d are buried in the modulation region 14 as independent plane patterns of a similar type so as to surround the central potential control region 18e with a space therebetween, but are further different from the structure of the pixel Xij of the solid-state imaging device according to the second embodiment in that the auxiliary gate electrode 41 is provided between the central potential control region 18e and the four potential control regions 18a, 18b, 18c, 18 d.
The auxiliary gate electrode 41 is arranged on the gate insulating film 22 shown in fig. 11 in a planar pattern as shown by way of example in fig. 10, and an insulating gate structure is formed. As shown in fig. 11, the cross-sectional structure of a pixel Xij of a solid-state imaging device according to the third embodiment is p epitaxially grown on or above a semiconductor substrate itself - The photoelectric conversion layer 11 is a base body. An n-type modulation region 14 is disposed on the photoelectric conversion layer 11 through a surface buried region 13. The p-well 12 surrounds the periphery of the modulation region 14. The gate insulating film 22 is formed to cover the p-well 12, the modulation region 14, the first potential control region 18a, the central potential control region 18e, the third potential control region 18c, and the like at the upper portion of the modulation region 14. As the gate insulating film 22, siO 2 Films are suitable, but SiO may also be used 2 Various insulating films other than the film. For example, it may be made of SiO 2 film/Si 3 N 4 film/SiO 2 An ONO film comprising three layers of laminated films. Further, an oxide containing at least any one element of strontium (Sr), aluminum (Al), magnesium (Mg), yttrium (Y), hafnium (Hf), zirconium (Zr), tantalum (Ta), bismuth (Bi), silicon nitride containing these elements, or the like may be used as the gate insulating film 22.
As shown in fig. 10, the planar pattern of the auxiliary gate electrode 41 has a ring-like topology in which a part of the outer peripheral side of the central potential control region 18e and a part of the inner peripheral side of the arrangement of the four potential control regions 18a, 18b, 18c, 18d are covered. As is clear from fig. 11, an octagonal surface embedded region 13 shown by a broken line in fig. 10 is partially embedded in the bottom of the central portion of the modulation region 14. The impurity density n2 of the surface buried region 13 is higher than the impurity density n1 of the modulation region 14 (n 2 > n 1). The five potential control regions 18a, 18b, 18c, 18d, and 18e each function as a pinning layer for directly controlling the potentials of the modulation region 14 of the embedded portion and the surface embedded region 13 directly below the modulation region, and capturing and discharging the non-signal charges, independently of each other. As shown in fig. 10, the modulation region 14 has an octagonal shape, and the central potential control region 18e disposed at the center thereof has an octagonal shape. The four potential control regions 18a, 18b, 18c, and 18d around the central potential control region 18e are each formed in an elongated octagon shape, and are similar to the topology of the solid-state imaging device according to the second embodiment in this regard.
As shown in fig. 10, the auxiliary gate electrode 41 is configured as a planar pattern of a topology that surrounds the outer periphery of the central potential control region 18e so as to reach the first potential control region 18a, whereby a first insulated gate transistor (MIS transistor) is configured between the central potential control region 18e and the first potential control region 18 a. Similarly, the auxiliary gate electrode 41 forms a second MIS transistor common to the first MIS transistor between the central potential control region 18e and the second potential control region 18b by a pattern in which the auxiliary gate electrode 41 surrounds the outer peripheral side of the central potential control region 18e so as to reach the second potential control region 18 b.
The auxiliary gate electrode 41 forms a third MIS transistor between the central potential control region 18e and the third potential control region 18c, forms a fourth MIS transistor between the central potential control region 18e and the fourth potential control region 18d, and has the auxiliary gate electrode 41 common to the first MIS transistor. P is provided near the inner side of the central portion of the side outside the first potential control region 18a + A first contact region 16a of the type. Similarly, p is provided in the vicinity of the inner side of the central portion of the side outside the second potential control region 18b + A second contact region 16b of the type. Furthermore, the processing unit is configured to,p is arranged near the inner side of the central part of the side outside the third potential control region 18c + A third contact region 16c having p arranged in the vicinity of the inner side of the central portion of the side outside the fourth potential control region 18d + Fourth contact region 16d of the type.
Fig. 11 is a cross-sectional view as seen from the direction IX-XI of fig. 10, and in fig. 11, the first contact region 16a buried in the right side of the first potential control region 18a, the central contact region 16e buried in the center of the central potential control region 18e, and the third contact region 16c buried in the left side of the third potential control region 18c are exposed. Further, the first charge accumulation region 17a is exposed near the right side of the first potential control region 18a, and the third charge accumulation region 17c is exposed near the left side of the third potential control region 18 c. In fig. 11, the auxiliary gate electrode 41 constituting the first MIS transistor formed between the central potential control region 18e and the first potential control region 18a is shown on the right side, and the auxiliary gate electrode 41 constituting the third MIS transistor formed between the central potential control region 18e and the third potential control region 18c is shown on the left side. The auxiliary gate electrode 41 on the right side and the auxiliary gate electrode 41 on the left side shown as separate patterns in fig. 11 are continuous and integral members as shown in fig. 10, and an interlayer insulating film is covered so as to cover the auxiliary gate electrode 41 and the gate insulating film 22. However, in the cross-sectional structure of fig. 11, illustration of the interlayer insulating film, the contact plug penetrating the interlayer insulating film, and the surface wiring connected to the first contact region 16a and the like via the contact plug is omitted as in fig. 2 and 9.
In the pixel Xij of the solid-state imaging device according to the third embodiment, as in the second embodiment, by applying a fixed potential of, for example, -1V to the central potential control region 18e and sequentially applying pulses driven in the mode of (0V, -2V) to the four potential control regions 18a, 18b, 18c, 18d, the transmission path of the signal charge can be sequentially determined, and the signal charge generated by the pixel Xij can be transferred in the outer direction of the modulation region 14 by the electrostatic induction effect. That is, n is provided in the vicinity of the outside of the first potential control region 18a arranged in the first quadrant Q1 + A kind of electronic deviceThe first charge accumulation region 17a serves as a floating drain region. Similarly, n is provided near the outside of the second potential control region 18b arranged in the second quadrant Q2 + The second charge accumulation region 17b of the type serves as a floating drain region. Further, n is arranged in the vicinity of the outside of the third potential control region 18c arranged in the third quadrant Q3 + The third charge accumulation region 17c is configured as a floating drain region, and n is arranged near the outer side of the fourth potential control region 18d arranged in the fourth quadrant Q4 + The fourth charge accumulation region 17d of the type serves as a floating drain region.
The first, second, third and fourth charge accumulation regions 17a, 17b, 17c and 17d are respectively arranged at equal intervals at the positions of the long sides of the modulation region 14 of the unequal octagon whose long sides and short sides are alternately arranged, which is cut out toward the outside. Further, the first drain region 19a, the second drain region 19b, the third drain region 19c, and the fourth drain region 19d are arranged so as to meet the short sides of the modulation region 14 having the unequal-sided octagon shape, respectively. As shown in fig. 10, a first drain gate electrode 43a is provided so as to cover the upper end portion of the first potential control region 18a, the right end portion of the second potential control region 18b, and a part of the first drain region 19a, with the gate insulating film 22, which is transparent in fig. 10 and is not shown. Similarly, the second drain gate electrode 43b is provided so as to cover the left end portion of the second potential control region 18b, the upper end portion of the third potential control region 18c, and a part of the second drain region 19 b. The third drain gate electrode 43c is provided so as to cover the lower end portion of the third potential control region 18c, the left end portion of the fourth potential control region 18c, and a part of the third drain region 19c, and the fourth drain gate electrode 43d is provided so as to cover the right end portion of the fourth potential control region 18d, the lower end portion of the first potential control region 18c, and a part of the fourth drain region 19 d.
Although the wiring layout of the surface wirings 31 to 38 and the like shown in fig. 1 is omitted in fig. 10, the surface wirings having the layout shown by way of example in fig. 1 or a layout different from that of fig. 1 are naturally connected to the surface wirings including the surface wirings connected to the central contact region 16e of the central potential control region 18 e. In addition, if these surface wirings are made of transparent electrodes such as polysilicon, it is possible to avoid a decrease in the aperture ratio of the pixels Xij, as in the first and second embodiments.
Although the display of the potential distribution as shown in fig. 4 used in the description of the first embodiment is omitted, in a state where the first control voltage g1= -2V is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3=0v is applied to the third potential control region 18c, the potential distribution on the upper surface side of the horizontal split pixel is such that, in the absence of the auxiliary gate electrode 41, the hook structure of the pnp type BJT having the third potential control region 18c as the emitter and the central potential control region 18e as the collector is connected in series with the hook structure of the pnp type BJT having the central potential control region 18e as the emitter and the first potential control region 18a as the collector. Similarly, in the case where the auxiliary gate electrode 41 is not present, the potential distribution on the upper surface side of the horizontal split pixel in the state where the first control voltage g1=0v is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3= -2V is applied to the third potential control region 18c is a potential distribution in which the hook structure of the pnp type BJT having the first potential control region 18a as the emitter, the central potential control region 18e as the collector and the hook structure of the pnp type BJT having the central potential control region 18e as the emitter and the third potential control region 18c as the collector are connected in series.
That is, as already described in the description of the second embodiment, in the case where the auxiliary gate electrode 41 is not present, a hook-shaped potential barrier against non-signal charges (holes) is formed between the third potential control region 18c and the central potential control region 18e, and between the central potential control region 18e and the first potential control region 18a, which are base positions of the BJTs. However, if the first control voltage G1, the second control voltage G2, the third control voltage G3, and the fourth control voltage G4 are not driven, for example, if g1=g2=g3=g4=0v and a negative voltage is applied to the auxiliary gate electrode 41, the potential barrier against the non-signal charges is eliminated. When a negative voltage (non-signal charge inducing pulse) is applied to the auxiliary gate electrode 41, the auxiliary gate electrode 41 induces a non-signal charge directly under the auxiliary gate electrode 41, and the non-signal charge is discharged from directly under the auxiliary gate electrode 41 to the surface wiring via the central potential control region 18e maintained at a fixed potential g0= -1V.
On the other hand, if a positive voltage is applied to the auxiliary gate electrode 41 in a state where the first control voltage G1, the second control voltage G2, the third control voltage G3, and the fourth control voltage G4 are not driven, the potential barrier against the non-signal charges increases. Since the potential barrier against the non-signal charges serves as a potential well for electrons that become a dark current and a background light component, electrons that become a dark current and a background light component immediately below the auxiliary gate electrode 41 can be discharged to the discharge drain regions 19a, 19b, 19c, and 19d by applying a positive potential as a "charge discharge voltage" to the discharge gate electrodes 43a, 43b, 43c, and 43 d. That is, the auxiliary gate electrode 41 can assist the discharge of electrons, which are a dark current and a background light component, to the discharge drain regions 19a, 19b, 19c, and 19d.
As shown in fig. 12, the solid-state imaging device according to the third embodiment has a pixel array section and peripheral circuit sections (101, 102, 104, 105) arranged on the same semiconductor chip. A plurality of active pixels X shown in fig. 10 are arranged in a two-dimensional matrix in the pixel array section ij . In addition, at the upper side of the pixel array section, along the pixel row X 11 ～X 1m ；X 21 ～X 2m ；……；X n1 ～X nm A charge modulation driver 101 is provided in the direction along pixel rows X11, X12, X13, … … X1m shown in the horizontal direction in fig. 12 at the lower side of the pixel array section; x105, X104, X103, … … X2m; x31, X32, X33, … … X3m; the directions of … … Xn1, xn2, xn3 and … … Xnm are provided with a column parallel folding integral/circulating A/D converter (column parallel folded integration/cyclic A/D converter) 104 and a column parallel folding integral/circulating A/D converterA horizontal shift register 105 to which the converter 104 is connected.
The first control voltages G are respectively outputted from the charge modulation driver 101 to the columns in mutually different phase relations 1 Second control voltage G 2 Third control voltage G 3 Fourth control voltage G 4 Charge discharging voltage G D . At the left side of the pixel array section, pixel columns X11, X21, … …, xi1, … …, xn1 shown in the vertical direction in fig. 12 are followed; x12, X22, … …, xi2, … …, xn2; x1j, X2j, … …, xij, … …, xnj; … …; vertical shift registers 103 are provided in the directions X1m, X2m, … …, xim, … …, xnm. A timing generation circuit, not shown, is connected to the vertical shift register 103 and the horizontal shift register 105. In the solid-state imaging element according to the third embodiment, a signal is read out to the column parallel folded integral/cyclic a/D converter 104 provided at the lower side of the pixel array section to perform a/D conversion, and noise is further eliminated. Thus, the signal level due to the optical charge is extracted, and a signal from which a part of the fixed pattern noise and the time random noise (reset noise) is eliminated is obtained.
As shown in fig. 13, the four-output charge modulation element according to the third embodiment operates using pulsed light having a relatively narrow duty cycle. As shown in fig. 13, during the period of receiving the light pulse of the incident light and accumulating the electric charges modulated by the charge modulating element, the first control voltage G is periodically supplied as shown in fig. 13 1 Second control voltage G 2 Third control voltage G 3 Fourth control voltage G 4 Charge discharging voltage G D The five pulse signals are constituted to operate.
(a) At a first control voltage G 1 At a second potential level H and a second control voltage G 2 Is the first potential level L and the third control voltage G 3 At the first potential level L and the fourth control voltage G 4 During the period of the first potential level L, the signal charges generated in the light receiving region are transferred to the first charge accumulating region 17a shown in fig. 10;
(b) At a second control voltage G 2 Is the firstTwo potential levels H, a first control voltage G 1 Is the first potential level L and the third control voltage G 3 At the first potential level L and the fourth control voltage G 4 During the period of the first potential level L, the signal charges generated in the light receiving region are transferred to the second charge accumulating region 17b shown in fig. 10;
(c) At a third control voltage G 3 At a second potential level H, a first control voltage G 1 Is the first potential level L and the third control voltage G 3 At the first potential level L and the fourth control voltage G 4 During the period of the first potential level L, the signal charges generated in the light receiving region are transferred to the third charge accumulating region 17c shown in fig. 10;
(d) At a fourth control voltage G 4 At a second potential level H, a first control voltage G 1 At a first potential level L and a second control voltage G 2 Is the first potential level L and the third control voltage G 3 During the period of the first potential level L, the signal charges generated in the light receiving region are transferred to the fourth charge accumulating region 17d shown in fig. 10.
(e) On the other hand, at the charge discharging voltage G D At a second potential level H D First control voltage G 1 At a first potential level L and a second control voltage G 2 Is the first potential level L and the third control voltage G 3 At the first potential level L and the fourth control voltage G 4 During the period of the first potential level L, the signal charges generated in the light receiving region are discharged to the first discharge drain region 19a, the second discharge drain region 19b, the third discharge drain region 19c, and the fourth discharge drain region 19d.
At this time, when the light pulse of the incident light arrives at the timing shown in fig. 13, the photoelectric charges are transferred to the second charge accumulating region 17b and the third charge accumulating region 17c. If the charges accumulated in the second and third charge accumulation regions 17b and 17c are Q2 and Q3, this is expressed as:
Q2＝I ph (T 0 -T 4 )+I a T 0 …………(1)
Q3＝I ph T 4 +I a T 0 …………(2)。
Wherein I is ph Is a photocurrent based on signal light pulse, I a Is a photocurrent based on background light, T 0 Is the pulse width of light, T 4 Is the delay time of the light pulse due to the time of flight of the light. At a first control voltage G 1 At a second potential level H and a second control voltage G 2 Is the first potential level L and the third control voltage G 3 At the first potential level L and the fourth control voltage G 4 A period of a first potential level L and a first control voltage G 1 At a first potential level L and a second control voltage G 2 Is the first potential level L and the third control voltage G 3 At the first potential level L and the fourth control voltage G 4 In the second potential level H, since the light pulse does not arrive, a signal caused by only the background light is accumulated. At this time, assuming that the charges stored in the first charge accumulation region 17a and the charges stored in the fourth charge accumulation region 17d are Q1 and Q4, this is expressed as:
Q1＝I a T 0 …………(3)
Q4＝I a T 0 …………(4)。
the influence of the background light included in Q2 and Q3 can be eliminated by using Q1, and the time of flight of light can be estimated. That is, according to the formulas (1), (2) and (3), the time of flight of light is represented by the formula (5):
T d ＝T 0 (Q3-Q1)/(Q2+Q3-2Q1)…………(5)
if the light pulse arrives at the timing of the second incident light of FIG. 13, the light flight time (delay time) at this time is set to T d2 At this time, the charges Q1, Q2, Q3, Q4 respectively accumulated in the first charge accumulation region 17a, the second charge accumulation region 17b, the third charge accumulation region 17c, and the fourth charge accumulation region 17d at this time are as follows:
Q1＝I a T 0 …………(6)
Q2＝I a T 0 …………(7)
Q3＝I ph (2T 0 -T d2 )+I a T 0 …………(8)
Q4＝I ph (2T d2 -T 0 )+I a T 0 …………(9)
t can be obtained using these formulae as shown in the following formula d2 ：
T d2 ＝T 0 +T 0 (Q4-Q1)/(Q4+Q3-2Q1)…………(10)
In this way, when the four-output charge modulation element according to the third embodiment is used, T can be used 0 Pulse width of (2) is at T 0 Distance measurements were made over a range of 2 times the light flight time. By comparing Q2 with Q4, it can be known whether the time of flight of the light pulse is longer than T 0 Large. That is, if Q2 > Q4, the time of flight of the light pulse is calculated using equation (4), and if Q2 is equal to or smaller than Q4, the time of flight of the light pulse is calculated using equation (10).
That is, by applying a fixed potential to the central potential control region 18e shown in fig. 10 and sequentially applying a path selection signal to the four potential control regions 18a, 18b, 18c, and 18d around the central potential control region in accordance with a pulse application pattern determined by a predetermined time chart, the transmission paths formed in the lower portion of the modulation region 14 and the surface-embedded region 13 can be controlled so that signal charges are sequentially accumulated in the four charge accumulation regions 17a, 17b, 17c, and 17d, and a TOF type operation can be efficiently and quickly realized, which is substantially the same as that of the solid-state imaging device according to the second embodiment, and thus, a repetitive description will be omitted.
(fourth embodiment)
The pixel Xij of the solid-state imaging device according to the fourth embodiment of the present invention is configured to have five p as shown in fig. 14 + The pattern of the potential control regions 18a, 18b, 18c, 18d, 18e of the type is based on the pattern, which is common to the planar layout of the pixels Xij of the solid-state imaging device according to the second and third embodiments. As in the second embodiment and the like, these five potential control regions 18a, 18b, 18c, 18d, 18e are buried in the upper portion of the n-type modulation region 14 as shown in fig. 15. In the case of matching the center of the central potential control region 18e with the center of the polar coordinate system, as can be seen from FIG. 14, four potential control regionsThe domains 18a, 18b, 18c, 18d are arranged in a 4-degree rotationally symmetrical topology with the center of the polar coordinate system as the center of rotation. The four potential control regions 18a, 18b, 18c, 18d are arranged as a similar independent planar pattern so as to surround the central potential control region 18e with a space therebetween, as in the second embodiment. However, the pixel Xij of the solid-state imaging device according to the fourth embodiment is different from the pixel Xij of the solid-state imaging device according to the second embodiment in that four pairs of electric field control electrodes 45a1, 45a2 are provided on the outer peripheral side of the arrangement of the four potential control regions 18a, 18b, 18c, 18d in a topology that is rotationally symmetrical 4 times; 45b1, 45b2;45c1, 45c2;45d1, 45d2.
As shown in fig. 14, n is provided in the vicinity of the outside of the first potential control region 18a arranged in the first quadrant Q1 + The first charge accumulation region 17a of the type serves as a floating drain region. Similarly, n is disposed in the vicinity of the outer side of the second potential control region 18b disposed in the second quadrant Q2 + A second charge accumulation region 17b having n arranged in the vicinity of the outer side of the third potential control region 18c arranged in the third quadrant Q3 + A third charge accumulation region 17c having n arranged in the vicinity of the outer side of the fourth potential control region 18d arranged in the fourth quadrant Q4 + The fourth charge accumulation region 17d of the type serves as a floating drain region. The first, second, third and fourth charge accumulation regions 17a, 17b, 17c and 17d are respectively arranged at equal intervals at positions where the long sides of the modulation region 14 of the non-equilateral octagon having the long sides and the short sides alternately arranged are cut out to the outside.
In fig. 14, a pair of first electric field control electrodes 45a1 and 45a2 arranged in the first quadrant Q1 control the transverse electric field of the modulation region 14 between the first electric field control electrodes 45a1 and 45a2 by simultaneously applying a pulse voltage as a transmission signal (transmission voltage) to the first electric field control electrodes 45a1 and 45a2, and thereby generate a potential distribution forming a charge transfer path in which signal charges are transferred between the first electric field control electrodes 45a1 and 45a2 toward the first charge accumulation region 17a in the modulation region 14. That is, by simultaneously applying a pulse voltage as a transfer signal (transfer voltage) to the first electric field control electrode 45a1 and the first electric field control electrode 45a2, thereby the potential gradient in the charge transfer path via the first potential control region 18a is defined to the inside of the modulation region 14 by the electrostatic induction effect, the signal charge generated in the pixel Xij is transferred to the first charge accumulation region 17a. The transfer of the signal charges by the first electric field control electrode 45a1 and the first electric field control electrode 45a2 is not accompanied by scattering of the signal charges due to surface defects or the like generated at the interface between the oxide film and the semiconductor, as in a normal MOS structure, and therefore the charges can be transferred at an extremely high speed.
Similarly, with respect to the pair of second electric field control electrodes 45b1 and 45b2 arranged in the second quadrant Q2, the transverse electric field of the modulation region 14 located between the second electric field control electrodes 45b1 and 45b2 is controlled by a transfer signal (transfer voltage), and the potential gradient in the charge transfer path through the second potential control region 18b is defined by the electrostatic induction effect, so that the signal charge generated in the pixel Xij is transferred to the second charge accumulation region 17b at high speed. In addition, regarding the pair of third electric field control electrodes 45c1 and 45c2 arranged in the third quadrant Q3, the transverse electric field of the modulation region 14 located between the third electric field control electrodes 45c1 and 45c2 is controlled by a transfer signal (transfer voltage), and the potential gradient in the charge transfer path through the third potential control region 18c is defined by the electrostatic induction effect, so that the signal charge generated in the pixel Xij is transferred to the third charge accumulation region 17c at high speed. Further, regarding the pair of the fourth electric field control electrode 45d1 and the fourth electric field control electrode 45d2 arranged in the fourth quadrant Q4, the transverse electric field of the modulation region 14 located between the fourth electric field control electrode 45d1 and the fourth electric field control electrode 45d2 is controlled by a transfer signal (transfer voltage), and the potential gradient in the charge transfer path through the fourth potential control region 18d is defined by the electrostatic induction effect, so that the signal charge generated in the pixel Xij is transferred to the fourth charge accumulation region 17d at high speed.
In the pixel Xij of the solid-state imaging device according to the fourth embodiment, as in the second and third embodiments, a fixed potential of, for example, -1V is applied to the central potential control region 18e, and pulses driven in the mode of (0V, -2V) are sequentially applied to the four potential control regions 18a, 18b, 18c, 18d, whereby the transmission path of the signal charge is sequentially determined. In the solid-state imaging device according to the fourth embodiment, the transfer voltage is sequentially applied to the four pairs of electric field control electrodes 45a1, 45a2 arranged in a topology of 4 times rotational symmetry in each pixel Xij by matching the time charts of the pulses applied to the four potential control regions 18a, 18b, 18c, 18 d; 45b1, 45b2;45c1, 45c2;45d1, 45d2, the signal charges generated by the pixels Xij can be sequentially transferred to the charge accumulation regions 17a, 17b, 17c, 17d outside the modulation region 14 at desired timings.
In fig. 15, the first electric field control electrode 45a2 and the third electric field control electrode 45c1 are exposed in the sectional view of fig. 14 taken along the XV-XV direction. The first electric field control electrode 45a2 and the third electric field control electrode 45c1 are arranged on the gate insulating film 22 shown in fig. 15 to form an insulated gate structure. As shown in fig. 15, a cross-sectional structure of a pixel Xij of a solid-state imaging device according to a fourth embodiment is formed by epitaxially growing p on or above a semiconductor substrate itself - The photoelectric conversion layer 11 is the same as that of the first to third embodiments in that it is a base. The n-type modulation region 14 is disposed on the photoelectric conversion layer 11 through the surface buried region 13. The p-well 12 surrounds the periphery of the modulation region 14. The gate insulating film 22 is formed to cover the p-well 12, the modulation region 14, the first potential control region 18a, the central potential control region 18e, the third potential control region 18c, and the like at the upper portion of the modulation region 14. As the gate insulating film 22, siO 2 Films are suitable, but SiO may also be used 2 An ONO film other than the film, an oxide containing at least any one element of Sr, al, mg, Y, hf, zr, ta, bi, or a silicon nitride containing any one element.
As is clear from fig. 15, an octagonal surface embedded region 13 shown by a broken line in fig. 14 is partially embedded in the bottom of the central portion of the modulation region 14. The impurity density n2 of the surface buried region 13 is higher than the impurity density n1 of the modulation region 14 (n 2 > n 1). The five potential control regions 18a, 18b, 18c, 18d, and 18e each function as a pinning layer for directly controlling the potentials of the modulation region 14 of the embedded portion and the surface embedded region 13 directly below the modulation region, and capturing and discharging the non-signal charges, independently of each other. As shown in fig. 14, the modulation region 14 has an octagonal shape, and the central potential control region 18e disposed at the center thereof has an octagonal shape. The four potential control regions 18a, 18b, 18c, 18d around the central potential control region 18e are each formed in an elongated octagon shape, and are similar in topology to the solid-state imaging devices according to the second and third embodiments.
Fig. 15 is a cross-sectional view as seen from the XV-XV direction in fig. 14, and in fig. 15, the first contact region 16a buried in the right side of the first potential control region 18a, the central contact region 16e buried in the center of the central potential control region 18e, and the third contact region 16c buried in the left side of the third potential control region 18c are exposed. In the plan view of FIG. 14, in addition to the above, it is shown that p is provided in the vicinity of the inner side of the center portion of the side outside the second potential control region 18b + A second contact region 16b having p arranged in the vicinity of the inner side of the central portion of the side outside the fourth potential control region 18d + Fourth contact region 16d of the type. In the cross-sectional structure of fig. 15, the interlayer insulating film, the contact plug penetrating the interlayer insulating film, or the surface wiring connected to the first contact region 16a or the like via the contact plug is omitted as in fig. 2, 9, and 11.
As shown in fig. 14, in the solid-state imaging device according to the fourth embodiment, the first drain region 19a, the second drain region 19b, the third drain region 19c, and the fourth drain region 19d are arranged so as to meet the short sides of the modulation region 14 having the unequal-sided octagon shape. As shown in fig. 14, a first drain gate electrode 43a is provided so as to cover the upper end portion of the first potential control region 18a, the right end portion of the second potential control region 18b, and a part of the first drain region 19a through a gate insulating film 22, which is not shown in fig. 14. Similarly, the second drain gate electrode 43b is provided so as to cover the left end portion of the second potential control region 18b, the upper end portion of the third potential control region 18c, and a part of the second drain region 19 b. The third drain gate electrode 43c is provided so as to cover the lower end portion of the third potential control region 18c, the left end portion of the fourth potential control region 18c, and a part of the third drain region 19c, and the fourth drain gate electrode 43d is provided so as to cover the right end portion of the fourth potential control region 18d, the lower end portion of the first potential control region 18c, and a part of the fourth drain region 19 d.
According to the pixel Xij of the solid-state imaging device according to the fourth embodiment, by applying a fixed potential to the central potential control region 18e shown in fig. 14 and sequentially applying a path selection signal to the four potential control regions 18a, 18b, 18c, 18d around the central potential control region according to the pulse application pattern determined by the same time chart as that shown in fig. 13, the transmission paths formed in the lower part of the modulation region 14 and the surface buried region 13 can be controlled so that signal charges are sequentially accumulated in the four charge accumulation regions 17a, 17b, 17c, 17d, thereby realizing a TOF type operation. At this time, four pairs of electric field control electrodes 45a1, 45a2 are connected in synchronization with the path selection signal; 45b1, 45b2;45c1, 45c2;45d1, 45d2 are sequentially applied with transfer voltages, whereby the signal charges generated by the pixels Xij can be transferred to the charge accumulating regions 17a, 17b, 17c, 17d at a higher speed than the solid-state imaging devices according to the second and third embodiments. By applying positive potentials to the drain gate electrodes 43a, 43b, 43c, and 43d shown in fig. 14, electrons, which become dark current and background light components, of the pixel Xij of the solid-state imaging device according to the fourth embodiment can be discharged to the drain regions 19a, 19b, 19c, and 19d. Other structures, operations, and features are substantially the same as those of the solid-state imaging device according to the second and third embodiments including the five potential control regions 18a, 18b, 18c, 18d, and 18e, and therefore, duplicate descriptions thereof are omitted.
Variation of the fourth embodiment
The pixels Xij of the solid-state imaging device according to the modification of the fourth embodiment of the present invention are arranged in five p as shown in fig. 16 + The pattern of the potential control regions 18a, 18b, 18c, 18d, and 18e is based on the pattern, and this is common to the planar layout of the pixels Xij of the solid-state imaging device according to the second to fourth embodiments. As in the second to fourth embodiments, these five potential control regions 18a, 18b, 18c, 18d, 18e are buried in the upper portion of the n-type modulation region 14 as shown in fig. 17. In addition, the pixel Xij of the solid-state imaging device according to the modification of the fourth embodiment includes four pairs of electric field control electrodes 45a1, 45a2 on the outer peripheral side of the arrangement of the four potential control regions 18a, 18b, 18c, 18d in a topology that is rotationally symmetrical 4 times; 45b1, 45b2;45c1, 45c2;45d1, 45d2 are common to the planar structure of the pixel Xij of the solid-state imaging device according to the fourth embodiment shown in fig. 14. However, as shown in fig. 16, the structure of the pixel Xij of the solid-state imaging device according to the fourth embodiment is different in that the auxiliary gate electrode 41 is provided between the central potential control region 18e and the four potential control regions 18a, 18b, 18c, 18 d.
The auxiliary gate electrode 41 is arranged on the gate insulating film 22 shown in fig. 17 in a planar pattern as shown by way of example in fig. 16, and an insulating gate structure is formed. As shown in fig. 17, a cross-sectional structure of a pixel Xij of a solid-state imaging device according to a modification of the fourth embodiment is p epitaxially grown on or above a semiconductor substrate itself - The photoelectric conversion layer 11 is a base body. An n-type modulation region 14 is disposed on the photoelectric conversion layer 11 through a surface buried region 13. The p-well 12 surrounds the periphery of the modulation region 14. The gate insulating film 22 is formed to cover the p-well 12, the modulation region 14, the first potential control region 18a, the central potential control region 18e, the third potential control region 18c, and the like at the upper portion of the modulation region 14. As the gate insulating film 22, siO removal 2 In addition to the film, various insulating films such as an ONO film and an oxide containing an element such as Sr, al, mg, Y can be used.
The planar pattern of the auxiliary gate electrode 41 shown in fig. 16 is a ring-shaped topology in which a part of the outer peripheral side of the central potential control region 18e and a part of the inner peripheral side of the arrangement of the four potential control regions 18a, 18b, 18c, 18d are covered on top, and is common to the planar pattern of the pixel Xij of the solid-state imaging device according to the third embodiment shown in fig. 10. As shown in fig. 16, the auxiliary gate electrode 41 is formed in a planar pattern of a topology that surrounds the outer periphery of the central potential control region 18e so as to reach the first potential control region 18a, whereby a first insulated gate transistor (MIS transistor) is formed between the central potential control region 18e and the first potential control region 18 a. Similarly, the auxiliary gate electrode 41 forms a second MIS transistor common to the first MIS transistor between the central potential control region 18e and the second potential control region 18b by a pattern in which the auxiliary gate electrode 41 surrounds the outer peripheral side of the central potential control region 18e so as to reach the second potential control region 18 b. The auxiliary gate electrode 41 forms a third MIS transistor between the central potential control region 18e and the third potential control region 18c, forms a fourth MIS transistor between the central potential control region 18e and the fourth potential control region 18d, and has the auxiliary gate electrode 41 common to the first MIS transistor.
P is provided near the inner side of the central portion of the side outside the first potential control region 18a + A first contact region 16a of the type. Similarly, p is provided in the vicinity of the inner side of the central portion of the side outside the second potential control region 18b + A second contact region 16b of the type. P is disposed in the vicinity of the inner side of the central portion of the side outside the third potential control region 18c + A third contact region 16c having p arranged in the vicinity of the inner side of the central portion of the side outside the fourth potential control region 18d + Fourth contact region 16d of the type.
Fig. 17 is a cross-sectional view of fig. 16 viewed from the direction XVII-XVII, and in fig. 17, the first contact region 16a buried in the right side of the first potential control region 18a, the central contact region 16e buried in the center of the central potential control region 18e, and the third contact region 16c buried in the left side of the third potential control region 18c are exposed. Further, the first charge accumulation region 17a is exposed near the right side of the first potential control region 18a, and the third charge accumulation region 17c is exposed near the left side of the third potential control region 18 c. In fig. 17, the auxiliary gate electrode 41 of the first MIS transistor formed between the central potential control region 18e and the second potential control region 18b is shown on the right side, and the auxiliary gate electrode 41 of the third MIS transistor formed between the central potential control region 18e and the third potential control region 18c is shown on the left side. Further, the first electric field control electrode 45a2 is shown on the right side of the right auxiliary gate electrode 41, and the third electric field control electrode 45c1 is exposed on the left side of the left auxiliary gate electrode 41. The auxiliary gate electrode 41 on the right side and the auxiliary gate electrode 41 on the left side, which are shown as separate patterns in fig. 17, are continuous integral members as shown in fig. 16.
The pair of first electric field control electrodes 45a1 and 45a2 illustrated in fig. 16 transfers the signal charges generated in the pixel Xij to the first charge accumulating region 17a at a high speed by applying a transfer signal to the first electric field control electrodes 45a1 and 45a2, thereby controlling the lateral electric field of the modulation region 14 between the first electric field control electrodes 45a1 and 45a 2. The pair of second electric field control electrodes 45b1 and 45b2 controls the lateral electric field of the modulation region 14 located between the second electric field control electrodes 45b1 and 45b2 by a transfer signal, and transfers the signal charge to the second charge accumulation region 17b at a high speed along the charge transfer path via the second potential control region 18 b. In addition, the pair of third electric field control electrodes 45c1 and 45c2 controls the lateral electric field of the modulation region 14 located between the third electric field control electrodes 45c1 and 45c2 by a transfer signal, and transfers the signal charge to the third charge accumulation region 17c at a high speed along the charge transfer path via the third potential control region 18 c. Further, the pair of fourth electric field control electrodes 45d1 and 45d2 controls the lateral electric field of the modulation region 14 located between the fourth electric field control electrode 45d1 and 45d2 by the transfer signal, and transfers the signal charge to the fourth charge accumulation region 17d at a high speed along the charge transfer path via the fourth potential control region 18 d.
In practice, an interlayer insulating film is covered so as to cover the first electric field control electrode 45a2, the third electric field control electrode 45c1, the auxiliary gate electrode 41, and the gate insulating film 22 shown in fig. 17. However, in the cross-sectional structure of fig. 17, illustration of the interlayer insulating film, the contact plug penetrating the interlayer insulating film, and the surface wiring connected to the first contact region 16a and the like via the contact plug is omitted as in fig. 2 and 9.
The position coordinates X21, X22, X23, … …, X30 in the plane direction (X direction) are shown on the upper side of fig. 17, and the curve indicated by the solid line of fig. 18 shows the potential distribution at the level of the pixel Xij shown in fig. 17 along the xviia-xviia direction. In addition, a curve of a broken line of fig. 18 shows a potential distribution at a level of the pixel Xij shown in fig. 17 in the xviib-xviib direction. As shown in fig. 18, a potential distribution on the upper surface side of the pixel horizontally sectioned along the direction of xviia-xviia in a state where the first control voltage g1= -2V is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3=0v is applied to the third potential control region 18c, a substantially constant zero potential is shown in a range (left side of the coordinate x 21) at the p-well 12 on the left side, and a potential well is shown at a position (between the coordinates x21-x 22) of the third charge accumulation region 17 c. Further, the potential distribution in the horizontal direction at the shallow position in the direction of xviia-xviia shows a potential of about 1V at a position (between coordinates x22 to x 23) directly below the third electric field control electrode 45c1 between the third electric charge accumulation region 17c and the third electric potential control region 18c and then rises until a position (coordinate x 23) of the left end of the third electric potential control region 18 c. Then, after a substantially constant zero potential is shown at the position (between coordinates x23 to x 24) of the third potential control region 18c, a potential valley is shown at the gap position (between coordinates x24 to x 25) between the third potential control region 18c and the central potential control region 18 e.
After the X-axis is shifted further rightward, a potential of approximately-1V is shown at the position of the central potential control region 18e (between coordinates X25 to X26), and then a potential valley is shown at the gap position between the central potential control region 18e and the first potential control region 18a (between coordinates X26 to X27). After a substantially constant peak voltage of-2V is shown at the position (between coordinates x27 to x 28) of the first potential control region 18a, a potential of about-1V is shown at the position (between coordinates x28 to x 29) directly below the first electric field control electrode 45a2 between the first potential control region 18a and the first charge accumulation region 17a, and then a potential well is shown at the position (between coordinates x29 to x 30) of the first charge accumulation region 17 a. Then, the X-axis is shifted further rightward, and a substantially constant zero potential is again shown in the range of the p-well 12 on the right side (right side of the coordinate X30).
As shown in fig. 18, the potential distribution on the upper surface side of the pixel horizontally sectioned along the direction of xviia-xviia in the state where the first control voltage g1= -2V is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3=0v is applied to the third potential control region 18c is such that the hook structure of the pnp type BJT having the third potential control region 18c as the emitter, the central potential control region 18e as the collector, and the hook structure of the pnp type BJT having the central potential control region 18e as the emitter and the first potential control region 18a as the collector are connected in series.
The potential distribution at a deep position, as shown by the broken line in fig. 18, where the surface embedded region 13 of the pixel is horizontally sectioned along the direction xviii b-xviii b in a state where the first control voltage g1= -2V is applied to the first potential control region 18a, the fixed potential g0= -1V is applied to the central potential control region 18e, and the third control voltage g3=0v is applied to the third potential control region 18c, shows a relatively gentle change. Starting from the potential well at the position of the third charge accumulation region 17c (between the coordinates x21 to x 22), the potential is shifted rightward, and the potential decreases from the position immediately below the third electric field control electrode 45c1 between the third charge accumulation region 17c and the third potential control region 18c, until the position of the third potential control region 18c (between the coordinates x22 to x 24) shows a potential of approximately constant about 1.8V. Thereafter, the gap between the third potential control region 18c and the central potential control region 18e is reduced to about 0.2V from the position of the first potential control region 18a (between coordinates x24 to x 28), and after the position of the gap between the first potential control region 18a and the first charge accumulation region 17a (between coordinates x28 to x 29) is at a certain potential of about 0.2V, a potential well is shown at the position of the first charge accumulation region 17a (between coordinates x29 to x 30).
As is clear from the potential distribution in fig. 18, by applying a fixed potential to the central potential control region 18e shown in fig. 16 and sequentially applying a path selection signal to the four potential control regions 18a, 18b, 18c, 18d around the central potential control region in accordance with a pulse application pattern determined by a predetermined time chart, the transmission paths formed in the lower portion of the modulation region 14 and the surface-embedded region 13 can be controlled so that signal charges are sequentially accumulated in the four charge accumulation regions 17a, 17b, 17c, 17d, and a TOF type operation can be realized.
In addition, if the time chart of fig. 13 used in the third embodiment is slightly modified so that the first control voltage G1, the second control voltage G2, the third control voltage G3, and the fourth control voltage G4 are not driven, for example, so that g1=g2=g3=g4=0v is applied to the auxiliary gate electrode 41, the potential barrier against the non-signal charges is eliminated. When a negative voltage (non-signal charge inducing pulse) is applied to the auxiliary gate electrode 41, the auxiliary gate electrode 41 induces a non-signal charge directly under the auxiliary gate electrode 41, and the non-signal charge is discharged from directly under the auxiliary gate electrode 41 to the surface wiring via the central potential control region 18e maintained at a fixed potential g0= -1V. On the other hand, if a positive voltage is applied to the auxiliary gate electrode 41 in a state where the first control voltage G1, the second control voltage G2, the third control voltage G3, and the fourth control voltage G4 are not driven, the potential barrier against the non-signal charges increases. Since the potential barrier against the non-signal charges serves as a potential well for electrons that are dark current and background light components, electrons that are dark current and background light components right under the auxiliary gate electrode 41 can be discharged to the discharge drain regions 19a, 19b, 19c, and 19d by applying a positive potential to the discharge gate electrodes 43a, 43b, 43c, and 43 d. That is, the auxiliary gate electrode 41 can assist the discharge of electrons, which are a dark current and a background light component, to the discharge drain regions 19a, 19b, 19c, and 19d.
By applying a positive potential to the discharge gate electrodes 43a, 43b, 43c, and 43d shown in fig. 16, electrons, which become dark current and background light components, of the pixel Xij of the solid-state imaging device according to the modification of the fourth embodiment can be discharged to the discharge drain regions 19a, 19b, 19c, and 19d. Other structures, operations, and features are substantially the same as those of the solid-state imaging device according to the second to fourth embodiments including the five potential control regions 18a, 18b, 18c, 18d, and 18e, and therefore, duplicate descriptions thereof are omitted.
(other embodiments)
As described above, the present invention has been described in the first to fourth embodiments, but the descriptions and drawings constituting a part of this disclosure should not be construed as limiting the present invention. Various alternative embodiments, examples, and techniques of application will be apparent to those skilled in the art from this disclosure. For example, in the descriptions of the first to fourth embodiments described above, a case where one transmission path is defined for each potential control region and one charge accumulation region is allocated to each potential control region is exemplified. However, a plurality of transmission paths may be defined for each potential control region. That is, it is needless to say that a plurality of charge accumulation regions may be allocated to each potential control region, and signal charges may be transferred from each potential control region along a plurality of transfer paths independently of each other.
< other embodiments: one >
For example, in the structures described in the first to fourth embodiments, when a component of slow signal charges that move in the neutral region at a diffusion rate is present in the deep portion of the photoelectric conversion layer 11, it is difficult to operate the pixel Xij at a high speed. When it is necessary to transfer electrons (signal charges) generated in the photoelectric conversion layer 11 at a position deep from the surface at a high speed, the semiconductor substrate 51 of the p-type is suitably used as shown in fig. 19The density of the extended impurities is, for example, 3X 10 18 ～2×10 19 cm -3 P of (2) + A back-side bias layer 10, and a continuous epitaxial growth of impurity density of, for example, 5×10 over the back-side bias layer 10 12 ～1×10 14 cm -3 P of (2) - The structure of the type photoelectric conversion layer 11.
By applying a negative voltage to the back-side bias layer 10, substantially the entire photoelectric conversion layer 11 is depleted from the surface of the photoelectric conversion layer 11, and thus the signal charges generated in the photoelectric conversion layer 11 can move at a high speed by the drift electric field. By the structure shown in fig. 19, the depletion layer is spread over the entire photoelectric conversion layer 11, and thus the signal charge can be moved at a high speed by the drift electric field in the depletion layer, and the pixel Xij can be operated at a high speed.
< other embodiments: two >
In the structure shown in fig. 19, when a problem occurs due to injection of holes from the p-well 12 into the photoelectric conversion layer 11, if the n-type shielding region 52 is provided to prevent injection of holes that are non-signal charges as shown in fig. 20, the depletion layer is spread over the entire photoelectric conversion layer 11, and thus an increase in power consumption due to injection of holes from the p-well 12 into the photoelectric conversion layer 11 can be avoided, and the pixel Xij can be operated at high speed.
< other embodiments: three >
Fig. 21 shows a structure in which a p-type well region (first p-well) 12a surrounding the inner side of the surface buried region 13 and an n-type tab region (n-tab) 53 surrounding the first p-well 12a in a wall shape are surrounded by an outer side p-type well region (second p-well) 12b surrounding the outer side of the n-tab 53. The cross-sectional structure of fig. 21 corresponds to the topology in which the p-type well region 12 shown in fig. 19 and 20 is divided into two parts, i.e., the first p-well 12a and the second p-well 12b, by the n-tab 53.
That is, as shown in the cross-sectional view of fig. 21, even in a structure in which two well regions, i.e., the first p-well 12a and the second p-well 12b, are formed by the n-tab 53, a potential barrier against holes (holes) can be formed on the lower surfaces of the first p-well 12a and the second p-well 12 b. Thus, according to the pixel Xij of the solid-state imaging device according to the other embodiment shown in fig. 21, holes can be suppressed from being injected into the photoelectric conversion layer 11 from the first p-well 12a and the second p-well 12b in a state in which the depletion layer is spread over the entire photoelectric conversion layer 11 and the pixel Xij is operated at a high speed.
< other embodiments: four >
In the description of the above-described first to fourth embodiments, descriptions on the specific layout of the MOS transistor group constituting the "in-pixel circuit element" such as the reset transistor, the readout transistor, the switching transistor, and the like illustrated in fig. 3 are omitted. When the MOS transistor group constituting the circuit element in the pixel is a normal CMOS process, an n-type source/drain region is generally formed on the p-well 12 shown in fig. 2, 8, and the like. However, as shown in fig. 22 and 23, an SOI substrate may be used to form a MOS transistor over the SOI insulating film 23 as an in-pixel circuit element.
For example, the SOI substrate can be formed by forming the SOI insulating film 23 by the SIMOX method using ion implantation of oxygen. Alternatively, the SOI substrate may be formed by directly bonding two silicon substrates via the SOI insulating film 23 by a bonding method. Furthermore, an SOI substrate may be formed by an ELTRAN (registered trademark) method based on epitaxial growth. In addition, the SOI structure formed by the bonding method may be formed by a smart cut method using a dicing method using a hydrogen embrittlement phenomenon by implantation of hydrogen ions, or the like.
Fig. 22 is a plan view showing a case where source/ drain regions 71a and 71b of MOS transistors are arranged so as to sandwich a gate electrode 72a, and source/ drain regions 71c and 71d of MOS transistors are arranged so as to sandwich a gate electrode 72b, thereby forming a part of a circuit element in a pixel. As is clear from fig. 23, source/ drain regions 71a, 71b,71c, 71d constituting a part of the MOS transistor group of the circuit element in the pixel are formed of single crystal silicon which is an SOI silicon thin film layer (SOI layer) formed on the SOI insulating film 23. As can be seen from fig. 23, a channel region 73a made of an SOI layer is formed immediately below the gate electrode 72a, and source/ drain regions 71a and 71b are disposed on both sides so as to sandwich the channel region 73 a. Similarly, a channel region 73b made of an SOI layer is formed immediately below the gate electrode 72b, and the source/ drain regions 71c and 71d are disposed so as to sandwich the channel region 73 b. Gate insulating films 27 for in-pixel circuit elements are disposed between the gate electrode 72a and the channel region 73a and between the gate electrode 72b and the channel region 73b, respectively, to realize a gate structure of a MOS transistor.
The pixel Xij shown in fig. 22 has four p + The configuration of the solid-state imaging device according to the other embodiments of the potential control regions 15a, 15b, 15c, and 15d is common to the configuration shown by way of example in the first embodiment shown in fig. 1. However, as shown in fig. 23, the four potential control regions 15a, 15b, 15c, and 15d are buried in the upper portion of the n-type modulation region 14 formed of a silicon substrate which is a support substrate of an SOI structure.
As is clear from fig. 23, the octagonal surface embedded region 13 shown by a broken line in fig. 22 is partially embedded in the bottom of the central portion of the modulation region 14. P is arranged in the first potential control region 15a + The first contact region 16a and the second potential control region 15b are provided with p + A second contact region 16b and a third potential control region 15c are provided with p + A third contact region 16c and a fourth potential control region 15d are provided with p + The configuration of the fourth contact region 16d of the mold is also common to the configuration shown by way of example in the first embodiment. As shown in fig. 22, four charge accumulation regions 17a, 17b, 17c, 17d for sequentially accumulating the signal charges transferred by the electrostatic induction effect through the four potential control regions 15a, 15b, 15c, 15d are arranged outside the four potential control regions 15a, 15b, 15c, 15d, respectively, as floating drain regions.
As shown in fig. 23, p is provided on the back surface of the photoelectric conversion layer 11 + A backside bias layer 10 of the type. As in the structure shown in fig. 20, a negative voltage can be applied to the back-side bias layer 10 to deplete substantially the entire photoelectric conversion layer 11 from the surface of the photoelectric conversion layer 11. In addition, since the n-type shielding region 77 is provided to block injection of holes that are non-signal charges, as in the structure shown in fig. 20, the depletion layer can be prevented from passing through the p-well 1 while expanding the entire photoelectric conversion layer 11 2 the power consumption by injecting holes into the photoelectric conversion layer 11 increases, and the signal charge can be moved at a high speed by the drift electric field in the depletion layer.
< other embodiments: five >
As is clear from fig. 24 and 25, a MOS transistor group constituting the in-pixel circuit element of each pixel Xij of the solid-state imaging device according to the other embodiment is further provided on the SOI insulating film 23. As shown in fig. 25, the feature that the first transfer gate electrode 47a and the third transfer gate electrode 47c constituting the transfer transistor are provided over the SOI insulating film 23 is different from the configuration shown in fig. 23. The thickness of the SOI insulating film 23 is selected to be about 50 to 200nm so that the transfer gate electrodes such as the first transfer gate electrode 47a and the third transfer gate electrode 47c can transfer signal charges efficiently. The SIMOX method is suitable for forming a thin SOI insulating film 23 of about 200nm or less, but is not limited to the SIMOX method. In order to improve the efficiency of the transfer gate electrodes such as the first transfer gate electrode 47a and the third transfer gate electrode 47c, the SOI insulating film 23 directly under the transfer gate electrode may be removed to form a thin gate oxide film on the surface of the silicon substrate as a support substrate of the SOI structure instead.
As is clear from fig. 25, a channel region 73a made of an SOI layer is formed immediately below a gate electrode 72a of a MOS transistor constituting a circuit element in a pixel, and source/ drain regions 71a and 71b made of an SOI layer are disposed on both sides so as to sandwich the channel region 73 a. Similarly, a channel region 73b formed of an SOI layer is formed immediately below the gate electrode 72b of the MOS transistor constituting the in-pixel circuit element, and source/ drain regions 71c and 71d formed of the SOI layer are disposed so as to sandwich the channel region 73 b. Gate insulating films 27 for in-pixel circuit elements are disposed between the gate electrode 72a and the channel region 73a and between the gate electrode 72b and the channel region 73b, respectively, to realize a gate structure of a MOS transistor.
As for the structure of the photodiode section, four potential control regions 15a, 15b, 15c, 15d are buried in the upper portion of an n-type modulation region 14 composed of a silicon substrate as a support substrate of an SOI structure as shown in fig. 25, similarly to the structure shown in fig. 23.A surface buried region 13 shown by a broken line in fig. 24 is buried in the bottom of the modulation region 14. P is arranged in the first potential control region 15a + The first contact region 16a and the second potential control region 15b are provided with p + A second contact region 16b and a third potential control region 15c are provided with p + A third contact region 16c and a fourth potential control region 15d are provided with p + The configuration of the fourth contact region 16d of the form is also common to the configuration shown in fig. 23. As shown in fig. 24, four charge accumulation regions 17a, 17b, 17c, 17d for sequentially accumulating the signal charges transferred by the electrostatic induction effect through the four potential control regions 15a, 15b, 15c, 15d are arranged outside the four potential control regions 15a, 15b, 15c, 15d, respectively, as floating drain regions. A first transfer gate electrode 47a is provided between the first potential control region 15a and the first charge accumulation region 17 a. A second transfer gate electrode 47b is provided between the second potential control region 15b and the second charge accumulation region 17b, a third transfer gate electrode 47c is provided between the third potential control region 15c and the third charge accumulation region 17c, and a fourth transfer gate electrode 47d is provided between the fourth potential control region 15d and the fourth charge accumulation region 17 c.
As shown in fig. 25, p is provided on the back surface of the photoelectric conversion layer 11 + The structure of the back-side bias layer 10 of the mold is the same as that of fig. 23. A negative voltage can be applied to the back-side bias layer 10 to deplete substantially the entire photoelectric conversion layer 11 from the surface of the photoelectric conversion layer 11. In addition, since the n-type shield region 77 is provided to block injection of holes in the same manner as in the structure shown in fig. 23, it is possible to avoid an increase in power consumption due to injection of holes from the p-well 12 into the photoelectric conversion layer 11 in a state where the depletion layer is spread over the entire photoelectric conversion layer 11, and to move the signal charges at a high speed by a drift electric field in the depletion layer.
< other embodiments: six >
As a solid-state imaging device using the photoelectric conversion element according to another embodiment of the present invention, as shown in fig. 27, a microlens 2 that condenses light from an object and makes the condensed light enter a light receiving region PD may be provided above a shielding plate 1. Since the aperture ratio can be increased by making light incident through the microlens 2, the solid-state imaging device can have higher sensitivity. The photoelectric conversion element according to the other embodiment shown in fig. 27 can also have an effect of enabling TOF-type high-speed operation with low power consumption, similar to the photoelectric conversion element shown in fig. 1 to 2, 6, 8 to 11, 14 to 17, 19 to 25, and the like. Note that the microlens is not limited to the single-layer structure as illustrated in fig. 27, and can be further miniaturized by combining a composite structure of two or more layers into the photoelectric conversion element.
In the description of the structure of the solid-state imaging device according to the other embodiments shown in fig. 19 to 25 and 27, the use of the p-type semiconductor substrate 51 and the p-type arranged on the semiconductor substrate 51 are exemplified + The back side bias layer 10 is not limited to the p-type semiconductor substrate 51. Instead of using the p-type semiconductor substrate 51, an n-type semiconductor substrate may be used, and instead of using the p-type semiconductor substrate 51, an insulator substrate may be used. Furthermore, p may also be employed in the backside bias layer 10 + The semiconductor substrate itself.
In using p + In the case of a semiconductor substrate of the type, the thickness of the semiconductor substrate may be adjusted to be 5 to 10 μm or less by grinding, CMP or the like in consideration of the light attenuation distance, and the semiconductor substrate may be a back-illuminated solid-state imaging device. In the case of a back-illuminated solid-state imaging device, it is preferable to bond an interlayer insulating film on the upper surface of a support substrate such as a Si substrate via the upper surface by a bonding method or the like to secure mechanical strength. Further, a deep trench (through hole) penetrating the photoelectric conversion layer may be formed around the chip by ion polishing or RIE, and p-type impurities may be diffused into the sidewall of the through hole to apply a reverse bias from the back side. Further, a conductor such as a high-melting point metal may be embedded in the through hole to form a TSV, and a reverse bias may be applied from the back surface side. Furthermore, only p just below the surface-buried region 13 shown in fig. 2 may be used - The semiconductor substrate has a region selectively formed with a recess of 5-10 μm or less so as to pass through the periphery thereofA frame-shaped thick semiconductor substrate is mechanically secured to form a back-illuminated solid-state imaging device.
In the description of the first to fourth embodiments, the description has been made with the first conductivity type being p-type and the second conductivity type being n-type, but it is easy to understand that the same effect can be obtained if the first conductivity type is n-type and the second conductivity type is p-type, and the electric polarities are opposite. In this case, for example, the modulation region 14 shown in fig. 2 may be appropriately inverted in polarity to be a "light receiving anode region". In the description of the first to fourth embodiments, the signal charge is an electron and the non-signal charge of the opposite conductivity type to the signal charge is a hole (hole), but when the polarity is reversed, the signal charge is a hole and the non-signal charge is an electron.
In the description of the first to fourth embodiments, the two-dimensional solid-state image pickup device (area sensor) is exemplified, but it should not be construed in a limiting sense that the pixel Xij of the present invention is used only as the pixel Xij of the two-dimensional solid-state image pickup device. It should be readily understood from the above disclosure that a plurality of pixels Xij may be one-dimensionally arranged as pixels Xij of a one-dimensional solid-state image pickup device (line sensor) of j=m=1 in a two-dimensional matrix shown in fig. 1, for example.
Thus, the present invention naturally includes various embodiments and the like not described herein. Accordingly, the technical scope of the present invention is defined only by the specific matters of the invention according to the claims appropriately derived from the above description.
Description of the reference numerals
1 … shielding plate
2 … microlens
10 … backside bias layer
11 … photoelectric conversion layer
12 … well region (p-well)
12a … first p-well
12b … second p-well
Edge of inner side of 12i … well region (p-well)
13 … surface buried region
14 … modulation region
15a … first potential control region
15b … second potential control region
15c … third potential control region
15d … fourth potential control area
16a … first contact area
16b … second contact region
16c … third contact region
16d … fourth contact area
16e … central contact area
17a, 18a … first charge accumulating region
17b, 18b … second charge accumulating region
17c, 18c … third charge accumulating region
17d, 18d … fourth charge accumulating region
18e … central potential control region
19a … first drain region
19b … second drain region
19c … third drain region
19d … fourth drain region
21 … interlayer insulating film
22 … gate insulating film
31-38 … surface wiring
41 … auxiliary gate electrode
43a … first drain gate electrode
43b … second drain gate electrode
43c … third discharge gate electrode
43d … fourth discharge gate electrode
45a1, 45a2 … first electric field control electrode
45b1, 45b2 … second electric field control electrode
45c1, 45c2 … third electric field control electrode
45d1, 45d2 … fourth electric field control electrode
51 … semiconductor substrate
52 … shielding region
53 … n tab
Claims (10)
1. A charge modulation element, comprising:
a photoelectric conversion layer of a first conductivity type;
a surface buried region of a second conductivity type buried in a part of an upper portion of the photoelectric conversion layer, and forming a photodiode with the photoelectric conversion layer;
a modulation region of a second conductivity type, which is buried in a portion of the upper portion of the photoelectric conversion layer on the upper surface side of the surface buried region of the upper portion of the photoelectric conversion layer, and which forms a part of the structure of the photodiode together with the photoelectric conversion layer, the modulation region having an impurity density lower than that of the surface buried region;
A potential control region dividing the modulation region into a plurality of regions with a center of the modulation region as a center of a polar coordinate, the potential control regions being disposed in the divided regions, respectively, the potential control region being of a first conductivity type, and an impurity density of the potential control region being higher than an impurity density of the photoelectric conversion layer; and
a second-conductivity-type charge accumulation region disposed at a plurality of positions adjacent to the potential control region on an outer peripheral side of each of the plurality of divided regions, spaced apart from the potential control region, and temporarily accumulating signal charges generated by the photodiodes and transferred along mutually independent transfer paths,
the transmission path is selected by controlling the potentials of the modulation region and the surface-buried region by a path selection signal as a pulse voltage applied to the potential control region.
2. The charge modulation element of claim 1 wherein the charge modulated element comprises,
a plurality of the charge accumulation regions are allocated to respective ones of the potential control regions such that the signal charges are transferred from the respective ones of the potential control regions along a plurality of transfer paths independently of each other.
3. The charge modulation element of claim 1 wherein the charge modulated element comprises,
the charge modulation element further includes a central potential control region of the first conductivity type centered on the center of the polar coordinate at the center of the arrangement of the plurality of potential control regions,
the central potential control region is applied with a fixed potential.
4. The charge-modulated element of claim 3,
the charge modulation element further includes:
a gate insulating film covering a region from an upper surface on an outer peripheral side of the pattern of the central potential control region to an upper surface on an inner peripheral side of the pattern of the potential control regions along an inner peripheral side of the plurality of arrangements; and
an auxiliary gate electrode disposed on an upper surface of the gate insulating film,
at a timing when the path selection signal is not applied, a non-signal charge inducing pulse is applied to the auxiliary gate electrode to induce a non-signal charge, which is a carrier of a conductivity type opposite to that of the signal charge, directly under the auxiliary gate electrode.
5. The charge modulation element of any one of claims 1 to 4 wherein,
The charge modulation element further includes a back-side bias layer of a first conductivity type on a lower surface of the photoelectric conversion layer, the back-side bias layer having an impurity density higher than that of the photoelectric conversion layer,
the photoelectric conversion layer is depleted by a voltage applied to the backside bias layer.
6. A solid-state image pickup device is characterized in that,
integrating a pixel array section in which a plurality of pixels are arranged and a peripheral circuit section which drives the pixels and processes signals from the pixels on the same semiconductor chip,
the pixel has:
a photoelectric conversion layer of a first conductivity type;
a surface buried region of a second conductivity type buried in a part of an upper portion of the photoelectric conversion layer, and forming a photodiode with the photoelectric conversion layer;
a modulation region of a second conductivity type, which is buried in a portion of the upper portion of the photoelectric conversion layer on the upper surface side of the surface buried region of the upper portion of the photoelectric conversion layer, and which forms a part of the structure of the photodiode together with the photoelectric conversion layer, the modulation region having an impurity density lower than that of the surface buried region;
A potential control region dividing the modulation region into a plurality of regions with a center of the modulation region as a center of a polar coordinate, the potential control regions being disposed in the divided regions, respectively, the potential control region being of a first conductivity type, and an impurity density of the potential control region being higher than an impurity density of the photoelectric conversion layer; and
a second-conductivity-type charge accumulation region disposed at a plurality of positions adjacent to the potential control region on an outer peripheral side of each of the plurality of divided regions, spaced apart from the potential control region, and temporarily accumulating signal charges generated by the photodiodes and transferred along mutually independent transfer paths,
in each of the pixels, the transmission paths of the pixels are selected by controlling the potentials of the modulation region and the surface buried region by a path selection signal as a pulse voltage applied to the potential control region.
7. The solid-state imaging device according to claim 6, wherein,
in each of the pixels,
a plurality of the charge accumulation regions are allocated to respective ones of the potential control regions such that the signal charges are transferred from the respective ones of the potential control regions along a plurality of transfer paths independently of each other.
8. The solid-state imaging device according to claim 6, wherein,
each of the pixels further has a central potential control region of the first conductivity type centered on the center of the polar coordinates at the center of the arrangement of the plurality of potential control regions,
in each of the pixels, the central potential control region is applied with a fixed potential.
9. The solid-state imaging device according to claim 8, wherein,
each of the pixels further includes:
a gate insulating film covering a region from an upper surface on an outer peripheral side of the pattern of the central potential control region to an upper surface on an inner peripheral side of the pattern of the potential control regions along an inner peripheral side of the plurality of arrangements; and
an auxiliary gate electrode disposed on an upper surface of the gate insulating film,
a non-signal charge inducing pulse is applied to the auxiliary gate electrode at a timing when the path selection signal of each of the pixels is not applied to induce a non-signal charge, which is a carrier of a conductivity type opposite to that of the signal charge, directly under the auxiliary gate electrode.
10. The solid-state imaging device according to any one of claims 6 to 9, wherein,
The solid-state image pickup device further includes a back-side bias layer of a first conductivity type on a lower surface of the photoelectric conversion layer, the back-side bias layer having an impurity density higher than that of the photoelectric conversion layer,
the photoelectric conversion layers of the respective pixels are depleted by a voltage applied to the back-side bias layer.
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| JP2021097214A (en) | 2019-12-18 | 2021-06-24 | ソニーセミコンダクタソリューションズ株式会社 | Light-receiving device |
| KR20210120536A (en) * | 2020-03-27 | 2021-10-07 | 에스케이하이닉스 주식회사 | Image sensing device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0897393A (en) * | 1994-09-29 | 1996-04-12 | Canon Inc | Photoelectric converter, line sensor array and semiconductor device |
| JPH10333605A (en) * | 1997-05-30 | 1998-12-18 | Casio Comput Co Ltd | Display device |
| WO2007026779A1 (en) * | 2005-08-30 | 2007-03-08 | National University Corporation Shizuoka University | Semiconductor distance measuring element and solid state imaging device |
| JP2007335673A (en) * | 2006-06-15 | 2007-12-27 | Matsushita Electric Ind Co Ltd | Solid-state imaging device and its manufacturing method |
| CN102214669A (en) * | 2010-04-08 | 2011-10-12 | 索尼公司 | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus |
| CN102270650A (en) * | 2010-06-02 | 2011-12-07 | 索尼公司 | Method for production of solid-state imaging element, solid-state imaging element, and imaging apparatus |
| WO2014021417A1 (en) * | 2012-08-03 | 2014-02-06 | 国立大学法人 静岡大学 | Semiconductor element and solid-state image pickup device |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448596B1 (en) * | 2000-08-15 | 2002-09-10 | Innotech Corporation | Solid-state imaging device |
| JP2002368205A (en) * | 2001-06-12 | 2002-12-20 | Olympus Optical Co Ltd | Input device for distance information |
| JP4426273B2 (en) * | 2003-05-22 | 2010-03-03 | イノテック株式会社 | MOS type solid-state imaging device and manufacturing method thereof |
| JP4280822B2 (en) | 2004-02-18 | 2009-06-17 | 国立大学法人静岡大学 | Optical time-of-flight distance sensor |
| JP4575030B2 (en) * | 2004-05-27 | 2010-11-04 | 三菱電機株式会社 | Elevator traffic demand prediction device and elevator control device provided with the same |
| JP5283216B2 (en) * | 2008-07-31 | 2013-09-04 | 国立大学法人静岡大学 | High-speed charge transfer photodiode, lock-in pixel and solid-state imaging device |
| JP2010056345A (en) * | 2008-08-28 | 2010-03-11 | Brookman Technology Inc | Amplification type solid state imaging device |
| US8338248B2 (en) * | 2008-12-25 | 2012-12-25 | National University Corporation Shizuoka University | Semiconductor element and solid-state imaging device |
| GB2474631A (en) | 2009-10-14 | 2011-04-27 | Optrima Nv | Photonic Mixer |
| JP5244076B2 (en) | 2009-11-24 | 2013-07-24 | 浜松ホトニクス株式会社 | Distance sensor and distance image sensor |
| JP2014150230A (en) * | 2013-02-04 | 2014-08-21 | Toshiba Corp | Solid state image pickup device manufacturing method and solid state image pickup device |
| US20160099283A1 (en) * | 2014-10-03 | 2016-04-07 | Omnivision Technologies, Inc. | Photosensor with channel region having center contact |
| JP6696647B2 (en) * | 2015-03-31 | 2020-05-20 | 国立大学法人静岡大学 | Length measuring element and solid-state imaging device |
| CN109691086B (en) * | 2016-08-24 | 2021-10-22 | 国立大学法人静冈大学 | Photoelectric conversion element |
-
2018
- 2018-12-07 CN CN201880078989.4A patent/CN111448664B/en active Active
- 2018-12-07 WO PCT/JP2018/045119 patent/WO2019112047A1/en active Application Filing
- 2018-12-07 JP JP2019558301A patent/JP7126271B2/en active Active
- 2018-12-07 US US16/770,616 patent/US11398519B2/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0897393A (en) * | 1994-09-29 | 1996-04-12 | Canon Inc | Photoelectric converter, line sensor array and semiconductor device |
| JPH10333605A (en) * | 1997-05-30 | 1998-12-18 | Casio Comput Co Ltd | Display device |
| WO2007026779A1 (en) * | 2005-08-30 | 2007-03-08 | National University Corporation Shizuoka University | Semiconductor distance measuring element and solid state imaging device |
| JP2007335673A (en) * | 2006-06-15 | 2007-12-27 | Matsushita Electric Ind Co Ltd | Solid-state imaging device and its manufacturing method |
| CN102214669A (en) * | 2010-04-08 | 2011-10-12 | 索尼公司 | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus |
| CN102270650A (en) * | 2010-06-02 | 2011-12-07 | 索尼公司 | Method for production of solid-state imaging element, solid-state imaging element, and imaging apparatus |
| WO2014021417A1 (en) * | 2012-08-03 | 2014-02-06 | 国立大学法人 静岡大学 | Semiconductor element and solid-state image pickup device |
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| Publication number | Publication date |
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| JP7126271B2 (en) | 2022-08-26 |
| WO2019112047A1 (en) | 2019-06-13 |
| CN111448664A (en) | 2020-07-24 |
| JPWO2019112047A1 (en) | 2020-12-17 |
| US11398519B2 (en) | 2022-07-26 |
| US20200312902A1 (en) | 2020-10-01 |
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