WO2019180898A1

WO2019180898A1 - Solid-state imaging element

Info

Publication number: WO2019180898A1
Application number: PCT/JP2018/011599
Authority: WO
Inventors: 大貴國京; 祐輔坂田; 三佳森
Original assignee: パナソニックＩｐマネジメント株式会社
Priority date: 2018-03-23
Filing date: 2018-03-23
Publication date: 2019-09-26
Also published as: JPWO2019180898A1

Abstract

This solid-state imaging element (100) is provided with a semiconductor substrate (10) in which light enters an upper surface; a first semiconductor (11) disposed within the semiconductor substrate (10); and a second semiconductor (12) which is disposed beneath the first semiconductor (11) within the semiconductor substrate (10). The first semiconductor (11) and a bonding region (10a), of the semiconductor substrate (10), where bonding is formed with the first semiconductor (11), constitute a photodiode (PD). The second semiconductor (12) and a photoelectric conversion region (10b), of the semiconductor substrate (10), where bonding is formed with the second semiconductor (12), constitute an avalanche photodiode (APD). The APD includes a multiplication region (15) where an electric charge is intensified by avalanche multiplication.

Description

Solid-state image sensor

The present disclosure relates to a solid-state imaging device, and particularly to a solid-state imaging device capable of detecting weak light.

In recent years, high-sensitivity photodetectors are used in various fields such as medical treatment, communication, biotechnology, chemistry, monitoring, in-vehicle use, and radiation detection. An avalanche photodiode (APD: Avalanche Photodiode) is known as one of highly sensitive photodetectors. The APD is a photodiode whose light detection sensitivity is increased by multiplying signal charges generated by photoelectric conversion using avalanche breakdown (breakdown). As a device using an APD, Patent Document 1 discloses a photodiode array having a high aperture ratio with respect to detected light. Patent Document 2 discloses a semiconductor photodetector that can detect weak light including random light.

International Publication No. 2008/004547 International Publication No. 2014/097519 Japanese Patent Laying-Open No. 2015-5752 US Pat. No. 5,965,875

The present disclosure provides a solid-state imaging device capable of detecting light having a short wavelength (for example, visible light) with high resolution and detecting light having a long wavelength (for example, near infrared light) with high sensitivity. .

A solid-state imaging device according to an aspect of the present disclosure includes a semiconductor substrate on which light is incident on an upper surface, a first semiconductor disposed in the semiconductor substrate, and a lower portion than the first semiconductor in the semiconductor substrate. The first semiconductor, and a first portion of the semiconductor substrate that joins the first semiconductor constitutes a first photoelectric conversion unit, and the second semiconductor and the semiconductor substrate. Among these, the second part joined to the second semiconductor constitutes a second photoelectric conversion unit, and the second photoelectric conversion unit includes a multiplication region where charges are multiplied by avalanche multiplication.

According to the present disclosure, a solid-state imaging device capable of detecting short wavelength light with high resolution and detecting long wavelength light with high sensitivity is realized.

FIG. 1 is a plan view of the solid-state imaging device according to the first embodiment. FIG. 2 is a cross-sectional view of the solid-state imaging device according to the first embodiment. FIG. 3 is a diagram illustrating an example of a configuration of a pixel circuit. FIG. 4 is a flowchart of the method for manufacturing the solid-state imaging device according to the first embodiment. FIG. 5 is a plan view of the solid-state imaging device according to the second embodiment. FIG. 6 is a cross-sectional view of the solid-state imaging device according to the second embodiment. FIG. 7 is a plan view of the solid-state imaging device according to the third embodiment. FIG. 8 is a first cross-sectional view of the solid-state imaging device according to the second embodiment. FIG. 9 is a first cross-sectional view of the solid-state imaging device according to the second embodiment.

(Knowledge that became the basis of this disclosure)
A solid-state imaging device that has an APD array and can detect weak light by performing signal amplification using avalanche multiplication has been proposed. A solid-state imaging device used for night vision imaging and a ToF (Time of Flight) sensor is required to have high sensitivity to near-infrared light. In a solid-state imaging device having an APD array, if the cell size of the APD is increased in order to increase the sensitivity to near infrared light, the problem is that the resolution deteriorates.

Therefore, in the following embodiment, a solid-state imaging device capable of detecting visible light with high resolution while realizing high sensitivity of near-infrared light will be described.

Hereinafter, embodiments will be described with reference to the drawings. It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements.

Each figure is a schematic diagram and is not necessarily shown strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, and the overlapping description may be abbreviate | omitted or simplified.

In the drawings used for explanation in the following embodiments, coordinate axes may be shown. The Z-axis direction in the coordinate axes is, for example, the vertical direction, the Z-axis + side is expressed as an upper side (upper), and the Z-axis-side is expressed as a lower side (lower). In other words, the Z-axis direction is a direction perpendicular to the upper surface or the lower surface of the semiconductor substrate. The X-axis direction and the Y-axis direction are directions orthogonal to each other on a plane (horizontal plane) perpendicular to the Z-axis direction. In the following embodiments, “plan view” means viewing from the Z-axis direction. Further, the present disclosure does not exclude a structure in which the P-type and the N-type are reversed in the following embodiments.

(Embodiment 1)
[Construction]
Hereinafter, the structure of the solid-state imaging device according to the first embodiment will be described. FIG. 1 is a plan view of the solid-state imaging device according to the first embodiment. FIG. 2 is a cross-sectional view of the solid-state imaging device according to the first embodiment. FIG. 2 is a cross-sectional view of the solid-state imaging device 100 taken along the line II-II in FIG. In FIG. 1, the first semiconductor 11 is actually located in the semiconductor substrate 10, but is illustrated by a solid line for clarifying the arrangement.

As shown in FIGS. 1 and 2, the solid-state imaging device 100 according to the first embodiment includes a semiconductor substrate 10, a first semiconductor 11, a second semiconductor 12, a separation region 13, and a transfer region 14. Prepare. The isolation region 13 is an example of a third semiconductor, and the transfer region 14 is an example of a fourth semiconductor.

The solid-state imaging device 100 is an image sensor including both an avalanche photodiode (APD: Avalanche Photodiode) and a photodiode (PD: Photodiode). Light enters the solid-state imaging device 100 from the upper surface side (Z-axis plus side). 1 and 2, only one APD and one PD are shown, but the solid-state imaging device 100 is arranged in a plurality of APDs arranged in an array in a plan view and in an array in a plan view. A plurality of PDs. In other words, the array shape is a matrix shape. In the solid-state imaging device 100, one pixel includes one APD and one PD.

The semiconductor substrate 10 is a substrate formed of a P-type semiconductor, and light is incident on the upper surface. The P type is an example of the first conductivity type. The semiconductor substrate 10 includes a junction region 10a, a photoelectric conversion region 10b, and a well region 10c. The bonding region 10 a is located on the upper surface side of the semiconductor substrate 10 with respect to the second semiconductor 12 and is bonded to the lower surface of the first semiconductor 11. The photoelectric conversion region 10 b is located on the lower surface side of the semiconductor substrate 10 with respect to the second semiconductor 12 and is bonded to the lower surface of the second semiconductor 12. The well region 10 c is located on the upper surface side of the semiconductor substrate 10 relative to the second semiconductor 12 and is located around the first semiconductor 11. The junction region 10 a is an example of a first portion of the semiconductor substrate 10, and the photoelectric conversion region 10 b is an example of a second portion of the semiconductor substrate 10.

The first semiconductor 11 is formed of an N-type semiconductor. The N type is an example of the second conductivity type. The first semiconductor 11 and the bonding region 10a of the semiconductor substrate 10 constitute a PD. PD is an example of a first photoelectric conversion unit. Further, the impurity concentration of the first semiconductor 11 is, for example, 10 ¹⁸ cm ⁻³ or less.

In the solid-state imaging device 100, the PD is an embedded type. Thus, if a P-type semiconductor layer having a relatively high impurity concentration is formed on the upper surface of the PD, noise and leakage current are suppressed. The PD may not be a buried type, and the PD may be exposed to the outside from the upper surface of the semiconductor substrate 10.

The second semiconductor 12 is formed of an N-type semiconductor. The second semiconductor 12 and the photoelectric conversion region 10b of the semiconductor substrate 10 constitute an APD. APD is an example of a second photoelectric conversion unit.

The light incident on the upper surface of the semiconductor substrate 10 is photoelectrically converted in the photoelectric conversion region 10b that is electrically separated from the well region 10c. As a result, electron-hole pairs that are signal charges are generated. In general, electrons of the generated signal charge flow to the upper surface side along the potential gradient, and move to the transfer region 14 via the second semiconductor 12.

The transfer region 14 is formed of an N-type semiconductor similar to the second semiconductor 12 and stores signal charges generated in the APD. The transfer region 14 has a columnar shape extending in the vertical direction, and has one end connected to the second semiconductor 12 and the other end exposed to the outside from the upper surface of the semiconductor substrate 10. The transfer region 14 is not necessarily exposed from the upper surface of the semiconductor substrate 10, and the transfer region 14 may be embedded in the semiconductor substrate 10. In this case, the impurity concentration gradient between the well region 10c and the transfer region 14 is designed such that no tunnel current is generated. At the other end of the transfer region 14, a transfer transistor TRN2 is arranged.

The APD includes a multiplication area 15. The multiplication region 15 is formed in the vicinity of the boundary between the photoelectric conversion region 10 b and the second semiconductor 12. When a reverse bias voltage equal to or higher than the breakdown voltage is applied to the semiconductor substrate 10, an avalanche multiplication phenomenon occurs in the multiplication region 15. In APD, the signal charge generated in the photoelectric conversion region 10 b is avalanche multiplied in the multiplication region 15. Thereby, a large number of signal charges can be generated before the electrons reach the transfer region 14. Therefore, the solid-state imaging device 100 can detect weak light that is normally buried in noise and cannot be detected.

In addition, if the photoelectric conversion area | region 10b is formed thickly, the probability which can photoelectrically convert the light which injected from the upper surface side will increase. If the photoelectric conversion region 10b has a thickness of 2 μm or more, it is possible to ensure sensitivity to light in a relatively long wavelength band.

The impurity concentration of the photoelectric conversion region 10b and the second semiconductor 12 is, for example, 5 × 10 ¹⁶ cm ⁻³ or more and 10 ¹⁸ cm ⁻³ or less. Thereby, avalanche multiplication can be generated. If the distance between the peak position of the impurity concentration of the photoelectric conversion region 10b and the peak position of the impurity concentration of the second semiconductor 12 is 0.5 μm or more, the offset of the impurity concentration due to impurity diffusion is suppressed. Therefore, it is possible to ensure a sufficient impurity concentration for generating avalanche multiplication.

The isolation region 13 is a region for electrically isolating the adjacent second semiconductors 12. The separation region 13 is located between the plurality of second semiconductors 12 arranged in an array and separates the plurality of second semiconductors 12 arranged in an array. The separation region 13 is located at a pixel boundary and has a lattice shape in plan view. According to the separation region, it is possible to suppress color mixture of adjacent pixels and leakage of signal charges in one pixel to other pixels.

The isolation region 13 is formed of, for example, an N-type semiconductor having an impurity concentration lower than that of the second semiconductor 12. Thereby, when a voltage is applied to the semiconductor substrate 10, a potential barrier is formed in the isolation region 13 and the adjacent second semiconductors 12 are electrically isolated. In addition, since the electric field strength between the second semiconductor 12 and the separation region 13 is lower than the electric field strength in the second semiconductor 12 and the multiplication region 15, the signal multiplication of the mixed color component generated by photoelectric conversion at the pixel boundary is performed. Can be suppressed.

When the isolation region 13 is formed of an N-type semiconductor having an impurity concentration lower than that of the second semiconductor 12, in addition to electrically isolating the plurality of second semiconductors 12, the photoelectric conversion region 10b and the well region 10c needs to be electrically separated. As the width of the isolation region 13 is increased, it is assumed that the electrical isolation between the photoelectric conversion region 10b and the well region 10c becomes more difficult, and the problem of a narrow design margin arises.

For example, when the width of the isolation region 13 is 0.5 μm or more and 1 μm or less, if the impurity concentration of the isolation region 13 is 10 ¹⁶ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, the photoelectric conversion region 10b and the well region 10c can be electrically separated. As described above, the impurity concentration of the isolation region 13 may be adjusted as appropriate according to the width of the isolation region 13. The impurity concentration of the well region 10c is, for example, not less than 10 ¹⁶ cm ^{−3 and not} more than 10 ¹⁸ cm ⁻³ .

[Arrangement of first semiconductor and second semiconductor]
The first semiconductor 11 is arranged on the upper surface side of the second semiconductor 12 in the semiconductor substrate 10. In other words, the second semiconductor 12 is disposed below the first semiconductor 11 in the semiconductor substrate 10. That is, the distance from the light incident surface (that is, the upper surface) of the semiconductor substrate 10 to the second semiconductor 12 is longer than the distance from the light incident surface of the semiconductor substrate 10 to the first semiconductor 11.

In general, due to the wavelength dependency of a semiconductor material such as silicon, the long wavelength component of light easily reaches the lower part (in other words, the deep part) in the semiconductor substrate 10, and the short wavelength component of light It is difficult to reach down.

Then, visible light having a relatively short wavelength out of the light incident on the solid-state imaging device 100 reaches the PD configured by the first semiconductor 11 and the junction region 10a, but by the second semiconductor 12 and the photoelectric conversion region 10b. It becomes difficult to reach the configured APD. On the other hand, near-infrared light having a relatively long wavelength out of light incident on the solid-state imaging device 100 easily reaches the APD. That is, according to the configuration in which the APD is positioned below the PD in the semiconductor substrate 10, the solid-state imaging device 100 can selectively avalanche-multiply light having a relatively long wavelength such as near infrared light. .

For example, the solid-state imaging device 100 can generate a luminance image by a signal output based on visible light reaching the PD. Further, the solid-state imaging device 100 can be used not only for generating a luminance image but also as a ToF (Time of Flight) sensor. The solid-state imaging device 100 can generate a distance image by using a signal obtained when pulsed near-infrared reflected light emitted from a light source reaches the APD.

Further, according to the solid-state imaging device 100, it is also possible to realize a ToF sensor with improved distance resolution. For example, the solid-state imaging device 100 detects reflected light of visible light from a visible light source by a PD for a distance to an object located at a short distance, and near red for a distance to an object located at a long distance. The reflected light of the near infrared light from the external light source is detected by APD. Thereby, a distance image with improved distance resolution can be obtained.

Note that PD and APD need to be electrically separated. The separation barrier when both PD and APD are in the reset state is, for example, at least 1 V or more. Further, the PD and the transfer area 14 need to be electrically separated. A P-type semiconductor or STI (Shallow Trench Isolation) or the like may be formed between the PD and the transfer region 14.

[Pixel circuit]
As shown in FIG. 1, a plurality of transistors constituting the pixel circuit are arranged on the upper surface of the semiconductor substrate 10. Hereinafter, the pixel circuit will be described. FIG. 3 is a diagram illustrating an example of a configuration of a pixel circuit. FIG. 3 shows the PD pixel circuit, but the APD pixel circuit has the same configuration.

The solid-state imaging device 100 includes a pixel array 102 including a plurality of pixels 101, a vertical scanning circuit 103, a horizontal scanning circuit 104, a readout circuit 105, and a buffer amplifier (amplifying circuit) 111.

The pixel 101 has a pixel circuit including a PD, a transfer transistor TRN1, a reset transistor RST1, a floating diffusion region FD1, an amplification transistor SF1, and a selection transistor SEL1. Although not shown in FIG. 3, the pixel 101 includes a pixel circuit including an APD, a transfer transistor TRN2, a reset transistor RST2, a floating diffusion region FD2, an amplification transistor SF2, and a selection transistor SEL2.

In the first to third embodiments, when “transistor” is simply described, it means a MOS transistor (MOSFET). However, the transistor constituting the pixel circuit of the solid-state imaging device is not limited to a MOS transistor, and may be a junction transistor (JFET), a bipolar transistor, or a mixture thereof.

The signal charge detected by the PD is transferred to the floating diffusion region FD1 through the transfer transistor TRN1, and a signal corresponding to the amount of signal charge detected by the pixels sequentially selected by the vertical scanning circuit 103 and the horizontal scanning circuit 104 is amplified. The data is transmitted to the reading circuit 105 via SF1. A signal obtained from the pixel 101 is output from the readout circuit 105 to the signal processing circuit (not shown) through the buffer amplifier 111, and after being subjected to signal processing such as white balance in the signal processing circuit (not shown), the display is performed. (Not shown) or a memory (not shown) to be imaged.

In the pixel circuit shown in FIG. 3, peripheral circuits (vertical scanning circuit 103, horizontal scanning circuit 104, readout circuit 105, and buffer amplifier 111) are added to the pixel array 102. However, the peripheral circuit is not necessarily included. The pixel circuit constituting the pixel 101 includes four transistors (transfer transistor TRN1, reset transistor RST1, amplification transistor SF1, selection transistor SEL1) and one floating diffusion region FD1, but the pixel circuit is However, the present invention is not limited to such a configuration, and the transistor may be configured with a larger or smaller number of transistors within a range in which the solid-state imaging device 100 can operate. The configuration and arrangement of the transistors (shown in FIG. 1) may be changed within a range in which the solid-state imaging device 100 operates.

Further, the pixel circuit may have a circuit configuration for acquiring a distance image by the ToF method. The pixel circuit may be shared by PD and APD.

[Production method]
Next, a method for manufacturing the solid-state imaging device 100 will be described. FIG. 4 is a flowchart of a method for manufacturing the solid-state imaging device 100.

The solid-state image sensor 100 is basically manufactured from the lower layer to the upper layer. First, a substrate on which the photoelectric conversion region 10b (P-type semiconductor) is formed is prepared (S11). Then, an N-type semiconductor is formed on the entire upper surface of the photoelectric conversion region 10b by ion implantation (S12). The second semiconductor 12 and the isolation region 13 are formed by performing patterning by photolithography, ion implantation using P-type impurities, and the like on the N-type semiconductor formed in step S12 (S13). Subsequently, the transfer region 14 and the first semiconductor 11 are formed by performing patterning by photolithography, ion implantation, and the like (S14). Thereafter, the well region 10c is formed (S15), and patterning and ion implantation by photolithography are performed in the well region 10c, thereby forming the source and drain of the transistor included in the pixel circuit (S16).

In addition, the formation method of a wiring layer (not shown) is as follows. For example, an insulating layer is formed on the semiconductor substrate 10 that has been subjected to the processing from step S11 to step S16, and patterning, etching, sputtering, and the like by photolithography are performed on the insulating layer, so that the insulating layer, gate Electrodes, contact plugs, and wirings are formed.

Further, at least one of the photoelectric conversion region 10b and the second semiconductor 12 may be produced by changing the impurity concentration during the formation of the semiconductor substrate 10 by epitaxial growth. With this method, crystal defects in the multiplication region 15 are less than in the multiplication region 15 when the photoelectric conversion region 10b and the second semiconductor 12 are formed by the ion implantation method, and noise can be reduced. is there.

[Effects]
The solid-state imaging device 100 includes a semiconductor substrate 10 on which light is incident on an upper surface, a first semiconductor 11 disposed in the semiconductor substrate 10, and a second semiconductor disposed below the first semiconductor 11 in the semiconductor substrate 10. 12. The first semiconductor 11 and the junction region 10 a that joins the first semiconductor 11 in the semiconductor substrate 10 constitute a PD. The junction region 10a is an example of a first portion, and the PD is an example of a first photoelectric conversion unit. The second semiconductor 12 and the photoelectric conversion region 10b bonded to the second semiconductor 12 in the semiconductor substrate 10 constitute an APD. The photoelectric conversion region 10b is an example of a second part, and the APD is an example of a second photoelectric conversion unit. The APD includes a multiplication region 15 where charges are multiplied by avalanche multiplication.

In such a solid-state imaging device 100, an APD is disposed on the lower surface side in the semiconductor substrate 10 in which short-wavelength light is difficult to reach and long-wavelength light is likely to reach. For this reason, if APD is used for detection of light having a long wavelength, the solid-state imaging device 100 can detect light having a long wavelength with relatively high sensitivity.

In the solid-state imaging device 100, the positions of the PD and APD are different in the vertical direction. Therefore, in the solid-state imaging device 100, the number of PDs can be increased, and light with a short wavelength can be detected with high resolution by increasing the number of PDs.

As described above, the solid-state imaging device 100 can detect light having a short wavelength with high resolution and can detect light having a long wavelength with high sensitivity.

The solid-state imaging device 100 includes a plurality of first semiconductors 11 arranged in an array in the semiconductor substrate 10 and a plurality of first semiconductors 11 arranged in an array below the plurality of first semiconductors 11 in the semiconductor substrate 10. A second semiconductor 12.

Thus, the solid-state imaging device 100 can output a luminance image or a distance image with a plurality of PDs, and can output a luminance image or a distance image with a plurality of APDs.

The solid-state imaging device 100 is further a transfer region 14 where charges generated in the APD are accumulated, one end of which is connected to the second semiconductor 12 and the other end from the upper surface of the semiconductor substrate 10. A transfer region 14 exposed to the outside and a transfer transistor TRN2 disposed at the other end of the transfer region 14 are provided. The transfer area is an example of a fourth semiconductor.

As described above, the solid-state imaging device 100 can transfer charges generated in the APD.

(Embodiment 2)
[Construction]
Hereinafter, the structure of the solid-state imaging device according to the second embodiment will be described. FIG. 5 is a plan view of the solid-state imaging device according to the second embodiment. FIG. 6 is a cross-sectional view of the solid-state imaging device according to the second embodiment. 6 is a cross-sectional view of the solid-state imaging device 200 taken along the line VI-VI in FIG. In FIG. 5, the first semiconductor 21 is actually located in the semiconductor substrate 20, but is shown by a solid line in order to clarify the arrangement.

As shown in FIGS. 5 and 6, the solid-state imaging device 200 according to the second embodiment includes a semiconductor substrate 20, a first semiconductor 21, a second semiconductor 22, a separation region 23, and a transfer region 24. Prepare. The isolation region 23 is an example of a third semiconductor, and the transfer region 24 is an example of a fourth semiconductor. The semiconductor substrate 20 includes a plurality of junction regions 20a, a photoelectric conversion region 20b, and a well region 20c. Hereinafter, in the second embodiment, description will be made centering on differences between the solid-state imaging device 200 and the solid-state imaging device 100, and description of the matters already described will be omitted or simplified.

In the solid-state imaging device 200, one pixel includes one APD and two PDs. That is, the solid-state imaging device 200 includes a plurality of PDs for one APD. Therefore, in the solid-state imaging device 200, the total number of the plurality of APDs (that is, the plurality of first semiconductors 21) is larger than the total number of the plurality of PDs (that is, the plurality of second semiconductors 22). Further, in plan view, one second semiconductor 22 overlaps the plurality of first semiconductors 21. Note that the number of PDs included in one pixel, the arrangement of PDs in one pixel, the shape of the PD, and the like are not particularly limited.

The plurality of PDs are arranged in the well region 20c of the semiconductor substrate 20 and are electrically separated. Also in the solid-state imaging device 200, the second semiconductor 22 is disposed below the first semiconductor 21 in the semiconductor substrate 20.

For example, when the photoelectric conversion region 20b is formed of silicon, the PD is used for detection of visible light, and the APD is used for detection of near-infrared light, it is possible to increase the resolution of a luminance image obtained by the PD. it can. In addition, silicon has a low absorption rate of near infrared light. Therefore, a configuration in which near-infrared light is avalanche multiplied in the APD multiplication region 25 is useful.

In the solid-state imaging device 200, the second semiconductor 22 is larger than the first semiconductor 21 in plan view. In the solid-state imaging device 200, all of the first semiconductors 21 overlap with the second semiconductor in a plan view, and the light receiving area of the APD is relatively larger than the light receiving area of the PD. Therefore, improvement in sensitivity to near infrared light is expected.

Further, since the photoelectric conversion region 20b is located on the side opposite to the upper surface (light incident surface) of the semiconductor substrate 20, it can be made relatively thick. Thereby, APD can detect near-infrared light by improving quantum efficiency.

Incidentally, as shown in FIG. 5, a plurality of transistors constituting the pixel circuit are arranged on the upper surface of the semiconductor substrate 20. The pixel circuit for PD includes a transfer transistor TRN1, a reset transistor RST1, a floating diffusion region FD1, an amplification transistor SF1, and a selection transistor SEL1. The APD pixel circuit includes a transfer transistor TRN2, a reset transistor RST2, a floating diffusion region FD2, an amplification transistor SF2, and a selection transistor SEL2.

In the solid-state imaging device 200, the pixel circuit for PD and the pixel circuit for APD are independent. On the other hand, the pixel circuits of the two PDs are made common, thereby reducing the mounting area of the PD pixel circuit. The pixel circuit can be shared even when there are three or more PDs. The PD pixel circuit and the APD pixel circuit may be shared.

[Effects]
In the solid-state imaging device 200, the second semiconductor 22 is larger than the first semiconductor 21 in plan view.

Thus, since the light receiving area of the APD configured by the second semiconductor 22 is large in the solid-state imaging device 200, the sensitivity of near-infrared light can be increased.

In the solid-state imaging device 200, the total number of the plurality of first semiconductors 21 is larger than the total number of the plurality of second semiconductors 22.

As described above, in the solid-state imaging device 200, since the number of PDs configured by the first semiconductor 21 is large, an image (luminance image or distance image) based on light detected by the PD is increased in resolution.

In the solid-state imaging device 200, one second semiconductor 22 overlaps the plurality of first semiconductors 21 in plan view.

Thereby, it is possible to reduce the size of the solid-state imaging device 200 by concentrating the plurality of first semiconductors 21.

(Embodiment 3)
[Construction]
Hereinafter, the structure of the solid-state imaging device according to the third embodiment will be described. FIG. 7 is a plan view of the solid-state imaging device according to the third embodiment. 8 and 9 are cross-sectional views of the solid-state imaging device according to the second embodiment. FIG. 8 is a cross-sectional view of the solid-state imaging device 300 taken along the line VIII-VIII in FIG. FIG. 9 is a cross-sectional view of the solid-state imaging device 300 taken along the line IX-IX in FIG. In FIG. 7, the first semiconductor 31 is actually located in the semiconductor substrate 30, but is illustrated by a solid line for clarity of arrangement.

As shown in FIGS. 7 to 9, the solid-state imaging device 300 according to the third embodiment includes a semiconductor substrate 30, a plurality of first semiconductors 31, a plurality of second semiconductors 32, a separation region 33, and a transfer. Region 34. The isolation region 33 is an example of a third semiconductor, and the transfer region 34 is an example of a fourth semiconductor. The semiconductor substrate 30 includes a plurality of junction regions 30a, a photoelectric conversion region 30b, and a well region 30c. Hereinafter, in the third embodiment, description will be made centering on differences between the solid-state imaging device 300 and the solid-state imaging device 100 and the solid-state imaging device 200, and description of the matters already described will be omitted or simplified.

In the solid-state imaging device 300, one pixel includes one APD and four PDs. That is, the solid-state imaging device 200 includes four PDs for one APD. Note that the number of PDs included in one pixel, the arrangement of PDs in one pixel, the shape of the PD, and the like are not particularly limited.

¡A Bayer color filter is applied to the four PDs. In the solid-state imaging device 300, an APD for detecting near-infrared light with high sensitivity is added while corresponding to such an existing Bayer color filter.

The PD (that is, the first semiconductor 31) is also disposed above the isolation region 33. When an image is output by the signal charge multiplied by the avalanche in the APD multiplication region 35, a negative bias voltage (also called a breakdown voltage) is applied to the lower surface side of the photoelectric conversion region 30b. At this time, it is necessary to electrically separate a plurality of APDs (that is, a plurality of second semiconductors 32) so that outputs for each pixel are not mixed. In addition, in order to stabilize the potential of the well region 30c where the transistors constituting the pixel circuit are arranged, it is necessary to electrically isolate the well region 30c and the photoelectric conversion region 30b.

In order to achieve both electrical isolation of a plurality of APDs and electrical isolation between the well region 30c and the photoelectric conversion region 30b, the isolation region 33 is reset to form a constant potential barrier between the pixels. It is necessary to maintain a depleted state in which the potential is lower than the APD in the state and is higher than the well region 30c. However, the range of the impurity concentration of the isolation region 33 that satisfies this condition is limited, and it is difficult to manufacture the solid-state imaging device 300 including the isolation region 33 that satisfies this condition.

If the PD is arranged on the separation region 33, even if a negative bias voltage is applied to the lower surface side of the photoelectric conversion region 30b, a PD to which a positive bias voltage is applied in the reset state is arranged above the separation region 33. Is done. For this reason, the electrical isolation | separation capability (namely, insulation capability) between the well area | region 30c and the photoelectric converting area | region 30b improves. In particular, a region P (shown in FIG. 7) adjacent to the corner of the APD in plan view in the separation region 33 is formed to have a relatively wide width so that an electrical connection between the well region 30c and the photoelectric conversion region 30b is achieved. There is a high concern that the separation capacity will decrease. Therefore, it is useful to arrange the PD above the region P.

Further, as shown in FIG. 9, in the solid-state imaging device 300, there is a difference in impurity concentration between the well region 30c and the junction region 30a, which are P-type semiconductors. Specifically, the impurity concentration of the junction region 30a is lower than the impurity concentration of the well region 30c. Thereby, since the depletion layer extends on the lower surface side of the PD, the sensitivity of the PD can be improved.

Further, in the solid-state image sensor 300, the impurity concentrations of the second semiconductor 32, the transfer region 34, and the first semiconductor 31 that are N-type semiconductors are different. Specifically, the impurity concentration of the second semiconductor 32 and the impurity concentration of the transfer region 34 are higher than the impurity concentration of the first semiconductor 31. Thus, when avalanche multiplication is performed by driving the APD, the negative bias voltage applied to the photoelectric conversion region 30b can be reduced. If the negative bias voltage applied to the photoelectric conversion region 30b is reduced, the risk of conduction between the photoelectric conversion region 30b and the well region 30c (in other words, punch-through) can be reduced.

Incidentally, as shown in FIG. 7, a plurality of transistors constituting the pixel circuit are arranged on the upper surface of the semiconductor substrate 30. The pixel circuit for PD includes a transfer transistor TRN1, a reset transistor RST1, a floating diffusion region FD1, an amplification transistor SF1, and a selection transistor SEL1. The APD pixel circuit includes a transfer transistor TRN2, a reset transistor RST2, a floating diffusion region FD2, an amplification transistor SF2, and a selection transistor SEL2.

In the solid-state imaging device 300, the pixel circuit for PD and the pixel circuit for APD are independent. The pixel circuits of the two PDs are shared, and one pixel has two sets of pixel circuits corresponding to the four PDs. Thereby, the mounting area of the pixel circuit for PD is reduced. The pixel circuit can be shared even when there are three or more PDs. Further, the pixel circuit for PD and the pixel circuit for APD may be shared.

[Effects]
The solid-state imaging device 300 includes a separation region 33 that is located between the plurality of second semiconductors 32 in the semiconductor substrate 30 and separates the plurality of second semiconductors 32. The isolation region 33 is an example of a third semiconductor. In plan view, the separation region 33 overlaps at least one of the plurality of first semiconductors 31.

Thereby, electrical conduction between the photoelectric conversion region 30b and the well region 30c is suppressed.

Further, the solid-state imaging device 300 includes four first semiconductors 31 with respect to one second semiconductor 32, and the four second semiconductors 32 form a 2 × 2 array.

As described above, in the solid-state imaging device 300, the APD is added while maintaining the PD Bayer arrangement. That is, the Bayer arrangement can be applied to the color filter of the second semiconductor 32 corresponding to the detection of visible light.

In the solid-state imaging device 300, the semiconductor substrate 30 is formed of a first conductivity type (for example, P-type) semiconductor, and the first semiconductor 31, the second semiconductor 32, and the transfer region 34 are the first conductivity type. It is formed of a second conductivity type (for example, N type) semiconductor different from the type. The impurity concentration of the second semiconductor 32 and the impurity concentration of the transfer region 34 are higher than the impurity concentration of the first semiconductor 31.

Thus, when avalanche multiplication is performed by driving the APD, the negative bias voltage applied to the photoelectric conversion region 30b can be reduced. If the negative bias voltage applied to the photoelectric conversion region 30b is reduced, conduction between the photoelectric conversion region 30b and the well region 30c can be suppressed.

In the solid-state imaging device 300, the semiconductor substrate 30 includes a well region 30c located around the first semiconductor 31, and the impurity concentration of the junction region 30a of the semiconductor substrate 30 is lower than the impurity concentration of the well region 30c. .

Thereby, since the depletion layer extends on the lower surface side of the PD, the sensitivity of the PD can be improved.

(Other embodiments)
The solid-state imaging device according to the embodiment has been described above, but the present disclosure is not limited to the above-described embodiment.

For example, in the above embodiment, the first photoelectric conversion unit does not include the multiplication region, but may include the multiplication region. That is, the first photoelectric conversion unit may be an APD instead of a PD.

In addition, all the numbers used in the description in the above-described embodiment are examples for specifically explaining the present disclosure, and the present disclosure is not limited to the illustrated numbers.

Further, the circuit configuration described in the above embodiment is an example, and the present disclosure is not limited to the above circuit configuration. That is, similar to the circuit configuration described above, a circuit that can realize the characteristic function of the present disclosure is also included in the present disclosure. For example, a device in which an element such as a switching element (transistor), a resistance element, or a capacitor element is connected in series or in parallel to a certain element within a range in which a function similar to the circuit configuration described above can be realized is also disclosed in the present disclosure. included.

In the above embodiment, the main materials constituting each layer of the stacked structure of the solid-state image sensor are illustrated, but each layer of the stacked structure of the solid-state image sensor has the same structure as the stacked structure of the above embodiment. Other materials may be included as long as these functions can be realized. In the drawings, the corners and sides of each component are linearly described, but the present disclosure also includes those in which the corners and sides are rounded due to manufacturing reasons.

In addition, the embodiment can be realized by variously conceiving various modifications to those embodiments, or by arbitrarily combining the components and functions in the embodiments without departing from the gist of the present disclosure. This form is also included in the present disclosure. For example, this indication may be realized as a manufacturing method of a solid-state image sensing device.

The solid-state imaging device of the present disclosure can be used for a camera, a ToF sensor, and the like.

10, 20, 30

Semiconductor substrate

10a, 20a,

30a Junction region

10b, 20b, 30b

Photoelectric conversion region

10c, 20c,

30c Well region

11, 21, 31

First semiconductor

12, 22, 32

Second semiconductor

13, 23, 33 Isolation region (third semiconductor)
14, 24, 34 Transfer area (fourth semiconductor)
15, 25, 35

Multiplier region

100, 200, 300 Solid-state imaging device 101 Pixel 102 Pixel array 103 Vertical scanning circuit 104 Horizontal scanning circuit 105 Read circuit 111 Buffer amplifier FD1, FD2 Floating diffusion region RST1, RST2 Reset transistor SEL1, SEL2 selection Transistor SF1, SF2 Amplifying transistor TRN1, TRN2 Transfer transistor

Claims

A semiconductor substrate on which light is incident on the upper surface;
A first semiconductor disposed in the semiconductor substrate;
A second semiconductor disposed below the first semiconductor in the semiconductor substrate,
The first portion of the first semiconductor and the semiconductor substrate bonded to the first semiconductor constitutes a first photoelectric conversion unit,
The second semiconductor and the second portion of the semiconductor substrate that is bonded to the second semiconductor constitutes a second photoelectric conversion unit,
The second photoelectric conversion unit includes a multiplication region where charges are multiplied by avalanche multiplication.
The solid-state imaging device according to claim 1, wherein the second semiconductor is larger than the first semiconductor in a plan view.
The solid-state imaging device is
A plurality of the first semiconductors arranged in an array in the semiconductor substrate, and a plurality of the second semiconductors arranged in an array below the plurality of first semiconductors in the semiconductor substrate. The solid-state imaging device according to 1 or 2.
The solid-state imaging device according to claim 3, wherein a total number of the plurality of first semiconductors is larger than a total number of the plurality of second semiconductors.
5. The solid-state imaging device according to claim 3, wherein one second semiconductor overlaps the plurality of first semiconductors in plan view.
And a third semiconductor positioned between the plurality of second semiconductors in the semiconductor substrate and separating the plurality of second semiconductors,
The solid-state imaging device according to any one of claims 3 to 5, wherein the third semiconductor overlaps at least one of the plurality of first semiconductors in plan view.
The solid-state imaging device includes four first semiconductors with respect to one second semiconductor, and the four second semiconductors form a 2 × 2 array. The solid-state image sensor described in 1.
further,
A fourth semiconductor in which charges generated in the second photoelectric conversion unit are accumulated, wherein one end is connected to the second semiconductor and the other end is exposed to the outside from the upper surface of the semiconductor substrate; Four semiconductors,
The solid-state imaging device according to any one of claims 1 to 7, further comprising: a transistor disposed at the other end of the fourth semiconductor.
The semiconductor substrate is formed of a first conductivity type semiconductor,
The first semiconductor, the second semiconductor, and the fourth semiconductor are formed of a second conductivity type semiconductor different from the first conductivity type,
The solid-state imaging device according to claim 8, wherein the impurity concentration of the second semiconductor and the impurity concentration of the fourth semiconductor are higher than the impurity concentration of the first semiconductor.
The semiconductor substrate includes a well region located around the first semiconductor;
The solid-state imaging device according to any one of claims 1 to 9, wherein an impurity concentration of the first portion of the semiconductor substrate is lower than an impurity concentration of the well region.