JPWO2019180898A1 - Solid-state image sensor - Google Patents

Abstract

The solid-state image sensor (100) includes a semiconductor substrate (10) in which light is incident on the upper surface, a first semiconductor (11) arranged in the semiconductor substrate (10), and a first semiconductor (10) in the semiconductor substrate (10). It includes a second semiconductor (12) arranged below 11). The bonding region (10a) bonded to the first semiconductor (11) of the first semiconductor (11) and the semiconductor substrate (10) constitutes a PD. The photoelectric conversion region (10b) bonded to the second semiconductor (12) of the second semiconductor (12) and the semiconductor substrate (10) constitutes the APD. The APD includes a multiplication region (15) in which the charge is multiplied by the avalanche multiplication.

Description

The present disclosure relates to a solid-state image sensor, and particularly to a solid-state image sensor capable of detecting weak light.

In recent years, high-sensitivity photodetectors have been used in a wide range of fields such as medical care, telecommunications, biotechnology, chemistry, surveillance, in-vehicle use, and radiation detection. An avalanche photodiode (APD) is known as one of the highly sensitive photodetectors. APD is a photodiode whose light detection sensitivity is enhanced by multiplying the signal charge generated by photoelectric conversion by using avalanche breakdown. As a device in which APD is used, Patent Document 1 discloses a photodiode array having a high aperture ratio with respect to the detected light. Further, Patent Document 2 discloses a semiconductor photodetector capable of detecting weak light including random light.

International Publication No. 2008/004547 International Publication No. 2014/077519 JP 2015-5752 U.S. Pat. No. 5,965,875

The present disclosure provides a solid-state image sensor capable of detecting short-wavelength light (for example, visible light) with high resolution and long-wavelength light (for example, near-infrared light) with high sensitivity. ..

The solid-state imaging device according to one aspect of the present disclosure is arranged below the semiconductor substrate in which light is incident on the upper surface, the first semiconductor arranged in the semiconductor substrate, and the first semiconductor in the semiconductor substrate. The first semiconductor and the first portion of the semiconductor substrate bonded to the first semiconductor constitute a first photoelectric conversion unit, and the second semiconductor and the semiconductor substrate are provided. The second portion bonded to the second semiconductor constitutes a second photoelectric conversion unit, and the second photoelectric conversion unit includes a multiplication region in which the charge is multiplied by the avalanche multiplication.

According to the present disclosure, a solid-state image sensor capable of detecting short-wavelength light with high resolution and long-wavelength light with high sensitivity is realized.

FIG. 1 is a plan view of the solid-state image sensor according to the first embodiment. FIG. 2 is a cross-sectional view of the solid-state image sensor according to the first embodiment. FIG. 3 is a diagram showing an example of the configuration of the pixel circuit. FIG. 4 is a flowchart of a method for manufacturing a solid-state image sensor according to the first embodiment. FIG. 5 is a plan view of the solid-state image sensor according to the second embodiment. FIG. 6 is a cross-sectional view of the solid-state image sensor according to the second embodiment. FIG. 7 is a plan view of the solid-state image sensor according to the third embodiment. FIG. 8 is a first cross-sectional view of the solid-state image sensor according to the second embodiment. FIG. 9 is a first cross-sectional view of the solid-state image sensor according to the second embodiment.

(Knowledge on which this disclosure was based)
A solid-state image sensor having an APD array and capable of detecting weak light by performing signal amplification using avalanche multiplication has been proposed. The solid-state image sensor used for night-vision imaging and ToF (Time of Flight) sensors is required to have high sensitivity to near-infrared light. In a solid-state image sensor having an APD array, there is a problem that the resolution deteriorates when the cell size of the APD is increased in order to increase the sensitivity to near-infrared light.

Therefore, in the following embodiments, a solid-state image sensor capable of detecting visible light with high resolution while achieving high sensitivity of near-infrared light will be described.

Hereinafter, embodiments will be described with reference to the drawings. It should be noted that all of the embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, etc. shown in the following embodiments are examples, and are not intended to limit the present disclosure. Further, among the components in the following embodiments, the components not described in the independent claims indicating the highest level concept are described as arbitrary components.

It should be noted that each figure is a schematic view and is not necessarily exactly shown. Further, in each figure, substantially the same configuration is designated by the same reference numerals, and duplicate description may be omitted or simplified.

In addition, coordinate axes may be shown in the drawings used for explanation in the following embodiments. The Z-axis direction in the coordinate axes is, for example, the vertical direction, the Z-axis + side is expressed as the upper side (upper side), and the Z-axis-side is expressed as the lower side (lower side). In other words, the Z-axis direction is a direction perpendicular to the upper surface or the lower surface of the semiconductor substrate. Further, the X-axis direction and the Y-axis direction are directions orthogonal to each other on a plane (horizontal plane) perpendicular to the Z-axis direction. In the following embodiments, "planar view" means viewing from the Z-axis direction. Further, the present disclosure does not exclude the structure in which the P-type and the N-type are reversed in the following embodiments.

(Embodiment 1)
[Construction]
Hereinafter, the structure of the solid-state image sensor according to the first embodiment will be described. FIG. 1 is a plan view of the solid-state image sensor according to the first embodiment. FIG. 2 is a cross-sectional view of the solid-state image sensor according to the first embodiment. FIG. 2 is a cross-sectional view of the solid-state imaging device 100 cut along the line II-II of FIG. In FIG. 1, the first semiconductor 11 is actually located in the semiconductor substrate 10, but is shown by a solid line for clarifying the arrangement.

As shown in FIGS. 1 and 2, the solid-state image sensor 100 according to the first embodiment includes a semiconductor substrate 10, a first semiconductor 11, a second semiconductor 12, a separation region 13, and a transfer region 14. Be prepared. The separation region 13 is an example of the third semiconductor, and the transfer region 14 is an example of the fourth semiconductor.

The solid-state image sensor 100 is an image sensor including both an avalanche photodiode (APD) and a photodiode (PD). Light is incident on the solid-state image sensor 100 from the upper surface side (Z-axis plus side). Although only one APD and one PD are shown in FIGS. 1 and 2, the solid-state image sensor 100 is arranged in an array in a plan view with a plurality of APDs arranged in an array in a plan view. It has a plurality of PDs. The array shape is, in other words, a matrix shape. In the solid-state image sensor 100, one pixel includes one APD and one PD.

The semiconductor substrate 10 is a substrate formed of a P-type semiconductor, and light is incident on the upper surface thereof. The P type is an example of the first conductive type. The semiconductor substrate 10 includes a bonding region 10a, a photoelectric conversion region 10b, and a well region 10c. The bonding region 10a is located on the upper surface side of the semiconductor substrate 10 with respect to the second semiconductor 12, and is bonded to the lower surface of the first semiconductor 11. The photoelectric conversion region 10b is located on the lower surface side of the semiconductor substrate 10 with respect to the second semiconductor 12, and is bonded to the lower surface of the second semiconductor 12. The well region 10c is located on the upper surface side of the semiconductor substrate 10 with respect to the second semiconductor 12, and is located around the first semiconductor 11. The bonding region 10a is an example of the first portion of the semiconductor substrate 10, and the photoelectric conversion region 10b is an example of the second portion of the semiconductor substrate 10.

The first semiconductor 11 is formed of an N-type semiconductor. The N type is an example of the second conductive type. The first semiconductor 11 and the bonding region 10a of the semiconductor substrate 10 constitute a PD. PD is an example of the first photoelectric conversion unit. The impurity concentration of the first semiconductor 11 is, for example, 10 ¹⁸ cm ^-3 or less.

In the solid-state image sensor 100, the PD is an embedded type. If a P-type semiconductor layer having a relatively high impurity concentration is formed on the upper surface of the PD in this way, noise and leakage current are suppressed. The PD does not have to be an embedded type, and the PD may be exposed to the outside from the upper surface of the semiconductor substrate 10.

The second semiconductor 12 is formed of an N-type semiconductor. The second semiconductor 12 and the photoelectric conversion region 10b of the semiconductor substrate 10 constitute an APD. APD is an example of a second photoelectric conversion unit.

The light incident on the upper surface of the semiconductor substrate 10 is photoelectrically converted in the photoelectric conversion region 10b electrically separated from the well region 10c. As a result, electron-hole pairs, which are signal charges, are generated. Generally, the electrons of the generated signal charge flow to the upper surface side along the potential gradient and move to the transfer region 14 via the second semiconductor 12.

The transfer region 14 is formed by an N-type semiconductor similar to the second semiconductor 12, and the signal charge generated in the APD is accumulated. The transfer region 14 is a columnar shape extending in the vertical direction, one end of which is connected to the second semiconductor 12, and the other end of which is exposed to the outside from the upper surface of the semiconductor substrate 10. The transfer region 14 does not necessarily have to be exposed from the upper surface of the semiconductor substrate 10, and the transfer region 14 may be embedded in the semiconductor substrate 10. In this case, the impurity concentration gradient between the well region 10c and the transfer region 14 is designed so that no tunnel current is generated. A transfer transistor TRN2 is arranged at the other end of the transfer region 14.

The APD includes a multiplying region 15. The multiplying region 15 is formed near the boundary between the photoelectric conversion region 10b and the second semiconductor 12. When a reverse bias voltage equal to or higher than the breakdown voltage is applied to the semiconductor substrate 10, an avalanche multiplication phenomenon occurs in the multiplication region 15. In APD, the signal charge generated in the photoelectric conversion region 10b is avalanche multiplied in the multiplication region 15. This allows a large number of signal charges to be generated before the electrons reach the transfer region 14. Therefore, the solid-state image sensor 100 can detect weak light that is normally buried in noise and cannot be detected.

If the photoelectric conversion region 10b is formed thick, the probability that the light incident from the upper surface side can be photoelectrically converted increases. When the photoelectric conversion region 10b has a thickness of 2 μm or more, sensitivity to light in a relatively long wavelength band can be ensured.

The impurity concentrations of the photoelectric conversion region 10b and the second semiconductor 12 are, for example, 5 × 10 ¹⁶ cm ^-3 or more and 10 ¹⁸ cm ^-3 or less. This makes it possible to generate avalanche multiplication. When the distance between the peak position of the impurity concentration in the photoelectric conversion region 10b and the peak position of the impurity concentration of the second semiconductor 12 is 0.5 μm or more, the cancellation of the impurity concentration due to the diffusion of impurities is suppressed. Therefore, it is possible to secure a sufficient impurity concentration to generate an avalanche multiplication.

The separation region 13 is a region for electrically separating adjacent second semiconductors 12. The separation region 13 is located between the plurality of second semiconductors 12 arranged in an array, and separates the plurality of second semiconductors 12 arranged in an array. The separation region 13 is located at the boundary of pixels and has a grid pattern in a plan view. According to the separation region, it is possible to prevent color mixing of adjacent pixels and leakage of signal charges in one pixel to other pixels.

The separation region 13 is formed of, for example, an N-type semiconductor having a lower impurity concentration than the second semiconductor 12. As a result, when a voltage is applied to the semiconductor substrate 10, a potential barrier is formed in the separation region 13 and the adjacent second semiconductors 12 are electrically separated. Further, since the electric field strength between the second semiconductor 12 and the separation region 13 is lower than the electric field strength in the second semiconductor 12 and the multiplication region 15, the signal multiplication of the color mixing component generated by the photoelectric conversion at the pixel boundary is performed. Can be suppressed.

When the separation region 13 is formed of an N-type semiconductor having a lower impurity concentration than the second semiconductor 12, in addition to electrically separating the plurality of second semiconductors 12, the photoelectric conversion region 10b and the well region are formed. It is necessary to electrically separate the 10c. It is assumed that the wider the width of the separation region 13, the more difficult the electrical separation between the photoelectric conversion region 10b and the well region 10c becomes, and the problem that the design margin becomes narrower.

For example, when the width of the separation region 13 is 0.5 μm or more and 1 μm or less, and the impurity concentration of the separation region 13 is 10 ¹⁶ cm ^-3 or more and 5 × 10 ¹⁷ cm ^-3 or less, the photoelectric conversion region 10b and the well region It can be electrically separated from 10c. As described above, the impurity concentration of the separation region 13 may be appropriately adjusted according to the width of the separation region 13. The impurity concentration in the well region 10c is, for example, 10 ¹⁶ cm ^-3 or more and 10 ¹⁸ cm ^-3 or less.

[Arrangement of first semiconductor and second semiconductor]
The first semiconductor 11 is arranged on the upper surface side of the second semiconductor 12 in the semiconductor substrate 10. In other words, the second semiconductor 12 is arranged below the first semiconductor 11 in the semiconductor substrate 10. That is, the distance from the light incident surface (that is, the upper surface) of the semiconductor substrate 10 to the second semiconductor 12 is longer than the distance from the light incident surface of the semiconductor substrate 10 to the first semiconductor 11.

In general, due to the wavelength dependence of a semiconductor material such as silicon, the long wavelength component of light easily reaches the lower part (in other words, the deep part) in the semiconductor substrate 10, and the short wavelength component of light is in the semiconductor substrate 10. It is difficult to reach the bottom.

Then, the visible light having a relatively short wavelength among the light incident on the solid-state image sensor 100 reaches the PD composed of the first semiconductor 11 and the junction region 10a, but is reached by the second semiconductor 12 and the photoelectric conversion region 10b. It becomes difficult to reach the configured APD. On the other hand, of the light incident on the solid-state image sensor 100, the near-infrared light having a relatively long wavelength easily reaches the APD. That is, according to the configuration in which the APD is located below the PD in the semiconductor substrate 10, the solid-state image sensor 100 can selectively multiply avalanche light having a relatively long wavelength such as near-infrared light. ..

For example, the solid-state image sensor 100 can generate a luminance image from a signal output based on visible light that has reached the PD. Further, the solid-state image sensor 100 can be used not only for generating a luminance image but also as a ToF (Time of Flight) sensor. The solid-state image sensor 100 can generate a distance image from a signal obtained by the reflected light of pulsed near-infrared light emitted from a light source reaching the APD.

Further, according to the solid-state image sensor 100, it is possible to realize a ToF sensor having an enhanced distance resolution. For example, the solid-state imaging device 100 detects the reflected light of visible light from a visible light source by PD for the distance to an object located at a short distance, and near-red for the distance to an object located at a long distance. The reflected light of near-infrared light from an external light source is detected by APD. As a result, it is possible to obtain a distance image with improved distance resolution.

It should be noted that PD and APD need to be electrically separated. The separation barrier when both PD and APD are in the reset state is, for example, at least 1 V or more. Further, the PD and the transfer area 14 need to be electrically separated. A P-type semiconductor, STI (Shallow Trench Isolation), or the like may be formed between the PD and the transfer region 14.

[Pixel circuit]
As shown in FIG. 1, a plurality of transistors constituting a pixel circuit are arranged on the upper surface of the semiconductor substrate 10. Hereinafter, the pixel circuit will be described. FIG. 3 is a diagram showing an example of the configuration of the pixel circuit. Although FIG. 3 shows a PD pixel circuit, the APD pixel circuit has the same configuration.

The solid-state image sensor 100 includes a pixel array 102 including a plurality of pixels 101, a vertical scanning circuit 103, a horizontal scanning circuit 104, a reading circuit 105, and a buffer amplifier (amplifier circuit) 111.

The pixel 101 has a pixel circuit including a PD, a transfer transistor TRN1, a reset transistor RST1, a floating diffusion region FD1, an amplification transistor SF1, and a selection transistor SEL1. Although not shown in FIG. 3, the pixel 101 has a pixel circuit including an APD, a transfer transistor TRN2, a reset transistor RST2, a floating diffusion region FD2, an amplification transistor SF2, and a selection transistor SEL2.

In the first to third embodiments, the term "transistor" simply means a MOS transistor (MOSFET). However, the transistor constituting the pixel circuit of the solid-state image sensor is not limited to the MOS type transistor, and may be a junction type transistor (JFET), a bipolar transistor, or a mixture thereof.

The signal charge detected by the PD is transferred to the floating diffusion region FD1 through the transfer transistor TRN1, and the signal corresponding to the amount of the signal charge detected in the pixels sequentially selected by the vertical scanning circuit 103 and the horizontal scanning circuit 104 is an amplification transistor. It is transmitted to the read circuit 105 via SF1. The signal obtained by the pixel 101 is output from the read circuit 105 to the signal processing circuit (not shown) via the buffer amplifier 111, and is displayed after being subjected to signal processing such as white balance by the signal processing circuit (not shown). It can be transferred to (not shown) or memory (not shown) and imaged.

In the pixel circuit shown in FIG. 3, peripheral circuits (vertical scanning circuit 103, horizontal scanning circuit 104, readout circuit 105, buffer amplifier 111) are added to the pixel array 102, but the solid-state image sensor 100 has. , Peripheral circuits may not necessarily be included. Further, the pixel circuit constituting the pixel 101 is composed of four transistors (transfer transistor TRN1, reset transistor RST1, amplification transistor SF1, selection transistor SEL1) and one stray diffusion region FD1, but the pixel circuit is composed of four transistors. The solid-state imaging device 100 may be composed of a larger number or a smaller number of transistors within a range in which the solid-state imaging device 100 can operate. The configuration and arrangement of the transistors (shown in FIG. 1) may be changed within the range in which the solid-state image sensor 100 operates.

Further, the pixel circuit may have a circuit configuration for acquiring a distance image by the ToF method. Further, the pixel circuit may be shared by PD and APD.

[Production method]
Next, a method of manufacturing the solid-state image sensor 100 will be described. FIG. 4 is a flowchart of a method for manufacturing the solid-state image sensor 100.

The solid-state image sensor 100 is basically manufactured from the lower layer to the upper layer. First, a substrate on which the photoelectric conversion region 10b (P-type semiconductor) is formed is prepared (S11). Then, an N-type semiconductor is formed on the entire upper surface of the photoelectric conversion region 10b by the ion implantation method (S12). The second semiconductor 12 and the separation region 13 are formed by performing patterning by photolithography, ion implantation using P-type impurities, and the like on the N-type semiconductor formed in step S12 (S13). Subsequently, the transfer region 14 and the first semiconductor 11 are formed by performing patterning by photolithography, ion implantation, and the like (S14). After that, the well region 10c is formed (S15), and the source and drain of the transistor included in the pixel circuit are formed in the well region 10c by performing patterning by photolithography, ion implantation, and the like (S16).

The method of forming the wiring layer (not shown) is as follows. For example, an insulating layer is formed on the semiconductor substrate 10 that has been processed in steps S11 to S16, and the insulating layer is patterned, etched, and sputtered by photolithography, whereby the insulating layer and the gate are formed. Electrodes, contact plugs, and wiring are formed.

Further, at least one of the photoelectric conversion region 10b and the second semiconductor 12 may be manufactured by changing the impurity concentration during the formation of the semiconductor substrate 10 by epitaxial growth. With this method, the crystal defects in the multiplication region 15 are smaller than those in the multiplication region 15 when the photoelectric conversion region 10b and the second semiconductor 12 are formed by the ion implantation method, and noise can be reduced. is there.

[Effects, etc.]
The solid-state image sensor 100 includes a semiconductor substrate 10 in which light is incident on the upper surface, a first semiconductor 11 arranged in the semiconductor substrate 10, and a second semiconductor arranged below the first semiconductor 11 in the semiconductor substrate 10. 12 and. The first semiconductor 11 and the bonding region 10a bonded to the first semiconductor 11 of the semiconductor substrate 10 constitute a PD. The junction region 10a is an example of the first portion, and the PD is an example of the first photoelectric conversion unit. The photoelectric conversion region 10b bonded to the second semiconductor 12 of the second semiconductor 12 and the semiconductor substrate 10 constitutes an APD. The photoelectric conversion region 10b is an example of the second part, and APD is an example of the second photoelectric conversion part. The APD includes a multiplication region 15 in which the charge is multiplied by the avalanche multiplication.

In such a solid-state image sensor 100, the APD is arranged on the lower surface side in the semiconductor substrate 10 where short-wavelength light is difficult to reach and long-wavelength light is easy to reach. Therefore, if the APD is used for detecting long-wavelength light, the solid-state image sensor 100 can detect long-wavelength light with relatively high sensitivity.

Further, in the solid-state image sensor 100, PD and APD have different positions in the vertical direction. Therefore, in the solid-state image sensor 100, the number of PDs can be increased, and by increasing the number of PDs, short-wavelength light can be detected with high resolution.

As described above, the solid-state image sensor 100 can detect short-wavelength light with high resolution and long-wavelength light with high sensitivity.

Further, the solid-state image sensor 100 includes a plurality of first semiconductors 11 arranged in an array in the semiconductor substrate 10, and a plurality of first semiconductors 11 arranged in an array below the plurality of first semiconductors 11 in the semiconductor substrate 10. A second semiconductor 12 is provided.

In this way, the solid-state image sensor 100 can output a luminance image or a distance image by a plurality of PDs, and can output a luminance image or a distance image by a plurality of APDs.

Further, the solid-state image sensor 100 is a transfer region 14 in which charges generated in the APD are accumulated, one end of which is connected to the second semiconductor 12, and the other end of which is from the upper surface of the semiconductor substrate 10. A transfer region 14 exposed to the outside and a transfer transistor TRN2 arranged at the other end of the transfer region 14 are provided. The transfer region is an example of a fourth semiconductor.

In this way, the solid-state image sensor 100 can transfer the electric charge generated in the APD.

(Embodiment 2)
[Construction]
Hereinafter, the structure of the solid-state image sensor according to the second embodiment will be described. FIG. 5 is a plan view of the solid-state image sensor according to the second embodiment. FIG. 6 is a cross-sectional view of the solid-state image sensor according to the second embodiment. FIG. 6 is a cross-sectional view of the solid-state image sensor 200 cut along the VI-VI line of FIG. In FIG. 5, the first semiconductor 21 is actually located in the semiconductor substrate 20, but is shown by a solid line for clarifying the arrangement.

As shown in FIGS. 5 and 6, the solid-state image sensor 200 according to the second embodiment includes a semiconductor substrate 20, a first semiconductor 21, a second semiconductor 22, a separation region 23, and a transfer region 24. Be prepared. The separation region 23 is an example of the third semiconductor, and the transfer region 24 is an example of the fourth semiconductor. The semiconductor substrate 20 includes a plurality of bonding regions 20a, a photoelectric conversion region 20b, and a well region 20c. Hereinafter, in the second embodiment, the differences between the solid-state image sensor 200 and the solid-state image sensor 100 will be mainly described, and the description of the above-mentioned items will be omitted or simplified.

In the solid-state image sensor 200, one pixel includes one APD and two PDs. That is, the solid-state image sensor 200 includes a plurality of PDs for one APD. Therefore, in the solid-state image sensor 200, the total number of the plurality of APDs (that is, the plurality of first semiconductors 21) is larger than the total number of the plurality of PDs (that is, the plurality of second semiconductors 22). Further, in a plan view, one second semiconductor 22 overlaps with a plurality of first semiconductors 21. The number of PDs included in one pixel, the arrangement of PDs in one pixel, the shape of PDs, and the like are not particularly limited.

The plurality of PDs are arranged in the well region 20c of the semiconductor substrate 20 and are electrically separated. Also in the solid-state image sensor 200, the second semiconductor 22 is arranged below the first semiconductor 21 in the semiconductor substrate 20.

For example, when the photoelectric conversion region 20b is formed of silicon, PD is used for detecting visible light, and APD is used for detecting near-infrared light, the luminance image obtained by PD can be made high resolution. it can. In addition, silicon has a low absorption rate of near-infrared light. Therefore, it is useful to have a configuration in which near-infrared light is avalanche-multipliered in the APD photomultiplier region 25.

Further, in the solid-state image sensor 200, the second semiconductor 22 is larger than the first semiconductor 21 in a plan view. In the solid-state image sensor 200, in a plan view, all of the first semiconductors 21 overlap the second semiconductor, and the light receiving area of the APD is relatively larger than the light receiving area of the PD. Therefore, it is expected that the sensitivity to near-infrared light will be improved.

Further, since the photoelectric conversion region 20b is located on the side opposite to the upper surface (light incident surface) of the semiconductor substrate 20, the film can be thickened relatively freely. As a result, the APD can detect near-infrared light by increasing the quantum efficiency.

By the way, as shown in FIG. 5, a plurality of transistors constituting a pixel circuit are arranged on the upper surface of the semiconductor substrate 20. The pixel circuit for PD includes a transfer transistor TRN1, a reset transistor RST1, a floating diffusion region FD1, an amplification transistor SF1, and a selection transistor SEL1. The pixel circuit for APD includes a transfer transistor TRN2, a reset transistor RST2, a floating diffusion region FD2, an amplification transistor SF2, and a selection transistor SEL2.

In the solid-state image sensor 200, the pixel circuit for PD and the pixel circuit for APD are independent. On the other hand, the pixel circuits of the two PDs are standardized, whereby the mounting area of the pixel circuits for PDs is reduced. It should be noted that the pixel circuit can be shared even when the number of PDs is three or more. The pixel circuit for PD and the pixel circuit for APD may be shared.

[Effects, etc.]
In the solid-state image sensor 200, the second semiconductor 22 is larger than the first semiconductor 21 in a plan view.

As described above, in the solid-state image sensor 200, since the light receiving area of the APD composed of the second semiconductor 22 is large, the sensitivity of near-infrared light can be increased.

Further, in the solid-state image sensor 200, the total number of the plurality of first semiconductors 21 is larger than the total number of the plurality of second semiconductors 22.

As described above, in the solid-state image sensor 200, since the number of PDs composed of the first semiconductor 21 is large, the image (luminance image or distance image) based on the light detected by the PD is increased in resolution.

Further, in the solid-state image sensor 200, one second semiconductor 22 overlaps with a plurality of first semiconductors 21 in a plan view.

Thereby, a plurality of first semiconductors 21 can be densely packed to realize miniaturization of the solid-state image sensor 200.

(Embodiment 3)
[Construction]
Hereinafter, the structure of the solid-state image sensor according to the third embodiment will be described. FIG. 7 is a plan view of the solid-state image sensor according to the third embodiment. 8 and 9 are cross-sectional views of the solid-state image sensor according to the second embodiment. FIG. 8 is a cross-sectional view of the solid-state image sensor 300 cut along the line VIII-VIII of FIG. FIG. 9 is a cross-sectional view when the solid-state image sensor 300 is cut by the IX-IX line of FIG. In FIG. 7, the first semiconductor 31 is actually located in the semiconductor substrate 30, but is shown by a solid line for clarifying the arrangement.

As shown in FIGS. 7 to 9, the solid-state image sensor 300 according to the third embodiment transfers the semiconductor substrate 30, the plurality of first semiconductors 31, the plurality of second semiconductors 32, the separation region 33, and the like. It includes a region 34. The separation region 33 is an example of the third semiconductor, and the transfer region 34 is an example of the fourth semiconductor. The semiconductor substrate 30 includes a plurality of bonding regions 30a, a photoelectric conversion region 30b, and a well region 30c. Hereinafter, in the third embodiment, the differences between the solid-state image sensor 300 and the solid-state image sensor 100 and the solid-state image sensor 200 will be mainly described, and the description of the above-mentioned items will be omitted or simplified.

In the solid-state image sensor 300, one pixel includes one APD and four PDs. That is, the solid-state image sensor 200 includes four PDs for one APD. The number of PDs included in one pixel, the arrangement of PDs in one pixel, the shape of PDs, and the like are not particularly limited.

A Bayer array color filter is applied to the four PDs. In the solid-state image sensor 300, an APD for detecting near-infrared light with high sensitivity is added while supporting such an existing color filter having a Bayer arrangement.

The PD (that is, the first semiconductor 31) is also arranged above the separation region 33. When an image is output by an avalanche-multiplier signal charge in the photomultiplier region 35 of the APD, a negative bias voltage (also called a breakdown voltage) is applied to the lower surface side of the photomultiplier region 30b. At this time, it is necessary to electrically separate the plurality of APDs (that is, the plurality of second semiconductors 32) so that the outputs of each pixel are not mixed. Further, in order to stabilize the potential of the well region 30c in which the transistors constituting the pixel circuit are arranged, it is also necessary to electrically separate the well region 30c and the photoelectric conversion region 30b.

In order to achieve both the electrical separation of a plurality of APDs and the electrical separation of the well region 30c and the photoelectric conversion region 30b, the separation region 33 is reset to form a constant potential barrier between pixels. It needs to be kept in a depleted state, which has a potential lower than that of the APD in the state and a potential higher than that of the well region 30c. However, the range of the impurity concentration of the separation region 33 satisfying this condition is limited, and it is difficult to manufacture the solid-state image sensor 300 having the separation region 33 satisfying this condition.

If the PD is arranged on the separation region 33, even if a negative bias voltage is applied to the lower surface side of the photoelectric conversion region 30b, a PD to which a positive bias voltage is applied in a reset state is arranged above the separation region 33. Will be done. Therefore, the electrical separation ability (that is, the dielectric strength) between the well region 30c and the photoelectric conversion region 30b is improved. In particular, of the separation region 33, the region P (shown in FIG. 7) adjacent to the corner of the APD in a plan view is formed to have a relatively wide width and is electrically connected between the well region 30c and the photoelectric conversion region 30b. There is a high concern that the separation capacity will decline. Therefore, it is useful to place the PD above the region P.

Further, as shown in FIG. 9, in the solid-state image sensor 300, the impurity concentrations of the well region 30c and the junction region 30a, which are P-type semiconductors, are different. Specifically, the impurity concentration in the bonding region 30a is lower than the impurity concentration in the well region 30c. As a result, the depletion layer extends on the lower surface side of the PD, so that the sensitivity of the PD can be improved.

Further, in the solid-state image sensor 300, the impurity concentrations of the second semiconductor 32, the transfer region 34, and the first semiconductor 31, which are N-type semiconductors, are different. Specifically, the impurity concentration of the second semiconductor 32 and the impurity concentration of the transfer region 34 are higher than the impurity concentration of the first semiconductor 31. As a result, the negative bias voltage applied to the photoelectric conversion region 30b can be reduced when the APD is driven to multiply the avalanche. If the negative bias voltage applied to the photoelectric conversion region 30b is reduced, the risk of conduction (in other words, punch-through) between the photoelectric conversion region 30b and the well region 30c can be reduced.

By the way, as shown in FIG. 7, a plurality of transistors constituting a pixel circuit are arranged on the upper surface of the semiconductor substrate 30. The pixel circuit for PD includes a transfer transistor TRN1, a reset transistor RST1, a floating diffusion region FD1, an amplification transistor SF1, and a selection transistor SEL1. The pixel circuit for APD includes a transfer transistor TRN2, a reset transistor RST2, a floating diffusion region FD2, an amplification transistor SF2, and a selection transistor SEL2.

In the solid-state image sensor 300, the pixel circuit for PD and the pixel circuit for APD are independent. The pixel circuits of the two PDs are standardized, and one pixel has two sets of pixel circuits corresponding to the four PDs. As a result, the mounting area of the pixel circuit for PD is reduced. It should be noted that the pixel circuit can be shared even when the number of PDs is three or more. Further, the pixel circuit for PD and the pixel circuit for APD may be shared.

[Effects, etc.]
The solid-state image sensor 300 is located between the plurality of second semiconductors 32 in the semiconductor substrate 30, and includes a separation region 33 that separates the plurality of second semiconductors 32. The separation region 33 is an example of a third semiconductor. In plan view, the separation region 33 overlaps with at least one of the plurality of first semiconductors 31.

As a result, conduction between the photoelectric conversion region 30b and the well region 30c is suppressed.

Further, the solid-state image sensor 300 has four first semiconductors 31 with respect to one second semiconductor 32, and the four second semiconductors 32 form a 2 × 2 arrangement.

As described above, in the solid-state image sensor 300, APD is added while maintaining the Bayer arrangement of PD. That is, the Bayer array can be applied to the color filter of the second semiconductor 32 corresponding to the detection of visible light.

Further, in the solid-state imaging device 300, the semiconductor substrate 30 is formed of a first conductive type (for example, P type) semiconductor, and the first semiconductor 31, the second semiconductor 32, and the transfer region 34 are the first conductive type. It is formed by a second conductive type (for example, N type) semiconductor different from the type. The impurity concentration of the second semiconductor 32 and the impurity concentration of the transfer region 34 are higher than the impurity concentration of the first semiconductor 31.

As a result, the negative bias voltage applied to the photoelectric conversion region 30b can be reduced when the APD is driven to multiply the avalanche. If the voltage of the negative bias applied to the photoelectric conversion region 30b is reduced, it is possible to suppress the conduction between the photoelectric conversion region 30b and the well region 30c.

Further, in the solid-state image sensor 300, the semiconductor substrate 30 includes a well region 30c located around the first semiconductor 31, and the impurity concentration in the junction region 30a of the semiconductor substrate 30 is lower than the impurity concentration in the well region 30c. ..

As a result, the depletion layer extends on the lower surface side of the PD, so that the sensitivity of the PD can be improved.

(Other embodiments)
Although the solid-state image sensor according to the embodiment has been described above, the present disclosure is not limited to the above embodiment.

For example, in the above embodiment, the first photoelectric conversion unit does not include a multiplication region, but may include a multiplication region. That is, the first photoelectric conversion unit may be an APD instead of a PD.

In addition, all the numbers used in the description in the above-described embodiment are exemplified for the purpose of specifically explaining the present disclosure, and the present disclosure is not limited to the illustrated numbers.

Further, the circuit configuration described in the above embodiment is an example, and the present disclosure is not limited to the above circuit configuration. That is, similarly to the above circuit configuration, a circuit capable of realizing the characteristic functions of the present disclosure is also included in the present disclosure. For example, the present disclosure also discloses an element in which elements such as a switching element (transistor), a resistance element, or a capacitive element are connected in series or in parallel to a certain element within a range in which the same function as the above circuit configuration can be realized. included.

Further, in the above-described embodiment, the main materials constituting each layer of the laminated structure of the solid-state image sensor are illustrated, but each layer of the laminated structure of the solid-state image sensor is the same as the laminated structure of the above-described embodiment. Other materials may be included as long as the functions of the above can be realized. Further, in the drawings, the corners and sides of each component are shown linearly, but the present disclosure also includes those having rounded corners and sides due to manufacturing reasons and the like.

In addition, it is realized by applying various modifications to each embodiment that can be conceived by those skilled in the art, or by arbitrarily combining the components and functions of each embodiment without departing from the spirit of the present disclosure. Also included in this disclosure. For example, the present disclosure may be realized as a method for manufacturing a solid-state image sensor.

The solid-state image sensor of the present disclosure can be used for cameras, ToF sensors, and the like.

10, 20, 30 Semiconductor substrate 10a, 20a, 30a Junction region 10b, 20b, 30b Photoelectric conversion region 10c, 20c, 30c Well region 11, 21, 31 First semiconductor 12, 22, 32 Second semiconductor 13, 23, 33 Separation region (third semiconductor)
14, 24, 34 Transfer area (fourth semiconductor)
15, 25, 35 Multiplying area 100, 200, 300 Solid-state image sensor 101 pixel 102 pixel array 103 Vertical scanning circuit 104 Horizontal scanning circuit 105 Reading circuit 111 Buffer amplifier FD1, FD2 Floating diffusion region RST1, RST2 Reset transistor SEL1, SEL2 selection Transistor SF1, SF2 Amplification transistor TRN1, TRN2 Transfer transistor

Claims (10)

A semiconductor substrate in which light is incident on the upper surface,
The first semiconductor arranged in the semiconductor substrate and
A second semiconductor arranged below the first semiconductor in the semiconductor substrate is provided.
The first semiconductor and the first portion of the semiconductor substrate bonded to the first semiconductor form a first photoelectric conversion unit.
The second semiconductor and the second portion of the semiconductor substrate bonded to the second semiconductor constitute a second photoelectric conversion unit.
The second photoelectric conversion unit is a solid-state image sensor including a multiplication region in which charges are multiplied by avalanche multiplication. The solid-state image sensor according to claim 1, wherein the second semiconductor is larger than the first semiconductor in a plan view. The solid-state image sensor
A claim comprising a plurality of the first semiconductors arranged in an array in the semiconductor substrate and a plurality of the second semiconductors arranged in an array below the plurality of the first semiconductors in the semiconductor substrate. The solid-state imaging device according to 1 or 2. The solid-state image sensor according to claim 3, wherein the total number of the plurality of first semiconductors is larger than the total number of the plurality of second semiconductors. The solid-state imaging device according to claim 3 or 4, wherein one second semiconductor overlaps with a plurality of the first semiconductors in a plan view. Further, a third semiconductor located between the plurality of second semiconductors in the semiconductor substrate and separating the plurality of second semiconductors is provided.
The solid-state imaging device according to any one of claims 3 to 5, wherein the third semiconductor overlaps at least one of the plurality of first semiconductors in a plan view. The solid-state image sensor has four first semiconductors with respect to one second semiconductor, and the four second semiconductors form a 2 × 2 array, any one of claims 3 to 6. The solid-state image sensor according to the above. further,
A fourth semiconductor in which charges generated in the second photoelectric conversion unit are accumulated, one end of which is connected to the second semiconductor and the other end of which is exposed to the outside from the upper surface of the semiconductor substrate. Four semiconductors and
The solid-state image sensor according to any one of claims 1 to 7, further comprising a transistor arranged at the other end of the fourth semiconductor. The semiconductor substrate is formed of a first conductive type semiconductor, and is formed of a first conductive type semiconductor.
The first semiconductor, the second semiconductor, and the fourth semiconductor are formed of a second conductive type semiconductor different from the first conductive type.
The solid-state image sensor according to claim 8, wherein the impurity concentration of the second semiconductor and the impurity concentration of the fourth semiconductor are higher than the impurity concentration of the first semiconductor. The semiconductor substrate includes a well region located around the first semiconductor.
The solid-state image sensor according to any one of claims 1 to 9, wherein the impurity concentration of the first portion of the semiconductor substrate is lower than the impurity concentration of the well region.

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