JPH0973786A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an internal boosted potential generating circuit making the semiconductor device mounted with BiCMOSs, BiN MOS circuits and high resistance load type cells and TFT load type cells operate with the low power source voltage of the order of 1.5V. SOLUTION: In an internal boosted potential generating circuit for BiCMOS/ BiNMOS, the base of a bipolar transistor 41 is connected to a boosted potential power source line VCHGB 11 and a constant current source 42 is connected between the collector of the transistor and the GND 4 and a constant current is set so that the voltage between the base and the collector becomes the voltage of the order of 0.6Vs and a VCC and the collector voltage of the bipolar transistor 41 are inputted to a differential amplifier 43 and then the operation of a charge pump circuit is subjected to a feedback control by using a compared result. Moreover, in an internal boosted potential generating circuit for high resistance load type/TFT load type memory, the operation of the charge pump circuit is subjected to the feedback control by using an NMOS connected to a diode instead of the bipolar detection element 41 with a similar circuit constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a logic using a so-called bipolar-CMOS (hereinafter simply referred to as "BiCMOS") technology in which a bipolar transistor and a MOS transistor are integrated on the same semiconductor substrate. The present invention relates to a low voltage operation technology of a circuit. Also,
The present invention relates to a low-voltage operation technology of SRAM (static type random access memory) that writes and reads a large amount of data at high speed.

[0002]

2. Description of the Related Art Conventionally, a BiCMOS logic gate or BiNMOS logic gate in which a bipolar and a MOS are integrated on the same substrate has a large driving ability and a high speed in the CMOS technology excellent in low power consumption and high integration. By incorporating the excellent bipolar technology, excellent high-speed performance that cannot be realized by the CMOS technology can be realized.

In the configuration normally used, these logic gates have a potential outside the LSI when the output pull-up bipolar transistor connected to the output terminal is turned on and the output level outputs a high potential. Base-emitter voltage VF from the high-potential side power supply potential supplied from
Only drops.

In recent years, the power supply voltage has been lowered due to reliability problems, power consumption problems, etc. due to the generation of hot electrons in MOS transistors.

When the power supply voltage drops in this way, Bi
Since the output logic amplitude of the CMOS logic gate is small, there has been a problem that the noise margin is lowered and the operation speed is deteriorated.

As one of the constitutions for solving this problem, Japanese Patent Application No. 6-78297 filed by the same applicant as the present application,
Okamura et al. Provided an internal booster circuit inside the LSI, generated a boosted potential higher than the power supply voltage on the high potential side supplied from the outside in the internal booster circuit, and generated the boosted voltage at the base of the BiCMOS gate circuit or BiNMOS gate circuit. A configuration is proposed in which it is supplied to the drive circuit. The configuration described in Japanese Patent Application No. 6-78297 will be described below.

FIG. 4 is a diagram showing a circuit configuration of a BiCMOS logic gate described in the above-mentioned Japanese Patent Application No. 6-78297.

Referring to FIG. 4, a high-potential-side power supply voltage (referred to as "VCC") 3 whose collector is supplied from outside the LSI 3
To the output terminal 2 and the base to P
Channel MOS transistor (referred to as "PMOS") 7
The first NPN bipolar transistor 5 connected to the connection point between the drain of the first N-channel MOS transistor (referred to as “NMOS”) 8 and the drain of the first N-channel MOS transistor (referred to as “NMOS”); Connect to the power supply voltage (referred to as "GND") 4 and connect the base
A second NPN bipolar transistor 6 which is commonly connected to the source of the MOS 8 and the source of the second NMOS 9.
And, the drain of the second NMOS 9 is the output terminal 2
It is connected to the.

A resistor element 10 is connected between the base of the second NPN bipolar transistor 6 and the GND 4 for extracting the base charge of the second NPN bipolar transistor 6.

The gate of the PMOS 7, the gate of the first NMOS 8, and the gate of the second NMOS 9 are all connected to the input terminal 1.

The source of the PMOS 7 is the second power source ("VC
HGB ”). The internal boosted potential generation circuit 16 supplies the power source potential boosted from VCC3 to VCH.
It is supplied to GB11.

In this structure, the level of the signal input to the input terminal 1 is changed from the high level to the low level.
w) When moving to the level, the PMOS 7 and the first NMOS
8 raises the output potential of the inverter (CMOS inverter circuit), and thus raises the base potential of the first NPN bipolar transistor 5.

As a result, the level of the output terminal 2 rises while maintaining the level lowered by the base-emitter voltage VF of the bipolar transistor from the base potential, and the level of the output terminal 2 lowered by VF from VCHGB11. Then, the first bipolar transistor 5 is turned off,
Stop supplying current to the output load.

Here, the potential of VCHGB11 is set to VCC3.
If set to a potential higher than the potential of about 0.6 V, the collector-emitter voltage of the first bipolar transistor 5 becomes
Since 0.2 to 0.3 V is secured, the output potential can be raised to the power supply potential VCC without saturation.

Further, the NPN bipolar transistor is
Generally, it has a high current amplification factor of about 50 to 100 and supplies the base current of the first bipolar transistor 5 only when the voltage of the output terminal 2 is raised, so that the voltage of VCHGB11 is determined internally. The boosted potential generation circuit 16 does not have to have a large current supply capability.

Further, VCHGB11 can be supplied to a large number of BiCMOS gate circuits by one internal boosted potential generating circuit.

FIG. 5 is a diagram showing a circuit configuration of the BiNMOS logic gate described in the above-mentioned Japanese Patent Application No. 6-78297.

Referring to FIG. 5, the first NPN bipolar
12, the collector is connected to VCC3, the emitter is connected to the output terminal 2, and the base is connected to the connection point between the drain of the PMOS 13 and the drain of the first NMOS 15.

The source of the first NMOS 15 is connected to GND4, the source is connected to GND4, and the drain is output terminal 2
And a second NMOS 14 connected to.

Gate of the PMOS 13, first and second NMO
The gates of S15 and S14 are connected to the input terminal 1.

The source of the PMOS 13 is connected to VCHGB11, and VCHGB11 is set to the power supply potential boosted by the internal boosted potential generation circuit 16.

The process of changing the input level from the high level to the low level will be described below.

The output potential of the inverter composed of the PMOS 13 and the first NMOS 15, that is, the first bipolar 12
The base potential of is increased. At the same time, the second NMOS 14 turns off.

As a result, the level of the output terminal 2 rises while maintaining the level of the base-emitter voltage VF lowered from the base potential, and the potential of the output terminal 2 drops by VF from VCHGB11 to the first bipolar transistor. 12 turns off and stops supplying current to the output load.

As in the case of the BiCMOS gate, if the potential of VCHGB11 is set higher than the potential of VCC3 by about 0.6V, the first bipolar transistor is formed.
Since the collector-emitter voltage of 12 is secured at 0.2 to 0.3 V, the output potential can be raised to the potential of VCC without being saturated. The current driving capability required for the internal boosted potential generating circuit 16 is exactly the same as that of the BiCMOS gate.

The above BiCMOS gate circuit and Bi
The NMOS gate circuit is not limited to inverter logic, but NA
It can also be applied to ND gates, NOR gates, and the like.

The potential of VCHGB11 needs to be higher than the potential of VCC3 by about 0.6V, and its accuracy is 0.6V.
It is necessary to set it to about ± 0.1V. VCHGB11 is VCC
When the voltage exceeds 0.7 V, the first bipolar transistor 5 (or 12) is saturated and the logical operation becomes impossible.

Then, VCHGB11 is 0.5 than VCC.
When the voltage becomes V or less, the increase in gate delay becomes 10% or more, and the high speed performance deteriorates.

On the other hand, a static RAM (SRAM) for reading and writing a large amount of data at high speed uses BiCMOS or CMOS as a peripheral circuit, is formed in various formats, and has a large number of memory cells for storing information arranged therein. Consists of

As memory cells, four NMOS and two
There is a so-called "complete CMOS type memory cell" in which a basic cell is configured by using one PMOS. However, since the complete CMOS type cell occupies a large area, there is a problem that it is not suitable for a large-scale SRAM configuration.

As a conventional structure for solving this, a so-called "high resistance type memory cell" (hereinafter abbreviated as "high resistance cell") using four NMOSs and two high resistances laminated thereon is used. There is.

There is a TFT type memory cell (hereinafter abbreviated as "TFT cell") in which two thin film transistors (hereinafter referred to as "TFT") are stacked on four NMOSs.

In these high resistance cells and TFT cells,
There is a great advantage that a smaller area and higher integration can be achieved as compared with the complete CMOS type cell, but on the other hand, there is a problem in low voltage operability.

As a conventional method for further solving the problem of low voltage operation, when the memory is accessed, the High level of the word line is supplied to the memory cell at the voltage level (in many cases, supplied from outside the LSI). A method of setting a potential higher than the high-potential-side power supply voltage VCC) is known. Further, this potential is generated using an internal boosted potential generating circuit. Then, these methods are disclosed in
No. 82, etc. That is, Japanese Patent Laid-Open No. 5-1208
No. 82 discloses a static type semiconductor memory device that achieves a low voltage operation of, for example, 2 V or less while using a high resistance type memory cell or a TFT type memory cell. The threshold voltage including the substrate bias effect of the driving MOSFET (MOS field effect transistor) is Vth, which is the internal voltage of the memory cell at the time of conventional writing, with the voltage of the High level being Vth
There has been proposed a semiconductor memory device provided with a means for making the voltage higher than CC-Vth. Further, in the above-mentioned Japanese Patent Laid-Open No. 5-120882, the word line is set to Hig
The voltage at the h level is set to a voltage Vch higher than the power supply voltage VCC, and the voltage inside the memory cell at the time of writing is Vch.
A configuration is disclosed in which ch-Vth is set to enable low voltage operation.

As another prior art of a low voltage static RAM, for example, Japanese Patent Laid-Open No. 7-45080 discloses a static RAM having a complicated structure for controlling the switching of the high level of a word line as needed. A configuration has been proposed in which the high level of the word line is set to VCC or higher with a simple configuration without using a control circuit, and low voltage operation is possible using a high resistance cell and a TFT memory cell.

The conventional example will be described below. FIG. 6 is a circuit diagram when a high resistance cell is used.

In FIG. 6, a first inverter 21 composed of a load resistor R1 and a driver transistor NMOS26 connected in series between a power supply VCC3 and GND4, and a resistor R2 and a driver transistor N connected in series in the same manner.
The second inverter 22 composed of the MOS 27 is cross-connected to each other. That is, the NMO of the first inverter 21.
The gate of S26 is connected to the storage node N2 of the second inverter 22, and the gate of the NMOS 27 of the second inverter 22 is connected to the storage node N1 of the first inverter.

Further, the first and second access transistors NMOS are provided between the storage nodes N1 and N2 of the first and second inverters 21 and 22 and the bit line pair BL and BLN, respectively.
28 and NMOS 29 are connected, and the gates of the first and second access transistors NMOS28 and NMOS29 are connected to the word line WL. High resistance memory cell
23 is formed.

A buffer 24, which is a circuit for driving the word line WL, is connected between one end of the word line WL and the output end of a row (ROW) address decoder (not shown).

The buffer 24 has a power supply VCHGW25 having a boosted voltage level higher than the cell supply voltage level (high potential side external power supply voltage VCC3 in FIG. 6) supplied to the memory cell 23.
Is used as the operating power supply, and the voltage level is set to the boosted power supply voltage VCHGW25 as the High level of the word line WL during both the writing and reading operations. That is, at the time of both the writing and reading operations, the High level of the word line WL is set by the buffer 24 to the same level VCHGW25 which is higher than the cell supply voltage level supplied to the memory cells. The boosted voltage V
CHGW 25 is generated and supplied by the internal boosted potential generation circuit 30.

Further, when the power supply voltage VCC3 is lowered to operate at a low voltage, the static noise margin, which is an index of the stability of the stored information, is such that the high level of the word line is higher than that of VCC3 by the access transistor NMOS28.
It becomes the maximum when the voltage level is set higher by the threshold voltage including the substrate bias effect of the NMOS 29.

The word line potential V (WL) at this time is expressed by the following equation (1), where VCC is the power supply voltage (cell supply voltage level) and Vthw is the threshold value including the substrate bias effect of the NMOS 28 and the NMOS 29. To be done.

V (WL) = VCC + Vthw (1)

In other words, when the word line High level is set to this V (WL), theoretically, the operation at the lowest power supply voltage VCC is realized.

When a TFT memory cell is used, the resistors R1 and R2 in the high resistance cell 23 shown in FIG.
The structure is replaced with a channel type thin film transistor (TFT), and the method for realizing the low voltage operation is exactly the same as the case of using the high resistance cell described above.

The BiCMO shown in FIGS. 4 and 5 is also used.
The S and BiNMOS logic gates can be applied to a general logic circuit, for example, the high resistance cell or T described above.
Of course, it can be applied to a decoder circuit of a large-scale high-speed SRAM using FT cells. In this case, SRAM
But, especially BiCMOS SRA which can obtain super high speed performance
M is constructed.

[0047]

As described above,
BiCMOS logic gate pull-up bipolar base is about 0.6V from VCC, high resistance or TF
The high level V (WL) of the word line of the T memory cell is set to V
It is known that internal voltage boosting to CC + Vthw ensures low voltage operation of both.

However, no specific means (configuration) for actually determining these optimum internal boosted voltages and controlling and supplying the internal boosted voltages has been known so far. That is, the conventional method is only the proposal, and there is no configuration example in which the optimum control of the internal boosted voltage is actually realized.

The present invention has been made in view of such problems, and an object thereof is a semiconductor provided with a BiCMOS circuit or a high resistance cell or a TFT memory cell for realizing a low voltage operation. In the device, it is to realize a configuration in which the optimum boosted voltage is determined, and the boosted voltage is controlled and supplied.
That is, the present invention provides an internal boosted potential generation circuit for generating the optimum boosted potential (VCHGB) in the BiCMOS circuit, and an internal boosted potential generation circuit for generating the optimum boosted voltage (VCHGW) in the SRAM. Especially.

[0050]

To achieve the above object, according to the present invention, a logic circuit is constituted by MOS transistors, the output of the logic circuit is input to a bipolar transistor of an output stage, and an output is taken out from the bipolar transistor. In the semiconductor device described above, there is provided boosted potential generating means for supplying a potential higher than the potential of the first high-potential-side power source supplied to the bipolar transistor as the second high-potential-side power source of the MOS transistor. The potential generating means includes a differential amplifying means for comparing a potential obtained by dropping a predetermined potential from the potential of the second high potential side power source with a potential of the second high potential side power source, The charge pump circuit is feedback-controlled based on the output to keep the potential of the second high potential side power source higher than the first high potential side power source by the predetermined potential. It is controlled to provide a semiconductor device according to claim.

The present invention is preferably characterized in that the predetermined potential is controlled so as to be substantially equal to the base-collector voltage immediately before the output-stage bipolar transistor is saturated.

Further, in the present invention, preferably, the boosted potential generating means is inserted in a diode type connection form between the second high potential side power source and one input terminal of the differential amplifying means. A second bipolar transistor of the same type as that of the output stage bipolar transistor, and a predetermined current is supplied from the constant current source from the second high potential side power supply line side through the second bipolar transistor. It is characterized by having done.

According to the present invention, a collector is connected to a first high-potential-side power source supplied from the outside, a first NPN bipolar transistor having an emitter connected to an output terminal, and a collector is connected to the output terminal, and an emitter is connected. A second NPN bipolar transistor connected to a low-potential-side power supply, and a push-pull type buffer including the first and second NPN transistors.
A plurality of MOS transistors that drive the base of the PN bipolar transistor; and an internal boosted potential generation circuit that generates a boosted potential higher than the first high-potential-side power supply as a second high-potential-side power supply, A BiCMOS semiconductor integrated circuit in which the source or drain terminal of a MOS transistor for charging and driving the base of the first NPN bipolar transistor is connected to the second high-potential-side power supply supplied by the internal boosted potential generating circuit. Wherein the internal boosted potential generation circuit has an anode connected to the second high-potential-side power supply and a cathode connected to the low-potential-side power supply via a constant current source; And a differential amplifier in which the cathode of the PN diode is connected to the differential input terminals, respectively. , To provide a semiconductor device which is characterized in that by switching pulses by output of the differential amplifier is fed back control means for generating said internal boosted potential charges the capacitor.

Further, according to the present invention, an NPN bipolar transistor in which a collector is connected to a first high-potential-side power source supplied from the outside and an emitter is connected to an output terminal, and a source terminal and a drain of one or a plurality of MOS transistors are provided. A load driving circuit having terminals connected in series or in parallel between the output terminal and a low-potential-side power supply;
A plurality of MOS transistors that drive the base of the PN bipolar transistor; and an internal boosted potential generation circuit that generates an internal boosted potential higher than the first high-potential-side power source as a second high-potential-side power source, The second high-potential-side power supply supplied by the internal boosted potential generation circuit is supplied with the N
A BiNMOS semiconductor integrated circuit in which a source or a drain terminal of a MOS transistor for charging and driving a base of a PN bipolar transistor is connected, wherein the internal boosted potential generation circuit connects an anode to the second high potential side power supply. In addition, a PN diode having a cathode connected to a low potential side power source via a constant current source, a first high potential side power source and a cathode of the PN diode are connected to a differential input terminal respectively. And a dynamic amplifier, wherein a means for switching a pulse according to an output result of the differential amplifier to charge a capacitor to generate the internal boosted potential is feedback-controlled.

[0055]

Operation: BiCMOS and BiNMOS according to the present invention
The internal boosted potential generating circuit for use has a configuration in which the forward current between the base and the collector, which is a physical factor of the saturation operation of the bipolar transistor, is referred to. Also, SRA
In the internal boosted potential generation circuit for M memory cells, the source is V
The threshold voltage including the substrate effect of the access transistor grounded at CC is referred to, the desired boost voltage is accurately determined, and the determined voltage is compared with the actually obtained boost voltage. By controlling the charge pump circuit based on the comparison result, it is possible to generate the optimum boosted voltage with high accuracy.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

[0057]

First Embodiment FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention. FIG. 1 shows a BiCMOS circuit which enables the low voltage operation of the conventional example shown in FIGS.
And internal boosted potential generation circuit in BiNMOS circuit
FIG. 16 is a diagram for explaining a configuration for realizing 16.

According to this embodiment, first, BiCMOS,
And the optimum boosted potential value for operating the BiNMOS circuit at high speed is determined, the difference between this and the actually obtained boosted potential VCHGB11 is detected, and the comparison result is output.

Referring to FIG. 1, BiCMOS or BiN
A node 61 connected to the boosted power supply line VCHGB11 has a base and an emitter connected to the booster power supply line VCHGB11 and a collector of the bipolar transistor 41, which is manufactured by using the same process as that for manufacturing the MOS logic gate. A constant current source 42 is connected between the and GND4.

The differential amplifier 43 has one input terminal at VCC.
The other input terminal is connected to a node 61 which is a connection point between the collector of the bipolar transistor (detection element) 41 and the constant current source 42.

Now, returning to the conventional example shown in FIGS. 4 and 5, the factor that the optimum boosted potential becomes about VCC + 0.6 V will be considered.

When the boosted potential VCHGB11 is lower than VCC + 0.6V, the logical outputs of the BiCMOS and BiNMOS gates are reduced from VCC, and the voltage amplitude for driving the next stage is reduced. Therefore, it is desirable that the boosted voltage VCHGB11 be as high as possible.

However, the boosted voltage VCHGB11 is set to V
If CC + 0.6V is set too high, the speed is reduced due to the saturation of the first bipolar transistor 5 or 12, and finally the logic operation becomes impossible.

Considering this saturation phenomenon, the bipolar transistor 5 which is reverse biased in the normal operation mode.
It can be seen that the saturation phenomenon is caused by the forward bias between the 12 bases and the collector and the current injection from the base toward the collector.

Therefore, the optimum boosted potential VCC + 0.6V
In other words, it is considered to be the potential immediately before the current injection from the base to the collector of the first bipolar transistor 5 or 12 becomes remarkable.

Therefore, in the present embodiment shown in FIG.
The current value flowing from the base to the collector of the bipolar transistor (detection element) 41 whose base is connected to the boosted voltage VCHGB11, that is, the current value of the constant current source 42 is set to the current value immediately before this saturation phenomenon occurs.

As a result, the base-collector voltage of the bipolar transistor 41 is set to about 0.6V, and the potential of the node 61 becomes VCHGB-0.6V.

Therefore, the potentials at the differential input terminals of the differential amplifier 43 are VCHGB-0.6V and VCC, respectively (therefore, the difference between the input terminal potentials is VCHGB-0.6V-VC).
C), which is the boosted voltage VCHG in the differential amplifier 43.
It is equivalent to comparing B with VCC + 0.6V which is the optimum boosted potential.

As described above, the comparison result output terminal 44, to which the output terminal of the differential amplifier 43 is connected, generates an analog output according to the difference between the optimum boosted voltage and the actually obtained VCHGB11. Specifically, if VCHGB11 is higher than the optimum value, an output lowered from the balanced output potential is obtained at the comparison result output terminal 44, and if VCHGB11 is lower than the optimum value, an output raised from the balanced output potential is obtained. Also,
The absolute value of their displacement from the balanced output potential is VCHG.
It is approximately proportional to the absolute value of the difference between B11 and the optimum boosted potential.

In the present embodiment, a bipolar transistor is used as the detection element 41 for the sake of simplicity, but the essence of the present invention is BiCMOS and BiN.
The purpose is to use the electrical characteristics between the base and collector of a bipolar transistor that constitutes a MOS as a replica in a replica manner.

Therefore, as the detecting element 41, it is possible to use not the bipolar transistor itself but a PN diode to which only the base / collector forming process is applied, excluding the emitter forming process from the manufacturing process of the bipolar transistor. . In this case, an area for forming an extra emitter is not necessary, and there is an advantage that the area can be reduced.

[0072]

[Embodiment 2] FIG. 2 is a diagram showing a configuration of a second embodiment of the present invention. More specifically, FIG. 2 illustrates a configuration for realizing the internal boosted potential generation circuit 30 in the SRAM circuit using the high resistance cell or the TFT cell which enables the low voltage operation of the conventional example shown in FIG. FIG.

According to the circuit of this embodiment, the optimum boosted potential value that maximizes the static noise margin of the memory cell is first determined, and the difference between this and the actually obtained boosted potential VCHGW25 is detected, The comparison result is output.

In FIG. 2, an NMOS transistor manufactured using the same process as that for manufacturing the access transistors NMOS28 and NMOS29 (see FIG. 6) of the memory cell is used as the detection element 45.
The gate and drain of 45 are connected to the boosted power supply line VCHGW25, and the node 62 and GND4 connected to the source thereof.
A constant current source 46 is connected between and.

One input terminal of the differential amplifier 47 is connected to VCC3, and the other input terminal is connected to a node 62 which is a connection point between the source of the NMOS transistor 45 and the constant current source 46.

Now, returning to the conventional example shown in FIG. 6 again, the optimum High level word line potential is given by the above equation (1), and therefore the optimum boosted potential VCHGW25 is the access transistors NMOS28, 29. It is necessary to set it near the sum of Vthw and VCC including the substrate bias effect of

Referring to FIG. 2, in the embodiment of the present invention, V
NMOS with gate and drain connected to CHGW25
The current value flowing from the drain to the source of the detection element 45 composed of a transistor, that is, the current value of the constant current source 46 is appropriately selected, and the gate-source voltage of the NMOS transistor 45 is set to about Vthw.

As a result, the potential of the node 62 becomes VCHGW.
-Vthw.

Therefore, the potentials at the differential input terminals of the differential amplifier 47 are VCHGW-Vthw and VCC, respectively, which is equivalent to the comparison between VCHGW25 and VCC + Vthw which is the optimum boosted potential.

As described above, the comparison result output terminal 48, to which the output terminal of the differential amplifier 47 is connected, generates an analog output according to the difference between the optimum boosted potential and the actually obtained VCHGW 25. Specifically, if VCHGW25 is higher than the optimum value, an output reduced from the balanced output potential is obtained at the comparison result output terminal 48, and if VCHGW25 is lower than the optimum value,
An increased output is obtained from the balanced output potential. The absolute value of the displacement from the balanced output potential is VCHGW25
Is approximately proportional to the absolute value of the difference between the optimum boosted potential.

As described above, according to the first and second embodiments,
An output voltage corresponding to the displacement between the actually obtained boosted potential and the optimum boosted potential is obtained for each of the BiCMOS, BiNMOS, high resistance memory cell, and TFT memory cell.

[0082]

[Third Embodiment] In order to realize a circuit configuration for feedback-controlling an optimum boosted potential by using the circuit configuration according to the first or second embodiment, for example, the circuit shown in FIG. 3 may be applied to each. Good.

In FIG. 3, the NMOS 53, 54 and the PMOS are
A current mirror circuit is composed of 51 and 52.

NMOS5 constituting current mirror circuit
Gates 3 and 54 are connected to the comparison result input terminal 50, and the voltage of the comparison result output terminal 44 or 48 in the first or second embodiment shown in FIG. 1 or 2 is input as the gate voltage. .

The drain of the PMOS 52 is connected to the inverter row high potential line 55, and the drain of the NMOS 54 is connected to the inverter row low potential line 56. A current having the same current value as the drain current of the NMOS 53 is folded back by the PMOS 51 and 52 forming the current mirror circuit and is supplied from the drain of the PMOS 52 to the inverter column high potential line 55.

An odd number of stages of inverters 57 are connected to the inverter row high potential line 55 and the inverter row low potential line 56.

As is generally used, the inverter is composed of a CMOS type inverter circuit in which PMOS 59 and NMOS 60 are connected in series between power supplies.

The odd-numbered inverter trains are connected in a ring shape with the final-stage output as the first-stage input, so-called CMO.
The S ring oscillator 64 is configured.

One of the internal nodes of the ring oscillator 64 is the pumping pulse output terminal 58.

In the circuit configuration of FIG. 3, the comparison result input terminal 50
The current value of the current mirror circuit is modulated in accordance with the voltage applied to, and the oscillation frequency of the ring oscillator 64 that oscillates using this as a current source is modulated.

For example, if the voltage of the comparison result input terminal 50 is increased, the oscillation frequency of the pumping pulse output terminal 58 is increased, and if it is decreased, the oscillation frequency is decreased.

Further, the pumping pulse output terminal is input to the charge pump circuit 63. Charge pump circuit
63 uses the oscillation signal of the pumping pulse output terminal 58,
By switching a charging circuit of a capacitor (not shown), an internal boosted potential of a power supply voltage VCC3 or more supplied from the outside is generated. The specific configuration of the charge pump circuit 63 is described in Japanese Patent Application No. 6-78297, Japanese Patent Application Laid-Open No. 5-120882, etc. referred to in the above-mentioned prior art. A circuit configuration such as that described in Japanese Patent No. 162560 may be used, and the technique is well known, so the description thereof will be omitted.

By using the configuration in which the circuits shown in FIGS. 1 and 3 are combined, the boosted potential VCHGB11 for the BiCMOS and BiNMOS gates is generated.

Further, by combining the circuits shown in FIGS. 2 and 3, the boosted potential VCH for SRAM memory cells is obtained.
GW25 is generated.

As described above, in the preferred embodiment of the present invention, the difference between the actual VCHGB11 and VCHGW25 generated in the charge pump circuit 63 and the optimum boosted potentials in the circuits of FIGS. Is detected and the oscillation frequency at the pumping pulse output terminal 58 for driving the charge pump circuit 63 is feedback-controlled by the circuit configuration as shown in FIG. 3, so that a desired boosted potential can be finally obtained.

Further, since this configuration uses the feedback control method, for example, in the BiCMOS gate or the SRAM memory cell, the load consumption current supplied from the boosted potential fluctuates, and the boosted potential slightly fluctuates from the optimum value. However, the correction is promptly made to eliminate the fluctuation by the feedback control.

By applying the above embodiment, Bi
High resistance cells for CMOS, BiNMOS and SRAM,
It is possible to generate the optimum boosted voltage of the TFT cell, and it is possible to operate these circuits at a low voltage of, for example, about 1.5V.

Further, the circuit configuration shown in FIG. 3 for modulating the frequency of the ring oscillator and controlling the boosted potential is merely for explaining the embodiment of the present invention, and the present invention has such a configuration. Of course, it is not limited to only.

Further, instead of using the configuration shown in FIG. 3, according to the comparison result output which is the output of the circuit shown in FIG. 1 or 2, as described in the conventional example, that is, JP-A-5-120882. It is also possible to simply perform control such that the operation of the ring oscillator that drives the charge pump circuit is stopped or operated.

[0100]

As described above in detail, according to the present invention, BiCMOS and Bi which have not been realized up to now have been realized.
It is possible to generate the optimum boosted voltage for the high resistance cells for NMOS and SRAM and the TFT cell, and it is possible to operate these circuits at a low voltage up to about 1.5V.

[Brief description of drawings]

FIG. 1 shows a BiCMOS, B according to an embodiment of the present invention.
It is a figure for demonstrating the circuit structure of the internal boosted potential generation circuit for iNMOS gates.

FIG. 2 is a diagram for explaining the circuit configuration of an internal boosted potential generation circuit for a high resistance cell for SRAM or a TFT cell according to a second embodiment of the present invention.

FIG. 3 is a diagram for explaining the circuit configuration of an internal boosted potential generation circuit as a third embodiment of the present invention.

FIG. 4 is a diagram showing an example of a circuit configuration of a conventional low-voltage operation BiCMOS gate.

FIG. 5 is a diagram showing a circuit configuration of a conventional low-voltage operation BiNMOS gate.

FIG. 6 is a diagram showing a configuration of a conventional high resistance cell for low voltage operation SRAM.

[Explanation of symbols]

 1 input terminal 2 output terminal 3 high potential side power supply (VCC) 4 low potential side power supply (GND) 5, 12 first NPN bipolar 6, 14 second NPN bipolar 7, 13, 51, 52, 59 PMOS 8, 15 First NMOS 9, 15 Second NMOS 10 Resistance element 11 Boosted potential (VCHGB) 16, 30 Internal boosted potential generation circuit 21 First inverter 22 Second inverter 23 Cell 24 Word line drive buffer 25 Boosted potential ( VCHGW) 26, 27, 28, 29, 53, 54, 60 NMOS 41, 45 Detection element 42, 46 Low current source 43, 47 Differential amplifier 44, 48 Comparison result output terminal 50 Comparison result input terminal 55 Inverter string high potential Side power supply line 56 Inverter row low potential side power supply line 57 Inverter 58 Pumping pulse output terminal 61, 62 Node 63 Charge pump circuit 64 Ring oscillator

Claims (10)

[Claims] 1. A semiconductor device in which a logic circuit is composed of MOS transistors, and an output of the logic circuit is input to a bipolar transistor in an output stage and an output is taken out from the bipolar transistor, the first device being supplied to the bipolar transistor. Of the second high-potential-side power supply, the boosted-potential generation means supplies a potential higher than that of the high-potential-side power supply of the second high-potential-side power supply of the MOS transistor. From the second high-potential-side power supply, the charge pump circuit is feedback-controlled on the basis of the output of the differential amplification means to feedback-control the charge pump circuit. The potential of the high-potential side power source is set to the first
The semiconductor device is controlled so as to be kept higher than the high-potential-side power source by the predetermined potential. 2. The semiconductor device according to claim 1, wherein the predetermined potential is controlled to be substantially equal to the base-collector voltage immediately before the output stage bipolar transistor is saturated. 3. The bipolar transistor of the output stage, wherein the boosted potential generating means is inserted in a diode type connection between the second high potential side power source and one input end of the differential amplifying means. A second bipolar transistor of the same type as the transistor is provided, and a predetermined current is caused to flow from the constant current source from the second high potential side power supply line side through the second bipolar transistor. Item 1. The semiconductor device according to item 1. 4. A first connection wherein a collector is connected to a first high-potential-side power supply supplied from the outside and an emitter is connected to an output terminal.
A NPN bipolar transistor, and a second NPN bipolar transistor having a collector connected to the output terminal and an emitter connected to a low-potential-side power supply; and a push-pull type buffer, and the first and second NPN bipolar transistors. A plurality of MOS transistors for driving the base of the power source, and an internal boosted potential generation circuit that generates a boosted potential higher than the first high-potential-side power supply as a second high-potential-side power supply. A BiCMOS semiconductor integrated circuit in which a source or drain terminal of a MOS transistor for charging and driving the base of the first NPN bipolar transistor is connected to the second high-potential-side power supply supplied by a potential generation circuit. The internal boosted potential generation circuit connects the anode to the second high potential side power supply , PN to and formed by connecting the cathode to the low potential side power source via the constant current source
At least a diode, and a differential amplifier in which the first high-potential-side power source and the cathode of the PN diode are connected to differential input terminals respectively, and a pulse is switched according to an output result of the differential amplifier. A semiconductor device characterized in that the means for charging the capacitor to generate the internal boosted potential is feedback-controlled. 5. An NP having a collector connected to a first high-potential-side power supply supplied from the outside and an emitter connected to an output terminal.
An N-bipolar transistor, a load driving circuit in which the source terminal and the drain terminal of one or more MOS transistors are connected in series or in parallel between the output terminal and the low-potential-side power supply, respectively, and the NPN bipolar transistor. A plurality of MOS transistors that drive the base of the second high-potential power supply, and an internal boosted potential higher than that of the first high-potential-side power supply.
An internal boosted potential generating circuit for generating a high-potential-side power source of the above, and a MOS transistor for charging and driving the base of the NPN bipolar transistor to the second high-potential-side power source supplied by the internal boosted potential generating circuit. A BiNMOS semiconductor integrated circuit having source and drain terminals connected to each other, wherein the internal boosted potential generation circuit has an anode connected to the second high-potential-side power supply, and a cathode connected to a low potential via a constant current source. PN connected to the side power supply
At least a diode, and a differential amplifier in which the first high-potential-side power source and the cathode of the PN diode are connected to differential input terminals respectively, and a pulse is switched according to an output result of the differential amplifier. A semiconductor device characterized in that the means for charging the capacitor to generate the internal boosted potential is feedback-controlled. 6. A memory cell having a flip-flop type structure comprising two inverters cross-connected to each other,
The inverter comprises a load element and a MOS transistor connected in series between a first high potential side power source and a low potential side power source, and is inserted between the two inverters and a bit line, respectively. In a semiconductor memory device comprising a plurality of memory cells including two word transistors whose gates are both connected to a common word line, a potential higher than a potential of the first high potential side power supply is set to a second high potential side. The boosted potential generating means for outputting as the potential of the power supply and the high level of the word line are set to the potential of the second high potential side power supply, which is supplied by the boosted potential generating means during both the writing and reading operations. A word line driving means, wherein the boosted potential generating means drops a predetermined potential from the potential of the second high potential side power source and the potential of the first high potential side power source. And a potential difference between the second high-potential-side power supply and the second high-potential-side power supply by controlling the feedback of the charge pump circuit based on the differential amplification output. Also, the semiconductor device is controlled so as to be kept higher by the predetermined potential. 7. A first and a second inverter, each of which comprises a driver MOS transistor and a load element of the driver MOS transistor, and which are cross-connected to each other, and storage nodes of the first and second inverters. A first and a second word transistor connected between the bit line pair and having gates respectively connected to the word line, and connected between the first high potential side power source and the low potential side power source And a word line drive circuit that drives the word line, and an internal boosted potential generation that outputs a potential higher than the potential of the first high-potential-side power supply as the potential of the second high-potential-side power supply. A word line driving circuit, the word line driving circuit supplies the word line to a potential of the second high-potential-side power supply, which is supplied by the internal boosted potential generating circuit during both writing and reading operations. Of the internal boosted potential generation circuit, the gate and the drain of which are connected to the second high potential side power supply, and the source of which is connected to the low potential side power supply via a constant current source. And a third MOS transistor connected to the second MOS transistor, the third MOS transistor having the same conductivity type as the first and second word transistors, and the first high-potential-side power supply. A differential amplifier having the source of the third MOS transistor as an input; and a feedback control of a means for switching a pulse by the output of the differential amplifier to charge a capacitor to generate an internal boosted potential. A semiconductor device characterized by the above. 8. The potential of the first high-potential-side power supply is approximately 2.5 V
The following low voltage is used:
5. The semiconductor device according to any one of 5, 6, and 7. 9. The semiconductor device according to claim 1, wherein the predetermined potential is approximately 0.6V. 10. The boosting means variably controls the oscillation frequency of an oscillator that outputs a pumping pulse based on the output of the differential amplifying means, or stops the oscillation of the oscillator.
7. The semiconductor device according to claim 1, wherein the semiconductor device is configured to control restart.