JPH0973726A - Device and method for signal processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily reduce an error rate for reproduced data caused by a difference of a recording medium or the like. SOLUTION: An equalizer 1 equalizes the waveform of the reproducing signal of an optical disk or the like by using a specified parameter set in its inside and outputs an equalizer output signal. An equalizing error detecting circuit 2 detects the jitters of the equalizer output signal as an equalizing error and supplies this equalizing error to a equalizer control circuit 3. The equalizer control circuit 3 controls the specified parameter set in the equalizer 1 so as to reduce the supplied equalizing error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus and a signal processing method, and more particularly to a signal processing apparatus for reducing the error rate of reproduced data by minimizing the jitter of an equalizer output signal. And a signal processing method.

[0002]

2. Description of the Related Art A digital signal reproducing apparatus is a disk reproducing apparatus for reproducing a recording medium such as an optical disk or a magnetic disk, a reproducing apparatus for reproducing a digital signal transmitted through a communication transmission line, and a video tape. There is a digital video tape recorder (VTR) or the like. When a digital signal is reproduced from a medium by this digital signal reproducing apparatus, band limitation limits the characteristics of the low frequency part and the high frequency part of the reproduced signal, so-called intersymbol interference occurs, and the error rate of the reproduced data deteriorates. It may happen.

Therefore, conventionally, an equalizer (waveform equalizer) is provided in the reproducing apparatus to equalize the waveform of the reproduced signal, suppress intersymbol interference of the reproduced signal, and reduce the error rate of the reproduced data. I am trying.

In the equalizer described above,
Although a predetermined parameter (for example, a mix ratio in a 3-tap equalizer) is set, if this parameter is fixed, waveform equalization may occur due to changes over time in the playback device, quality variations, etc. The frequency characteristic of the equalizer output thus obtained may be different from the desired one (that is, the frequency characteristic of the equalizer output may be deteriorated).

Therefore, in the case where the reproducing device changes with time, variations in quality, etc., an automatic equalizer that changes the above parameters so that the frequency characteristic of the equalizer output is always in an optimum state is provided. Are known.

FIG. 12 is a block diagram showing a configuration example of a conventional automatic equalizer. When the equalizer 100 having predetermined parameters set therein receives a reproduction signal of digital data recorded on a recording medium (for example, a magneto-optical disk), the equalizer 100 equalizes the waveform of the reproduction signal. And outputs it to the comparator 101 and the delay circuit 103.

The comparator 101 binarizes the output signal of the equalizer, outputs the binarized data to a circuit (not shown) as reproduced data, and also outputs a target waveform calculation circuit 102.
To supply.

The target waveform calculation circuit 102 includes a comparator 101.
A waveform (target waveform) when the output of the equalizer has a desired frequency characteristic is calculated from the binarized data by and is output to the equalization error calculation circuit 104. At this time,
The equalizer output signal corresponding to the signal output from the target waveform calculation circuit 102 is delayed by the delay circuit 103 for a predetermined time and then supplied to the equalization error calculation circuit 104.

The equalization error calculation circuit 104 compares the waveforms of these two signals (equalizer output signal and target waveform signal), detects the difference (equalization error), and the equalizer control circuit. 10
5 is output. The equalizer control circuit 105 controls the values of the parameters set in the equalizer 100 so as to reduce the input equalization error.

As described above, the change with time of the reproducing apparatus,
Even when quality variations occur, the frequency characteristics of the equalizer output signal can be set to the optimum state.

[0011]

The frequency characteristics of the signal component and noise component of the reproduced signal greatly differ depending on the recording medium, the recording density of the data recorded on the recording medium, the data modulation method, and the like. Therefore, it becomes necessary to set the frequency characteristic of the target waveform of the equalizer output calculated by the target waveform calculation circuit 102 in accordance with the difference in the recording medium.

However, in the conventional automatic equalizer shown in FIG. 12, unless the characteristics of the reproduced signal input to the equalizer 100 are limited to some extent, the equalizer output signal output from the equalizer 100 is There is a problem that it is difficult to optimally set the characteristics.

The present invention has been made in view of such a situation, and an object thereof is to easily reduce an error rate of reproduced data due to a difference in recording medium and the like.

[0014]

A signal processing apparatus according to claim 1 comprises: an equalizing means for equalizing the waveform of an input signal; and a detecting means for detecting a jitter of an equalized signal output from the equalizing means. And a control means for controlling the equalization means in accordance with the detection result of the detection means.

The signal processing method according to claim 6 equalizes the waveform of the input signal, outputs the equalized signal, detects the jitter of the equalized signal, and detects the jitter of the equalized signal. It is characterized by controlling the waveform equalization processing of.

In the signal processing device according to the first aspect of the present invention, the equalizing means equalizes the waveform of the input signal, and the detecting means detects the jitter of the equalized signal output from the equalizing means.
The control means controls the equalization means according to the detection result of the detection means.

In the signal processing method according to the sixth aspect, the waveform of the input signal is equalized, the equalized signal is output, the jitter of the equalized signal is detected, and the input signal is input according to the jitter detection result. Controls the signal waveform equalization process.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings, but before that, the correspondence between each means of the invention described in the claims and the following embodiments will be clarified. In order to achieve the above, a corresponding embodiment (however, one example) is added in parentheses after each means, and the features of the present invention will be described as follows.

The signal processing apparatus according to claim 1 is equalization means for equalizing the waveform of an input signal (for example, the equalizer 1 in FIG. 1).
A detection means for detecting the jitter of the equalized signal output from the equalization means (for example, the equalization error detection circuit 2 in FIG. 1), and a control means for controlling the equalization means in accordance with the detection result of the detection means ( For example, the equalizer control circuit 3) of FIG. 1 is provided.

According to another aspect of the signal processing apparatus of the present invention, the detecting means includes sampling means (for example, the A / D converter 10 in FIG. 6) for sampling the level of the equalized signal output from the equalizing means at a predetermined timing. , At a timing before and after the zero-cross point of the equalized signal, a sum calculation means (for example, calculation circuit 13B, zero-cross detection circuit 12, switch 17 in FIG. 6) for calculating the sum of two sampling values sampled by the sampling means, It is characterized by comprising a calculation means (for example, the time average calculation circuit 18 in FIG. 6) for calculating the time average of the sum.

In the signal processing device according to the third aspect of the present invention, the detection means samples the sampling means 2 at the timings before and after the zero-cross point of the equalized signal.
Difference calculation means (for example, the calculation circuit 14B, the zero-cross detection circuit 12 and the switch 17 in FIG. 4) that calculates the difference between two sampling values, and a normalization means that normalizes the sum by dividing it by the difference (for example, the normalization in FIG. 4). 15) is further provided.

In the signal processing device according to the fourth aspect, the detecting means further includes a square calculating means (for example, the arithmetic circuit 16 in FIG. 3) for calculating the square of the output of the normalizing means, and the calculating means (for example, FIG. 3). The time average calculation circuit 18) of 1 calculates the time average of the output of the square calculation means.

In the signal processing device according to the fifth aspect, the detecting means calculates the time average value of each of the sum and the difference (for example, the time average calculating circuits 18A and 18 in FIG. 5).
B) is further provided, and the normalizing means is characterized by dividing the time average of the sum by the time average of the difference.

Note that, of course, this description does not mean that each means is limited to those described above.

FIG. 1 is a block diagram showing the outline of an automatic equalizer to which the present invention is applied. When the equalizer 1 having predetermined parameters set therein receives a reproduction signal of a magneto-optical disk or the like, the equalizer 1 equalizes the waveform of the reproduction signal,
It is designed to be output as an equalizer output signal. This output is supplied to a not-shown binarization circuit in the subsequent stage and binarized with the 0 level as a threshold. The equalization error detection circuit 2 is
A value corresponding to the jitter of the equalizer output signal output from the equalizer 1 is detected as an equalization error, and the equalization error is output to the equalizer control circuit 3.

The equalizer control circuit 3 includes an equalization error detection circuit 2
The parameters set in the equalizer 1 are controlled so as to reduce the equalization error supplied from (to minimize the jitter).

Next, the principle of equalization error detection according to this embodiment will be described with reference to FIG. FIG. 2 is a diagram showing the waveform of the equalizer output signal output from the equalizer 1.

There is a strong correlation between the jitter of the output signal of the equalizer and the error rate of the reproduced data, and the error rate of the reproduced data can be reduced by reducing the jitter of the output signal of the equalizer. .

For example, in FIG. 2, a time T _{Z at} which the zero-crossing of the equalizer output signal occurs is a time T _X (= T ₁ (T ₁ or T ₂ ) which is an intermediate point between the data sampling timings (time T ₁ and T ₂ ) before and after that.
The closer to (T ₁ + T ₂ ) / 2), the higher the reliability of reproduced data (that is, the smaller the error rate). That is, the jitter of the equalizer output signal is the time T _{Z at} which the equalizer output signal zero-crosses (the signal level of the equalizer output signal changes from positive to negative (or negative to positive)) and the time Data sampling timing before and after T _Z (time T ₁ , T ₂ )
It is represented by the variance of the time difference | T _X −T _Z | from the time T _{X in} the middle of, and the error rate of the reproduced data can be reduced by reducing this jitter value.

Assuming that the equalizer output signal changes linearly (in a linear function) in the vicinity of the zero-cross point, the jitter value of the equalizer output signal is the time T.
The signal level A of the equalizer output signal at ₁ and the time T ₂
In proportion to the intermediate level of the signal level B (hereinafter referred to as intermediate level) C ′ (= (A + B) / 2). That is, under the above assumption, time T _X (time T
The signal level of the equalizer output signal at an intermediate time between ₁ and T ₂ ) is an intermediate level C ′, and the intermediate level C ′ is 0.
, The time T _Z at which the equalizer output signal crosses zero
Coincides with time T _X. Therefore, the jitter can be reduced by reducing the size of the intermediate level C ′, and the error rate of the reproduced data can be reduced.

The equalization error detection circuit 2 of this embodiment shown in FIG. 3 is constructed based on the above principle. In the equalization error detection circuit 2, the A / D converter 10 outputs the equalizer output signal (eg, the equalizer output signal output from the equalizer 1 in FIG.
The equalizer output signal shown in FIG. 2) is sampled at a predetermined time of a fixed cycle (for example, data sampling timing T ₁ , T ₂ , T ₃ , ... Shown in FIG. 2). .

The signal level of the equalizer output signal sampled at a predetermined time by the A / D converter 10 is 1 sample delay 11 and zero cross detection circuit 1.
2, supplied to the arithmetic circuits 13A and 14A. The 1-sample delay 11 delays the signal level of the supplied equalizer output signal by 1 sample, and the zero-cross detection circuit 1
2, the arithmetic circuit 13A and the arithmetic circuit 14A.

That is, the zero-cross detection circuit 12, the arithmetic circuit 13A and the arithmetic circuit 14A are simultaneously supplied with the signal levels A and B of the two equalizer output signals at two consecutive data sampling timings.

The arithmetic circuit 13A calculates the sum (A + B) of the signal levels A and B of the two input equalizer output signals, and uses that value as the above-mentioned intermediate level value (described later).
It is adapted to be supplied to the normalizer 15. The arithmetic circuit 14A calculates the difference (AB) between the signal levels A and B of the two input equalizer output signals, and supplies the calculated value to the normalizer 15 as a normalized value. Has been done.

The normalizer 15 uses the intermediate level value (that is, the sum (A + B) of the two signal level values) supplied from the arithmetic circuit 13A as the normalized value (that is, two values) supplied from the arithmetic circuit 14A. Signal level value difference (AB))
Normalize by dividing by the value ((A + B)
/ (AB)) is supplied to the arithmetic circuit 16.

The arithmetic circuit 16 determines the magnitude of the value supplied from the normalizer 15 by squaring the value ((A +
B) / (A-B)) ² is calculated and output. A switch 17 is provided at a connection point between the arithmetic circuit 16 and the time average calculation circuit 18, and the switch 17 is controlled by the zero cross detection circuit 12.

When the time average calculation circuit 18 receives the value output from the arithmetic circuit 16, the time average calculation circuit 18 calculates the time average of the values and uses the time average value as an equalization error to show the equalizer shown in FIG. The output is provided to the control circuit 3.

Next, the operation of the automatic equalizer of this embodiment will be described. When the equalizer 1 receives a reproduction signal of a magneto-optical disk, the equalizer 1 equalizes the waveform of the reproduction signal,
The equalizer output signal shown in FIG. 2 is output. The equalizer output signal output from the equalizer 1 is A / A of the equalization error detection circuit 2.
It is input to the D converter 10.

Upon receiving the input of the equalizer output signal shown in FIG. 2, the A / D converter 10 samples the equalizer output signal at the data sampling timings T ₁ , T ₂ , .... , Output the sampled signal level.

That is, the A / D converter 10 samples the equalizer output signal at time T ₁ and outputs a sampling value A (> 0). Further, at time T ₂ which is the next data sampling timing, A /
The D converter 10 samples the equalizer output signal and outputs a sampling value B (<0).

The sampling values A and B of the equalizer output signal sampled by the A / D converter 10 are arranged in the order of their data sampling timings, respectively, a 1-sample delay 11, a zero-cross detection circuit 12, an arithmetic circuit 13A and an arithmetic circuit. 14A. The 1-sample delay 11 delays the sampling value supplied from the A / D converter 10 by 1 sample and outputs it to the zero-cross detection circuit 12, the arithmetic circuits 13A and 14A (that is, the sampling value A at time T ₁ ). At time T ₂
To output).

Therefore, the sampling value B output from the A / D converter 10 and the sampling value A delayed by the one-sample delay 11 are input to the zero-cross detection circuit 12 and the arithmetic circuits 13A and 14 at the same time. .

The output signal of the equalizer is assumed to change linearly (in a linear function) in the vicinity of the zero-cross point,
The arithmetic circuit 13A has an intermediate level C (= A + B) between the sampling value A and the sampling value B (correctly, the intermediate level value is represented by (A + B) / 2 (= C ′), and the predetermined value is set to that value. The value obtained by multiplying the coefficient (= 2) corresponds to the intermediate level, and in this specification, A + B (= C) will be described as the intermediate level).

The arithmetic circuit 14A also uses a normalization value D (= A- used to normalize the intermediate level value C).
B) (that is, the level change value of the sampling value when changing from time T ₁ to time T ₂ ) is calculated.

Then, an intermediate level value C between the sampling value A at time T _{1 and} the sampling value B at time T ₂ calculated by the arithmetic circuit 13A, and the arithmetic circuit 14A.
The normalized value D calculated in ( ₁ ) (the level change value of the sampling value when changing from time T ₁ to time T ₂ ) is input to the normalizer 15. The normalizer 15 determines the intermediate level value C
Is normalized by dividing it by a normalized value D, and the value (C / D) is output to the arithmetic circuit 16.

The arithmetic circuit 16 receives the input value (C / D)
In order to obtain the magnitude of ((C / D) may be a negative value), a value (C / D) ² obtained by squaring the value is calculated. The time average value of this value (C / D) ² is proportional to the square of the jitter value. In addition to the above reason, if the jitter is assumed to be Gaussian distributed, the most appropriate reason for obtaining the square of (C / D) is to obtain the square of (C / D) and use that value. There is also a reason that an evaluation can be done.

By the way, the equalizer output signal has two consecutive
When zero crossing is not performed between two data sampling timings (for example, between times T _{2 and} T ₃ in FIG. 2), the time average value of the values obtained by the above processing is not proportional to the square of the jitter value (that is, in this case). In, the value obtained by the above treatment has no meaning). Therefore,
The zero-cross detection circuit 12 detects the zero-cross point of the equalizer output signal, and outputs the value calculated by the arithmetic circuit 16 to the time only when the equalizer output signal zero-crosses between two consecutive data sampling timings. Average calculation circuit 1
The on / off of the switch 17 is controlled so that the switch 17 is supplied to the switch 8.

That is, the zero-cross detection circuit 12 detects the sign of the sampling values at the two input data sampling timings, and if the signs are different, the equalizer is provided between the two data sampling timings. The switch 17 is turned on when it is determined that the output signal has crossed zero. On the other hand, when the signs of both are the same, it is determined that the equalizer output signal does not cross zero at the two data sampling timings, and the switch 1
Turn off 7.

For example, when the sampling values A and B are input to the zero-cross detection circuit 12, the signs of the zero-cross detection circuit 12 are different (the sign of the sampling value A is positive and the sign of the sampling value B is negative). Is detected), it is determined that the equalizer output signal has a zero cross between times T _{1 and} T ₂ , and the switch 17 is turned on. At this time,
The value (C / D) ² calculated by the arithmetic circuit 16 is supplied to the time average calculation circuit 18.

On the other hand, for example, when the sampling values B and E (the sampling values at time T ₃ ) are input to the zero-cross detection circuit 12, the zero-cross detection circuit 12 has the same sign (the signs of the samplings B and E are the same). It is determined that both are negative), and it is determined that the equalizer output signal does not cross zero between times T _{2 and} T ₃ , and the switch 17 is turned off. At this time, the value calculated by the arithmetic circuit 16 is not supplied to the time average calculation circuit 18.

The time average calculation circuit 18 is composed of a low-pass filter, a median filter, etc., and calculates the time average value (value proportional to the square of the jitter value) of the values supplied from the arithmetic circuit 16 to obtain the equalization error as Output to the equalizer control circuit 3 shown in FIG.

The equalizer control circuit 3 includes the equalization error detection circuit 2
Equalizer 1 to minimize the equalization error supplied by
Controls the value of the parameter set to. By doing so, the jitter of the equalizer output output from the equalizer 1 can be reduced to almost the minimum.

In the above embodiment, the equalizer 1 is controlled so that the value proportional to the jitter of the output of the equalizer is minimized, so that it corresponds to the difference in the recording medium, the recording density and the like. It is possible to easily reduce the error rate of the reproduced data to almost the minimum regardless of the difference in the frequency characteristic of the reproduced signal.

In the embodiment described above, the arithmetic circuit 16
However, in order to obtain the magnitude of the value calculated up to the preceding stage, the square of the value is calculated, but it is also possible to calculate the equalization error without providing the arithmetic circuit 16. If so, an embodiment thereof will be described with reference to FIG.

The configuration of the equalization error detection circuit 2 of the embodiment shown in FIG. 4 is basically the same as the configuration of the equalization error detection circuit 2 shown in FIG. 3, and instead of the operation circuits 13A and 14A, the operation circuit. 13B and 14B are provided, and the arithmetic circuit 16 is removed.

In the equalization error detection circuit 2 of the present embodiment, the arithmetic circuit 13B calculates the intermediate level value of the sampling values at two consecutive times, similarly to the arithmetic circuit 13A shown in FIG. The absolute value of the intermediate level value is calculated. For example, the arithmetic circuit 13B is configured to operate at the time T
Absolute value C (= | A + B |) of the intermediate level value between the sampling value A at ₁ and the sampling value B at time T ₂ .
Is calculated.

The arithmetic circuit 14B is also the arithmetic circuit 13B.
Similarly, the absolute value of the value obtained by the arithmetic circuit 14A shown in FIG. 3 is calculated as a normalized value D (= | AB |).

In the present embodiment, since the values calculated by the arithmetic circuits 13B and 14B are the values representing the magnitudes (that is, positive values), the arithmetic circuit shown in the embodiment of FIG. It is not necessary to provide 16. In this embodiment, the time average value of the value (C / D) (for example, | A + B | / | AB |) calculated by the normalizer 15 is proportional to the jitter value, and this value is equalized. The error is output to the equalizer control circuit 3 in FIG.

The equalizer error detection circuit 2 may have another configuration. FIG. 5 is a block diagram showing the configuration of another embodiment of the equalization error detection circuit 2 of FIG. The configuration of the equalization error detection circuit 2 of this embodiment is basically the same as the configuration of the equalization error detection circuit 2 shown in FIG. 4, except for the following parts.

That is, the equalization error detection circuit 2 of the present embodiment.
In, between the arithmetic circuit 13B and the normalizer 15,
The switch 17A and the time average calculation circuit 18A are provided in order, and similarly, the arithmetic circuit 14B and the normalizer 15 are provided.
Between the switch 17B and the time average calculation circuit 18B.
Are provided in order. Switches 17A and 17B
The zero cross detection circuit 12 controls ON and OFF of each of the above.

In the equalization error detection circuit 2 of this embodiment, the time average calculation circuit 18A calculates the time average value C ″ of the intermediate level values | A + B | (= C) calculated by the arithmetic circuit 13B.
Is calculated and output to the normalizer 15. Similarly, the time average calculation circuit 18B calculates the normalized value |
The time average value D ″ of AB − (= D) is calculated and output to the normalizer 15.

The normalizer 15 normalizes by dividing the time average value C ″ of the intermediate level value by the time average value D ″ of the normalized value, and the value (C ″ / D ″). Is output as an equalization error.

In this embodiment, since the division processing (division processing in the normalizer 15) which generally requires a long processing time is performed after the time averaging processing, the processing speed is increased. Can be achieved.

Further, even when the characteristic of the equalizer is changed, if the time average value of | AB is considered to be substantially constant, sampling of the equalizer output signal at two data sampling timings is performed. The time average value of the magnitude of the intermediate level of the values (for example, | A + B |) can be treated as an equalization error without normalization. FIG. 6 is a block diagram showing the configuration of an embodiment of the equalization error detection circuit 2 in this case.

In the equalization error detection circuit 2 of this embodiment, the arithmetic circuit 14B of the equalization error detection circuit 2 shown in FIG.
The switch 17B, the time average calculation circuit 18B, and the normalizer 15 are removed, and the time average value of the intermediate level values | A + B | calculated by the arithmetic circuit 13B is output as an equalization error.

In this embodiment, division processing (for example,
Since the division process in the normalizer 15 in FIG. 5 is not performed, it is possible to further speed up the equalization error detection process.

By utilizing the principle of the automatic equalizer described above, the following automatic equalizer can be constructed.

FIG. 7 is a block diagram showing the configuration of an embodiment of an automatic equalizer to which the present invention is applied. In the automatic equalizer of this embodiment, a reproduction signal obtained by reproducing a magneto-optical disk or the like is input to the three 3-tap equalizers 30 to 32. The 3-tap equalizer 30 equalizes the signal waveform of the reproduction signal using the mix ratio k set therein and outputs it as an equalizer output signal (waveform-equalized reproduction data). Has been done.

The 3-tap equalizer 31 uses the mix ratio k + δ set therein (a mix ratio slightly larger than the mix ratio k set in the 3-tap equalizer 30) to generate 3 taps. Similar to the equalizer 30, it equalizes the signal waveform of the reproduction signal and outputs an equalizer output signal for equalization error detection.

The 3-tap equalizer 32 uses a mix ratio k−δ set therein (a mix ratio slightly smaller than the mix ratio k set in the 3-tap equalizer 30), Similar to the 3-tap equalizer 30, the signal waveform of the reproduction signal is equalized and an equalizer output signal for equalization error detection is output.

The equalization error detection circuit 2A has the same configuration as that of the equalization error detection circuit 2 shown in any of FIGS. 3 to 6, and the equalization error supplied from the 3-tap equalizer 31. The equalization error Ep is detected based on the output signal of the equalizer for detection, and is output to the inverting circuit 33.

The inverting circuit 33 multiplies the equalization error Ep supplied from the equalization error detection circuit 2A by -1 to invert it, and outputs the inverted equalization error -Ep to the adder 34. ing.

The equalization error detection circuit 2B has the same configuration as the equalization error detection circuit 2A, and is a 3-tap equalizer 32.
The equalization error En is detected on the basis of the equalizer output signal for detecting the equalization error, which is supplied to the adder 34.

The adder 34 has an inverted equalization error -Ep.
And the equalization error En are added, and the added value (En-E
p) is output to the equalizer control circuit 35.

The equalizer control circuit 35 controls the value of the mix ratio "k" set in the 3-tap equalizers 30 to 32 in accordance with the value supplied from the adder 34. ing.

FIG. 8 is a block diagram showing an example of the internal structure of the 3-tap equalizer 30 shown in FIG. In the 3-tap equalizer 30, the inverting attenuation circuit 50 uses the reproduction signal with a predetermined constant −k (a constant obtained by multiplying the mix ratio k by −1).
Is multiplied and is inverted and attenuated, and the signal is output to the adder 54 as the signal X.

The delay circuit 51 outputs the reproduced signal for a predetermined time T
_The delayed reproduction signal is delayed by _F and is output to the adder 54 as the signal Y. The reproduction signal delayed by the delay circuit 51 is also supplied to the delay circuit 52, where the reproduction signal is further delayed for a predetermined time T _F (delay circuit 5).
It is delayed by the same time as the delay time in 1) and supplied to the inverting attenuation circuit 53.

The inverting attenuator circuit 53 includes delay circuits 51 and 5
2, the reproduction signal delayed by a predetermined time 2 · T _F is multiplied by a predetermined constant −k (a constant obtained by multiplying the mix ratio k by −1) to invert and attenuate, and the signal is added as a signal Z to an adder. It is designed to output to 54.

The adder 54 receives the three input signals X,
Y and Z are added to equalize the waveform of the reproduction signal and output the equalizer output signal. That is, the signal waveform of the reproduction signal is equalized by setting the predetermined constants set in the inverting attenuation circuits 50 and 53 to appropriate values.

The configuration of the 3-tap equalizers 31 and 32 shown in FIG. 7 is basically the same as the configuration of the 3-tap equalizer 30 shown in FIG. 8 and is set in the inverting attenuation circuits 50 and 53. The constants (constants obtained by multiplying each mix ratio by -1) are different.

That is, in the 3-tap equalizer 31, the predetermined constant set in the inverting attenuation circuits 50 and 53 is-(k + δ), and in the 3-tap equalizer 32, the inverting attenuation circuits 50 and 53. The predetermined constant set to is − (k−δ).

Next, the operation of the automatic equalizer of this embodiment will be described. When the reproduction signal obtained by reproducing the magneto-optical disk is supplied to the 3-tap equalizers 30 to 32, the 3-tap equalizers 30 to 32 have predetermined constants (-1 for each mix ratio). Is used to perform waveform equalization of the reproduction signal. The equalizer output signal waveform-equalized by the 3-tap equalizer 30 (reproduced data waveform-equalized) is output to the outside. Further, the equalizer error detection equalizer output signals waveform-equalized by the 3-tap equalizers 31 and 32 are equalized error detection circuits 2A and 2 respectively.
B.

The equalization error detection circuit 2A uses the above-mentioned value corresponding to the jitter value as an equalization error based on the equalizer output signal for equalization error detection supplied from the 3-tap equalizer 31. The equalization error detection process for detecting is performed, and the equalization error Ep is output to the inverting circuit 33. The inverting circuit 33 has an equalization error Ep.
Is multiplied by -1 to invert, and the inverted equalization error -Ep is supplied to the adder 34.

The equalization error detection circuit 2B performs the same equalization error detection processing as the equalization error detection circuit 2A on the basis of the equalizer output signal for equalization error detection supplied from the 3-tap equalizer 32. And supplies the equalization error En to the adder 34.

The adder 34 has the inverted equalization error -Ep.
And the equalization error En are added, and the added value (En-E
p) is supplied to the equalizer control circuit 35.

When En-Ep is a positive value (that is, the equalization error waveform-equalized by the mixing ratio k-δ which is slightly smaller (smaller by δ) than the mixing ratio k of the 3-tap equalizer 30). Equalization error En based on the output signal of the equalizer for detection is equalized to a waveform equalized by a mix ratio k + δ that is slightly larger (by δ) than the mix ratio k of the 3-tap equalizer 30. (Equalization error Ep based on the equalizer output signal of 1), the equalizer control circuit 35 sets the mix set in the 3-tap equalizer 30 that outputs the equalizer output signal (reproduction data). It is determined that the ratio k is smaller than a desired value, and the 3-tap equalizers 30 to 32 are controlled so as to increase the value of k.

On the other hand, when En-Ep has a negative value (that is, waveform equalization is performed by a mix ratio k-δ that is slightly smaller (smaller by δ) than the mix ratio k of the 3-tap equalizer 30). The equalization error En based on the equalizer output signal for equalization error detection is equal to the mix ratio k of the 3-tap equalizer 30.
Slightly larger than (by δ) the mix ratio k +
If it is smaller than the equalization error Ep based on the equalizer output signal for equalization error detection that is waveform equalized by δ), the equalizer control circuit 35 sets the mix set in the 3-tap equalizer 30. It is determined that the ratio k is larger than a desired value, and the 3-tap equalizers 30 to 32 are controlled so as to reduce the value of k.

When En-Ep is substantially equal to 0 (that is, the equalization error waveform-equalized by the mixing ratio k-δ which is slightly smaller (smaller by δ) than the mixing ratio of the 3-tap equalizer 30). The equalization error En based on the output signal of the equalizer for detection and the mix ratio k that is slightly larger (larger by δ) than the mix ratio k of the 3-tap equalizer 30.
If the equalization error Ep based on the equalizer output signal for detecting the equalization error waveform equalized by + δ has almost the same value), the equalizer control circuit 35 causes the 3-tap equalizer 30 to operate. It is determined that the set mix ratio k is almost the desired value, and the value of k is not changed.

FIG. 9 shows the relationship between the equalization error of the equalizer output signal waveform-equalized by the automatic equalizer of this embodiment and the mix ratio k set in the 3-tap equalizer 30. It is a figure explaining. Note that, in FIG. 9, the line connecting the black squares indicates the case where the equalization error detecting circuit 2 shown in FIG. 5 is used for the equalization error detecting circuits 2A and 2B, and the line connecting the black circles indicates the same. The case where the equalization error detection circuit 2 shown in FIG. 6 is used for the equalization error detection circuits 2A and 2B is shown.

In this embodiment, no matter which of the equalization error detection circuits 2 shown in FIGS. 5 and 6 is used as the equalization error detection circuits 2A and 2B, the mix for minimizing the equalization error is used. The ratio k is about 0.3.

FIG. 10 shows an equalizer output signal (reproduced data).
FIG. 6 is a diagram for explaining the relationship between the bit error rate of and the mix ratio k set in the 3-tap equalizer 30. As is clear from this figure, the bit error rate becomes the minimum when the mix ratio is 0.3, which minimizes the equalization error.

Therefore, the equalization error based on the jitter of the equalizer output signal is detected, and the mix ratio k is set so as to minimize the equalization error (in the case of this embodiment, the mix ratio k is By setting 0.3), the error rate of the equalizer output signal output from the 3-tap equalizer 30 can be minimized.

In the present embodiment, the waveform equalization of the reproduced signal is performed using the 3-tap equalizer, but the present invention is not limited to this, and equalizers having other configurations may be used. Often,
FIG. 11 shows a configuration example of another equalizer.

The equalizer shown in FIG. 11 is a distortion of a reproduction signal generated when the optical disc set in the optical disc reproducing device has an inclination in the tangential direction (has a tangential skew). An equalizer for unbalance correction that corrects (asymmetry of rising and falling of signal waveform of reproduced signal).

The structure of this unbalance correction equalizer is as follows.
The configuration is basically the same as that of the 3-tap equalizer shown in FIG. 8, and switches 61 and 62 are provided in front of the inverting attenuation circuits 50 and 53, respectively. The switches 61 and 62 are on / off controlled by the value of the mix ratio k set in the inverting attenuation circuits 50 and 53.

The mix ratio k set in the inverting attenuation circuits 50 and 53 of this unbalance correction equalizer.
Is a value corresponding to the tangential skew of the optical disc, and the value is controlled by the equalizer control circuit 35 in FIG.

For example, when the equalizer output signal has an equalization error due to the tangential skew of the optical disc, the mix set in the inverting attenuation circuits 50 and 53 is controlled by the equalizer control circuit 35 in FIG. The value of the ratio k changes. At this time, when the mix ratio k is smaller than 0, the switch 61 is turned on and the switch 62 is turned off. On the other hand, when the mix ratio k is larger than 0, the switch 62 is turned on and the switch 61 is turned off.

When there is no tangential skew of the optical disc, the equalizer output signal has no equalization error, and the equalizer control circuit 35 sets the mix ratio k to 0.
At this time, both the switches 61 and 62 are turned off.

By doing so, it is possible to correct the distortion of the reproduction signal caused by the tangential skew of the optical disc.

In the above embodiment, the value corresponding to the jitter of the equalizer output signal output from the equalizer is detected as the equalization error, and the equalizer is minimized to minimize the equalization error. Although the predetermined parameter set in the above is controlled, the present invention is not limited to this, and the predetermined parameter set in the equalizer is changed by using a microcomputer or the like, and each parameter value is changed. The equalization error may be evaluated and a parameter value that minimizes the equalization error may be set.

[0101]

As described above, according to the signal processing device and the signal processing method of the present invention, the jitter of the equalized signal is detected,
Since the equalization is controlled according to the detection result, even if the characteristics of the recording medium, recording density, data modulation method, etc. are unknown, the equalizer is optimally adjusted to The error rate of can be easily reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of an equalizer output signal.

3 is a block diagram showing a configuration example of an equalization error detection circuit 2 in FIG.

FIG. 4 is a block diagram showing another configuration example of the equalization error detection circuit 2 of FIG.

5 is a block diagram showing another configuration example of the equalization error detection circuit 2 of FIG.

FIG. 6 is a block diagram showing another configuration example of the equalization error detection circuit 2 of FIG.

FIG. 7 is a block diagram showing the configuration of another embodiment of the present invention.

8 is a block diagram showing a configuration example of a 3-tap equalizer 30 in FIG.

9 is a diagram illustrating a relationship between a mix ratio k set in the 3-tap equalizer 30 in FIG. 7 and an equalization error of an equalizer output signal.

10 is a diagram illustrating the relationship between the mix ratio k set in the 3-tap equalizer 30 of FIG. 7 and the bit error rate of reproduced data.

FIG. 11 is a diagram showing a configuration example of an unbalance correction equalizer that equalizes distortion of a reproduction signal due to tangential skew of an optical disc.

FIG. 12 is a block diagram showing a configuration example of a conventional automatic equalizer.

[Explanation of symbols]

 1 Equalizer 2, 2A, 2B Equalization error detection circuit 3 Equalizer control circuit 10 A / D converter 11 1 Sample delay 12 Zero cross detection circuit 13A, 13B, 14A, 14B Arithmetic circuit 15 Normalizer 16 Arithmetic circuit 17 , 17A, 17B switch 18, 18A, 18B time average calculation circuit 30 to 323 3 tap equalizer 33 inverting circuit 34 adder 35 equalizer control circuit 50 inverting attenuator circuit 51, 52 delay circuit 53 inverting attenuator circuit 54 adder 61, 62 Switch 100 Equalizer 101 Comparator 102 Target Waveform Calculation Circuit 103 Delay Circuit 104 Equalization Error Calculation Circuit 105 Equalizer Control Circuit

Claims (6)

[Claims] 1. An equalizer for equalizing the waveform of an input signal, a detector for detecting a jitter of an equalized signal output from the equalizer, and the equalizer corresponding to a detection result of the detector. A signal processing apparatus comprising: a control unit that controls the unit. 2. The detecting means includes a sampling means for sampling the level of the equalized signal output from the equalizing means at a predetermined timing, and the sampling means at timings before and after a zero-cross point of the equalized signal. The signal processing apparatus according to claim 1, further comprising: a sum calculating unit that calculates a sum of two sampled values sampled by: and a calculating unit that calculates a time average of the magnitude of the sum. 3. The detecting means calculates difference between two sampling values sampled by the sampling means at a timing before and after a zero-cross point of the equalized signal, and the sum is calculated as the difference. The signal processing apparatus according to claim 2, further comprising a normalization unit that divides and normalizes. 4. The detecting means further comprises a square calculating means for calculating the square of the output of the normalizing means, and the calculating means calculates a time average of the output of the square calculating means. The signal processing device according to claim 3. 5. The detecting means further comprises a time average calculating means for calculating a time average value of each of the sum and the difference, and the normalizing means divides the time average of the sum by the time average of the difference. The signal processing device according to claim 3, wherein 6. The waveform equalization of the input signal is performed, the equalized signal is output, the jitter of the equalized signal is detected, and the waveform equalization processing of the input signal is performed according to the detection result of the jitter. A signal processing method characterized by controlling.