JPH0969296A - Non-volatile multi-value memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer multi-valued information by operating a second reader during the data transfer period of first data register group, and simultaneously reading from a plurality of memory cells of a second memory array. SOLUTION: A control circuit 800 is connected to a microcomputer 8 ADPCM encoder 2 EDPCM decoder 7 and has an A-D conversion down counted value outputting down counter 801 at the time of reading and an address generator 10. It sends a 9-bit X address ADRX, a 11-bit Y address ADRY and a 4-bit data, outputs various clock signals and a control signal, fetches and sends digital data. Multi-valued information can be transferred by the transferring operation of data and simultaneously reading from a plurality of memories for two read/ write circuit groups 300LV, 300LL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile multi-level memory device using an EEPROM or the like capable of storing multi-level information.

[0002]

2. Description of the Related Art EEPR with floating gate
In a non-volatile memory such as an OM, it has been conventionally practiced to change the threshold level by controlling the amount of charges injected into the floating gate and store the analog amount and multi-valued information in the memory cell.

For example, in Japanese Patent Application Laid-Open No. 4-500576, while an input analog signal is sampled and held by an analog sample and hold circuit, a high voltage write pulse is supplied to a nonvolatile memory cell to charge the floating gate. After the injection, the analog amount corresponding to the injected charge is read out, compared with the analog signal that was sampled and held, and the supply of the write pulse is repeated until both analog amounts match, corresponding to the input analog voltage The analog amount to be recorded is recorded in a memory cell.

Further, the above-mentioned analog sample and hold circuit is provided in pairs in each column of the memory array.
While one of the plurality of sample and hold circuits sequentially captures the input analog signal, the analog amount held in the other of the plurality of sample and hold circuits is simultaneously stored in the memory cell array. The multi-valued memory is a memory that stores a discrete analog amount, and the writing and reading have substantially the same configurations as those in the above publications.

[0005]

In the conventional example, the former configuration has a problem in reliability of data retention because it uses an analog sample hold circuit, and the input analog signal is sequentially held in a plurality of sample hold circuits. When the analog amount held in multiple sample and hold circuits is written to multiple memory cells at the same time after the hold is completed, the analog sample and hold circuits cannot hold for a long time. The number of cells will decrease.

On the other hand, for reading, since the analog signal read from the memory cell is simply output as it is, there is no problem even if the reading is started when the analog signal is transferred to the outside. If the read time from one memory cell is longer than the transfer rate of data to the outside, the read will not be in time.

Therefore, even if the reading is started prior to the transfer, it is a wasteful operation to read the information that does not need to be read first, and there remains a problem of when the reading should be started optimally. .

[0008]

SUMMARY OF THE INVENTION The present invention is directed to first and second memory cell arrays comprising a plurality of nonvolatile memory cells capable of writing multi-valued analog amounts, and the first and second memory cell arrays.
First and second data register groups provided corresponding to the respective memory cell arrays, and reading the analog amounts written in the first and second memory cell arrays, and digital data corresponding to the analog amounts, respectively. , First and second read circuit groups set in the first and second data register groups, and first and second transfer circuits for transferring digital data held in the first and second data register groups to the outside. Second transfer circuit group and the first transfer circuit group are operated to sequentially transfer the data held in the first data register group to the outside, and after the transfer is completed, the second transfer circuit group is operated. Then, the data held in the second data register group is sequentially transferred to the outside, and the second read circuit is operated while the data in the first data register group is being transferred. Then, the plurality of memory cells of the second memory cell array are simultaneously read out, and the first read circuit is operated to transfer the first memory cell array while the data of the second data register group is being transferred. And a control circuit for controlling the simultaneous reading from the plurality of memory cells.

Further, according to the present invention, the control circuit includes a first detection circuit for detecting that a specific data register of the first data register group is designated during the transfer period by the first transfer circuit group. A second detection circuit for detecting that a specific data register of the second data register group is designated during the transfer period by the second transfer circuit group, and according to the output of the first detection circuit. It is characterized in that reading from the second memory cell array is started, and reading from the first memory cell array is started according to the output of the second detection circuit.

Further, according to the present invention, first and second memory cell arrays composed of a plurality of non-volatile memory cells capable of writing multi-valued analog quantities, and first and second memory registers composed of a plurality of data registers holding digital data. The second data register group and the analog amounts corresponding to the data held in the first and second data register groups are respectively calculated as the first amount.
And first and second write circuit groups each including a plurality of write circuits for writing in the second memory cell array, and digital data sequentially input at a predetermined cycle are sequentially set in the first data register group, and the setting is completed. Thereafter, digital data sequentially input at a predetermined cycle is sequentially set in each data register of the second data register group, and the second data register group is set to the second data register group during the data setting period.
Write circuit group is operated to simultaneously write to a plurality of memory cells of the second memory cell array, and the first data write operation is performed in the first data setting period in the second data register group.
And a control circuit for controlling the writing circuit group to operate so as to simultaneously write to the plurality of memory cells of the first memory cell array.

Further, according to the present invention, n memory cell arrays each composed of a plurality of nonvolatile memory cells capable of writing multi-valued analog amounts, and n memory cell arrays provided corresponding to the n memory cell arrays, respectively. A data register group, n read circuit groups for reading the analog amounts written in the n memory cell arrays, and setting digital data corresponding to the analog amounts in the n data register groups, respectively. n transfer circuit groups for transferring the digital data held in the n data register groups to the outside;
The (m = 1, 2, ..., N) transfer circuit is operated to sequentially transfer the data held in the mth data register group to the outside, and after the transfer is completed, the (m + 1) th data is transferred.
A period during which the data held in the (m + 1) th data register group is sequentially transferred to the outside by operating the th transfer circuit group and the data of the mth data register group is transferred. And a control circuit for controlling the (m + 1) th read circuit to operate so as to simultaneously read from a plurality of memory cells of the (m + 1) th memory cell array.

Further, according to the present invention, the control circuit includes a detection circuit for detecting that a specific data register of the m-th data register group is designated during the transfer period by the m-th transfer circuit group. In addition, it is characterized in that the reading from the (m + 1) th memory cell array is started according to the output of the detection circuit. Further, the present invention provides an n memory cell array composed of a plurality of nonvolatile memory cells capable of writing multi-valued analog amounts, an n data register group composed of a plurality of data registers for holding digital data, N write circuit groups each including a plurality of write circuits for writing an analog amount corresponding to the data held in the plurality of data register groups to the plurality of memory cell arrays, and digital data sequentially input at a predetermined cycle. Is the m-th (m = 1, 2, ...
, N) are sequentially set in the data register group, and after the setting is completed, digital data sequentially input in a predetermined cycle is sequentially set in each data register of the (m + 1) th data register group, and A control circuit for controlling the m-th write circuit group to operate during the data setting period for the (m + 1) -th data register group so as to simultaneously write to a plurality of memory cells of the m-th memory cell array; It is characterized by having.

[0013]

FIG. 5 is a schematic block diagram of a voice recording / reproducing apparatus to which the present invention is applied. In this device, first, in a recording mode, an input analog audio signal is converted into 12-bit digital audio data by a first AD converter 1 at a predetermined sampling cycle, and a 4-bit digital compression is performed by an ADPCM encoder 2 at the next stage. The data is encoded and sent to the read / write control circuit 3. In the read / write control circuit 3, 4-bit digital compressed data is converted into an analog signal by an internal second DA converter 4, and this analog signal is stored in an EEPROM.
6 is written.

On the other hand, in the reproducing mode, the read / write control circuit 3 reads an analog signal from the EEPROM 6 and converts it into 4-bit digital compressed data by the internal second AD converter 5. The 4-bit digital compressed data is converted into 1 by the ADPCM decoder 7.
The digital audio data is decoded into 2-bit digital audio data, and the 12-bit digital audio data is converted into an analog signal by the first DA converter 8 at the next stage, and is emitted as audio from a speaker (not shown) or the like.

The 20-bit address for writing and reading to and from the EEPROM 6 is based on a command or the like input from the microcomputer 9 and the address generation circuit 1
0, and supplied to the EEPROM 6 and the read / write control circuit 3. Next, a specific configuration of the read / write circuit 300 included in the read / write control circuit 3 is shown in FIG.

In FIG. 2, reference numeral 20 denotes a D flip-flop, which is 4 output from the ADPCM encoder 2.
A two-bit data register 21 that fetches and holds the upper or lower two bits of the digital compressed data of bits, and 21 stores the reference voltage Vref at V1 to V4 (V1 <V2 <
V3 <V4), a resistance dividing circuit for dividing the voltage into four voltages,
Reference numeral 2 denotes a decoder for decoding the contents of the data register 20 and selectively outputting any one of the voltages V1 to V4 in accordance with the contents. Reference numeral 23 inputs the analog voltage Vdec output from the decoder 22 to the non-inverting terminal +. And EEPROM6
The voltage Vm read from the memory cell 60 of the inverting terminal −
The comparator 24 outputs the output of the comparator 23 as it is while the timing clock RWCK4 is at the H level, latches the output of the comparator at the time of falling to the L level, and A latch circuit for transmitting the output latched for a period, an output buffer 25 for outputting the contents of the data register 20, and a resistance dividing circuit 21
The second DA converter 4 shown in FIG.
Is composed.

The memory cell 60 of the EEPROM 6 is a split gate type cell having a floating gate FG, and writing is performed by injecting charges into the floating gate FG to perform writing.
The erase is performed by extracting the charge injected into G. Each memory cell 60 has its drain D connected to bit lines BL1, BL2,..., Its source S connected to source lines SL1, SL2,..., And its control gate CG connected to word lines WL1, WL2,.
It is connected to the. Each bit line BL1, BL2,.
Are selected by the X address decoder 100 which decodes the upper 4 bits of the X address ADRX [8: 5], and are connected to the inverting terminal of the comparator 23. The source lines SL1, SL2,... Are connected to Y address decoders 200 and 250 for decoding an 11-bit Y address [10: 0], respectively. Various bias voltages are supplied from the second bias generation circuit 400. The bias voltage includes a high voltage bias Vhv1 for writing and a high voltage bias Vhv2 for erasing.
It is included.

The address decoders 100, 200, 2
50 has RWCK3 and RWCK as timing signals.
4, WBE is input. The terms drain and source here are based on the operating state at the time of reading. Three kinds of bias voltages VBH, VBLH, VBLL (VBH
>VBLH> VBLL) are output from the first bias generation circuit 500, and the supply lines for these bias voltages are respectively connected to the P-channel MOS transistors 2 as switches.
6, N channel MOS transistor 27, N channel M
An OS transistor 28 is inserted. An analog switch 29 that is turned on only at the time of writing is connected to the output side of these transistors. The output of the analog switch 29 is connected to an input / output line 30 to the X address decoder 100. The output C of the latch circuit 24 is connected to one end of the gate of the P-channel MOS transistor 26.
The output of the AND gate 31 for inputting the OMP is applied,
Outputs of AND gates 32 and 33 are applied to N-channel MOS transistors 27 and 28, respectively. A
The ND gates 32 and 33 have an AND gate 31 at one end.
, And a signal obtained by inverting the upper bit D1 to the data register 20 by the inverter 34 is input to the other end of the AND gate 32.
3 has an upper bit D1 to the data register 20.
Is entered as is.

Further, a read bias generation circuit 35 constituted by a resistance division circuit is provided for reading the analog amount written in the memory cell 60 as a voltage, and the voltage dividing point P thereof is turned on only at the time of comparison. N channel MO
Via the S transistor 36, the X address decoder 10
0 is connected to the input / output line 30. An N-channel MOS transistor 37 that is turned on by a control signal WBE is inserted between the input / output line 30 and the ground to supply a ground potential to the bit lines BL1, BL2,.

By the way, the read / write circuit 3 shown in FIG.
00 manages eight memory cells as one block in the X address direction, and each block has a block selector 6 for detecting that its own block has been selected.
00 is arranged. The block No. shown in FIG. In the block of 0, the block selector 600 is configured by an AND gate that detects that the lower 6 bits of the X address ADRX [5: 0] are all “0”.

Further, in FIG. 2, 38 is a sampling clock RWCK2 and a latch enable signal LATEN.
To input the output BSEL of the block selector 600 and N
An AND gate 39 is a NAND gate for inputting the timing clock RWCK3, the read enable signal REAEN2 and the output COMP, and 40 is a block selector 60
0 output BSEL and read enable signal REAEN2
, 41 is a NAND gate for inputting the outputs of the two NAND gates 38 and 39, 42
Is an AND gate for inputting a timing clock RWCK3 and a write enable signal WREN2, and 43 is a read enable signal REAEN2 and a write enable signal W
An OR gate 44 for inputting RIEN2 and an A 44 for inputting the timing clock RWCK4 and the output of the OR gate 43
An ND gate, the output of the NAND gate 41 is applied to the clock terminal of a D flip-flop constituting the data register 20, the output of the NAND gate 40 is applied as an on / off control signal of the output buffer 25, and the output of the AND gate 42 is applied. This signal is applied as an on / off control signal for the analog switch 29, and the output of the AND gate 44 is applied to the N-channel M
The voltage is applied to the gate of the OS transistor 36.

The write operation and read operation of the read / write circuit 300 will be described below with reference to the timing charts of FIGS. The bias condition in each operation state of the memory cell 60 is as shown in FIG.
First, prior to a write operation, a latch mode for latching data in the data register 20 is entered. In this mode, 2-bit digital data D1 and D0 are transmitted to the input line 45, and the data to be written E
The addresses ADRX and ADRY of the EPROM 6 are sent from the address generation circuit 10, and the signal LATEN indicating the latch mode goes high. The lower 6 bits ADRX [5: 0] of the output X address are the same as the block No. of its own. When the sampling time RWCK2 rises, the output of the NAND gate 38 becomes L level, and the output of the NAND gate 41 also becomes L level. Therefore, a clock is applied to the clock terminal CK of the D flip-flop constituting the data register 20, and the input data D1 and D0 are taken into the data register 20.

When the capturing is completed, the signal WBE becomes H level, the N channel MOS transistor 37 is turned on, and the input / output line 30 becomes the ground potential 0V. In the X address decoder 100, since the bit line selected by the X address ADRX [8: 5] is connected to the input / output line 30, the bit line BL becomes 0V.
On the other hand, a high voltage bias Vhv2 for erasing is applied to the selected word line WL by the Y address decoder 250, and the Y address decoder 20 is applied to the source line SL.
Since 0 to 0 V is applied, the selected memory cell is in the erased state. That is, the charge to the floating gate FG of the memory cell 60 is drawn.

After such erasing, the actual write mode is entered. In the write mode, as shown in FIG. 8C, the signal WRITEN2 is at the H level, and therefore, while the clock RWCK3 is at the H level as shown in FIG. 8D, the output of the AND gate 42 is at the H level. Further, since the latch circuit 24 is initially set to the H level, the output of the AND gate 31 also goes to the H level. Therefore,
When the analog switch 29 is turned on, the P-channel M
The OS transistor 26 turns off.

Now, the upper bit D1 of the input data is "0".
In this case, the output of the AND gate 32 goes high, so that the N-channel MOS transistor 27 is turned on,
As shown in FIG. 4B, the bias voltage VBLH is applied to the analog switch 29, the input / output line 30, and the X address decoder 100.
Is supplied to the selected bit line BL. Conversely, if the upper bit D1 of the input data is “1”, A
Since the output of ND gate 33 attains an H level, N-channel MOS transistor 28 is turned on and bias voltage VBL
L is the bit line B selected via the analog switch 29, the input / output line 30, and the X address decoder 100.
L.

While the clock RWCK3 is at H level,
Since the high voltage Vhv1 is supplied to the source line SL selected by the Y address decoder 200 ((c) in FIG. 8) and VB2 is supplied to the word line WL selected by the Y address decoder 250 ((g) in FIG. 8), FIG. Are satisfied, and writing to the memory cell 60 is executed. That is, injection of charges into the floating gate FG of the memory cell 60 is started.

Next, the clock RWCK3 falls,
When the clock RWCK4 becomes H level as shown in FIG.
When the output of the AND gate 42 is at L level, the AND gate 44
Becomes an H level, the analog switch 29 is turned off, the N-channel MOS transistor 36 is turned on,
The voltage dividing point P of the read bias generation circuit 35 is connected to the input / output line 30. The potential at the voltage dividing point P is N channel MO
When the S transistor 36 is off, the voltage VREFM is set slightly higher than V4. Further, in this state, VB1 is applied to the selected word line WL by the Y address decoder 250, and 0V is applied to the source line SL from the Y address decoder 200, so that the selected memory cell 60 is read. State. Therefore, a voltage Vm corresponding to the charge injected into the floating gate FG of the selected memory cell is obtained on the input / output line 30, and this voltage Vm is
Is compared with the output voltage Vdec.

In the decoder 22, one of the four voltages V1 to V4 from the resistance dividing circuit 21 is selected according to the data latched in the data register 20, and the non-inverting terminal of the comparator 23 is selected. Is output to. Here, the relationship between the data D1 and D0 and the partial pressure values V1 to V4 is shown in FIG. As a result of the comparison, if Vdec> Vm, the output of the comparator 23 maintains the H level, and the write operation based on the clock RWCK3 and the clock RW
The read and compare operations based on CK4 are repeated. By repeating the write operation, the amount of charge injected into the floating gate FG increases, and the read voltage Vm increases as shown in FIG. Then, when Vdec ≦ Vm, as shown in FIG. 8, the output of the comparator 23 is inverted to L level, and the output COMP of the latch circuit 24 also becomes L level. Therefore, the output of the AND gate 31 is inverted from the H level to the L level, the P-channel MOS transistor 26 is turned on, and the outputs of the AND gates 32 and 33 are set to the L level, so that the two N-channel MOS transistors 27 , 28 are turned off. Therefore, the clock R
When WCK3 becomes H level, the bias voltage V
BH is supplied to the bit line BL of the memory cell via the analog switch 29 (see FIG. 8). That is, the write bias condition shown in FIG. 11 is broken, and the write operation stops.

As described above, in the write mode, the 4-value analog amount corresponding to the 2-bit input digital data is stored in the selected memory cell 60.
FIG. 12 is a graph showing the relationship between the number n of write pulses and the memory cell current Ir during the above-described write operation. The curve a indicates the bias voltage VBL to the drain.
Curve b shows the case where a bias voltage VBLL is applied to the drain.

When the number of write pulses n increases, the amount of charges injected into the floating gate increases and the threshold voltage Vt of the memory cell increases, so that the memory cell current Ir decreases. However, since the amount of charge injected into the floating gate per pulse gradually decreases,
The decrease rate of the memory cell current gradually decreases.

Therefore, when a relatively high VBLH is adopted as the bias voltage applied to the drain, as shown by the curve a, when about 15 pulses are applied, the memory cell current value corresponding to the data "0, 1" becomes 80 μA, A read voltage Vm of approximately V2 is obtained at the time of reading, but a write pulse of 60 pulses or more is applied to obtain a memory cell current of 60 μA (a current value corresponding to the read voltage V3) corresponding to the data “1,0”. There is a need to.

However, in the circuit configuration shown in FIG.
When the upper bit D1 of the data is "1", the bias voltage to the drain is switched from VBLH to a lower VBLL, so that the amount of charge injection into the floating gate per pulse increases, as shown by the curve b. , Memory cell current 60 μA corresponding to data “1, 0” with about 4 pulses
, And a memory cell current of 40 μA (current value corresponding to the read voltage V4) corresponding to the data “1, 1” can be obtained in almost 11 pulses.

That is, writing can be performed in a short time by switching the bias voltage value supplied to the drain according to the data to be written. Next, the operation in the read mode will be described with reference to FIG.
In the read mode, first, when the signal XSET (FIG. 9C) goes to H level, the initial value all "1" is set in the data register 20 (FIG. 9E), and the decoder 2
9 outputs an analog voltage V4 corresponding to all "1" as shown in FIG. Therefore, the clock RW
When CK4 becomes H level as shown in FIG.
Since the bias condition for 0 is exactly the same as that in the read operation in the write mode, a voltage Vm corresponding to the electric charge injected into the floating gate of the selected memory cell is obtained at the inverting terminal of the comparator 23.
m is compared with the voltage V4 from the decoder 22. As a result of comparison, if Vm> V4, the comparator 23 and the latch circuit 2
4 is at L level, the output of NAND gate 39 is at H level. At this time, the output of NAND gate 38 is fixed at H level.
The output of the D gate 41 becomes L level, and the data register 20 keeps all “1” without performing the latch operation thereafter.

On the other hand, if the comparison result Vm ≦ V4, the output COMP of the comparator 23 and the latch circuit 24 becomes H level, so that when the clock RWCK3 becomes H level as shown in FIG. Output becomes L level, so that a clock signal is output from the NAND gate 41 to the data register 20, and the data supplied to the data input line 45 is latched in the data register 20. The data input line 45 is read from the down counter 801 shown in FIG.
Since the data "D1, D0" of "0", "01", and "00" are sequentially output each time the clock RWCK4 falls, the data "10" follows the data "11" as shown in FIG. Is latched in the data register 20. Then, the output Vdec of the decoder 22 drops to the voltage V3 as shown in FIG. 9 and when the clock RWCK4 goes to the H level again, the voltage Vm corresponding to the analog amount read from the memory cell is compared with the voltage V3. You. If Vm> V3, the comparator 23 and the latch circuit 24
Is inverted to the L level, and "10" is held in the data register 20 without performing the latch operation thereafter. When the comparison result is Vm ≦ V3, the comparator 23
Since the output COMP of the latch circuit 24 maintains the H level, the next data "01" is latched in the data register 20, and the comparator 23 compares the voltages V2 and Vm.
From this comparison, if Vm> V2, data register 2
The content of 0 is fixed to “01”, and if Vm ≦ V2, the last data “00” is latched by the data latch 20;
The voltages Vm and V1 are compared. Since the voltage V1 is set to approximately 0 V, Vm> V1 in the last comparison, and the content of the data register 10 is fixed to "00".

As described above, the voltage Vm corresponding to the analog amount read from the memory cell is stored in the data register 2
0, resistance dividing circuit 21, decoder 22, comparator 23, N
The signal is AD-converted by the AND gate 39 and the NAND gate 41 and transferred to the outside via the output buffer 25. That is, these circuits constitute the second AD converter 5 shown in FIG.

By the way, in the read / write circuit 300 described above, the 2-bit digital data is converted into the quaternary analog amount and written into one memory cell. However, the actual digital signal output from the ADPCM encoder 2 is used. The data is 4 bits. Therefore, in this example, as shown in FIG. 1, the upper 2 bits of the input 4-bit digital data are set to the memory cell array 6 on the right side.
R, and the lower 2 bits are stored in the left memory cell array 6
L. Of course, storage in both arrays is performed by the above-described read / write circuit 300. After 2-bit digital data is converted into 4-value analog quantities, multi-value storage is performed in each memory cell.

In FIG. 1, 800 is a microcomputer 8 and AD
A 9-bit X address ADRX, 11 is a control circuit connected to the PCM encoder 2 and the ADPCM decoder 7, and includes a down counter 801 that outputs a down count value for AD conversion at the time of reading, and an address generation circuit 10. A bit Y address ADRY and 4-bit data are transmitted, various clock signals and control signals shown in FIG. 2 are output, and digital data corresponding to the analog amount read from the memory cell array is once taken in to ADPCM. It serves to send to the decoder 7.

Further, in the memory cell array 6R on the right side,
A block selector group 600 RU, a read / write circuit group 300 RU, an X address decoder group 100 RU, and a sub-decoder 700 RU are arranged on the upper side, and the block selector group 600 RL,
A read / write circuit group 300RL, an X address decoder group 100RL, and a sub-decoder 700RL are arranged. As for the left memory cell array 6L, similarly to the right cell array, the block selector groups 600L are vertically arranged.
U, read / write circuit group 300LU, X address decoder group 100LU, sub-decoder 700LU, block selector group 600LL, read / write circuit group 300
LL, X address decoder group 100LL, and sub-decoder 700LL are arranged.

Since the circuit configurations for the right side memory cell array 6R and the left side memory cell array 6L are all the same and the input address signals are also the same, these memory cells perform exactly the same operation. Incidentally, Y
The address decoders 200 and 250 and the second bias generation circuit 400 have the same configuration as that shown in FIG. Here, FIG. 3 shows the details of the left memory cell array 6L and its peripheral circuits.

In FIG. 3, the memory cell array 6L is vertically divided into 32 blocks, and a block selector BS, a read / write circuit R / W, and an X address decoder X-ADEC are arranged for each of these blocks. Has been done. Therefore, the block selector group 600LU,
Each of 600LL includes 32 block selectors BS, each of the read / write circuit groups 300LU and 300LL includes 32 read / write circuits R / W, and each of the X address decoder groups 100LU and 100LL includes 32 X address decoders X-X. ADEC. The read / write circuit R / W of each block shown in FIG. 3 has exactly the same configuration as the read / write circuit 300 shown in FIG. 2, and the X address decoder X-ADEC also has exactly the same structure as the X address decoder 100 shown in FIG. It is the structure of. However, since the block selector BS detects that its own block has been selected, its own block NO. In this configuration, a different address is input for each block so that the H level is output only when the X address ADRX [5: 0] indicating the address is input.

The operation in the data write mode will be described below with reference to FIG. First, since the addresses sent from the address generating circuit 10 are sequentially updated, the lower 6 bits of the X address ADRX [5: 0] change as shown in FIG. 6A, and the block NO in the upper block selector group 600LU . 0 to NO. The select output BSEL sequentially becomes H level toward 31. This period is shown in FIG.
As shown in c and d, the upper read / write circuit group 300L
Since the latch enable signal LATEN and the write enable signal WREN2 to U become H level and L level, respectively, the block NO. 0 to NO. Toward the data register 20 in each read / write circuit R / W
Then, the sampled data is sequentially latched. Further, as the X address ADRX [5: 0] is updated, the block number of the lower block selector group 600LL is changed. 32 to NO. 63, the select output sequentially becomes H level, and during this period, the latch enable signal LATEN becomes H level as shown in FIG. 6E. Therefore, in the lower read / write circuit group 300LL, the block NO. 32 to NO. The sampled data is sequentially latched in the data register 20 in each read / write circuit R / W toward 63. Also, during this period,
At the same time, the write enable signal WRITEN2 to the upper read / write circuit group 300LU becomes H level as shown in FIG. 6D, so that the write operation is executed simultaneously in each block. However, in each block, the X address decoder X-ADEC controls the upper 8 bits of the X address ADR.
X [8: 5] selects any one bit line BL, and Y address decoders 200 and 250 select any one source line SL and word line WL. Writing is simultaneously performed on the 32 memory cells.

After writing, the address ADRX [5:
0] again returns to “0” and sequentially updates the address, so that the next 32 input sampling data are sequentially latched in the data register 20 of each block of the upper read / write circuit group 300LU. In the period during which such a latch operation is performed, in the lower read / write circuit group 300LL, the write enable signal WITEN2 is at the H level, so that data can be simultaneously written to 32 selected memory cells in all blocks. Be executed.

Thus, the upper read / write circuit group 30
In the 0LU and the lower read / write circuit group 300LL, the data latch operation and the write operation are performed alternately, and even if the write operation is longer than one sampling time, the write operation can be performed efficiently without creating an idle time. Next, the operation in the read mode will be described with reference to FIG.

First, as shown by the solid line in FIG. 4, the sub-decoder 700LU has a NAND gate 701 for inputting the X address ADRX [4: 2] and an address ADRX.
NA for inputting [5] and the output of NAND gate 701
A read enable signal REAEN2 shown in FIG. 2 is inputted as an output by inputting an ND gate, a signal REAEN which is always at H level in the read mode, and an output of the NAND gate 702.
And an AND gate 703 that outputs the same. The sub-decoder 700LL differs from the sub-decoder 700LU only in that an inverted signal thereof is input instead of the address ADRX [5] as shown by a dotted line, and the other parts have the completely same configuration.

Therefore, in the read mode, as shown in FIG. 7A, the address ADRX [5: 0] is updated, and when the address becomes "60", all the bit outputs of ADRX [5: 2] become H level. Therefore, sub-decoder 700L
In U, the output of the NAND gate 701 becomes L level, so that the outputs REAEN2 of the NAND gate 702 and the AND gate 703 become H level as shown in FIG. 7C. Therefore, the upper read / write circuit group 700
The read operation is started simultaneously from the 32 memory cells in the LU. This read operation is longer than one sampling period (a period in which the address is updated by 1), and in this case, it takes about three sampling periods, and ends before the address returns to “0”.

Meanwhile, the period in which the NAND gate 701 is at the H level continues until the address changes from "60" to "63", and when the address returns to "0", its output becomes the L level. However, the address is "0"
Since ADRX [5] is always at the L level during the period from to "31", the output of NAND gate 702 is at the H level, and output REAEN2 of sub-decoder 700LU continuously maintains the H level as shown in FIG. . When the address ADRX [5: 0] changes from “0” to “31”, the block NO. 0 to NO. Since the 31 block selectors BS sequentially output the H level, the output buffer 34 is opened in each read / write circuit R / W, and the contents of the data register 20 are sequentially output.

On the other hand, in the sub-decoder 700LL, when the address ADRX [5: 0] becomes "28", the inverted output of the address ADRX [5] and each bit output of ADRX [4: 2] become H level. , The output of the NAND gate 701 becomes H level, and therefore the output of the NAND gate 702 and the AND gate 703 is REAEN2.
Becomes H level as shown in FIG. Therefore, the read operation is simultaneously started from the 32 memory cells in the lower read / write circuit group 300LL. And NAN
The output of the D gate 701 keeps the H level until the address becomes “31”, and goes to the L level when the address becomes “32”.
Since the inverted output of RX [5] is always at the L level, during this period, the output RE of the lower read / write circuit group 300LL is output.
AEN2 continuously maintains the H level as shown in FIG. During the period when the address changes from "32" to "63", the block NO. 32 to NO. Since the 63 block selectors BS sequentially output the H level, the output buffer 34 is opened in each read / write circuit R / W, and the contents of the data register 20 are sequentially output.

As described above, by pre-reading the contents of the data register 20 from four sampling periods before the timing at which the data output should be started, it is possible to prevent unnecessary idle time in the read mode. As described above, the left memory cell array 6L has been described with reference to FIG. 3, but as described above, exactly the same operation is performed in the right memory cell array 6R.

[0049]

According to the present invention, the number of memory cells that can be simultaneously written can be significantly increased while maintaining the reliability of data retention. Further, even when the reading time of the multi-valued information from the memory cell is longer than the transfer rate of the read multi-valued information, the read multi-valued information can be transferred without providing a vacant time, and a useless read operation is performed. Will be able to be omitted as much as possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a pair of left and right memory cell arrays and peripheral circuits thereof according to the present invention.

FIG. 2 is a circuit diagram showing a read / write circuit according to the present invention.

FIG. 3 is a block diagram showing a left memory cell array and its peripheral circuits according to the present invention.

FIG. 4 is a circuit diagram showing a specific configuration of a sub-decoder according to the present invention.

FIG. 5 is an overall block diagram of a voice recording / reproducing apparatus to which the present invention is applied.

FIG. 6 is a timing chart showing an operation in a latch mode and a write mode of the read / write circuit group according to the present invention.

FIG. 7 is a timing chart showing an operation in a read mode of the read / write circuit group according to the present invention.

FIG. 8 is a timing chart showing a write mode operation of the read / write circuit according to the present invention.

FIG. 9 is a timing chart showing a read mode operation of the read / write circuit according to the present invention.

FIG. 10 is a diagram showing a relationship between input digital data and a corresponding analog voltage in the present invention.

FIG. 11 is a diagram showing a bias condition of a memory cell in the present invention.

FIG. 12 is a characteristic diagram showing write characteristics of a memory cell in the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 1st AD converter 2 ADPCM encoder 3 read / write control circuit 4 2nd DA converter 5 2nd AD converter 6 EEPROM 6R right memory cell array 6L left memory cell array 7 ADPCM decoder 8 1st DA converter 9 microcomputer 10 address generation circuit 20 data register 21 resistance division circuit Reference Signs List 22 decoder 23 comparator 24 latch circuit 25 output buffer 26 P-channel MOS transistor 27, 28, 36, 37 N-channel MOS transistor 29 analog switch 60 memory cell 100 X address decoder 100 LU, 100 LL, 100 RU, 100 RL X
Address decoder group 200 Y address decoder (for SL) 250 Y address decoder (for WL) 300 read / write circuit 300LU, 300LL, 300RU, 300RL read / write circuit group 400 second bias generation circuit 500 first bias generation circuit 600 block selector 600LU , 600LL, 600RU, 600RL Block selector group 700LU, 700LL, 700RU, 700RL Sub decoder 800 Control circuit 801 Down counter

Claims (6)

[Claims] 1. A first and a second memory cell array composed of a plurality of non-volatile memory cells capable of writing a multi-valued analog amount, and a first memory cell provided corresponding to the first and the second memory cell array, respectively. The first and second data register groups and the analog amounts written in the first and second memory cell arrays are read and digital data corresponding to the analog amounts are respectively stored in the first and second data register groups. First and second read circuit groups to be set, first and second transfer circuit groups for transferring digital data held in the first and second data register groups to the outside, and the first transfer The circuit group is operated to sequentially transfer the data held in the first data register group to the outside, and after the transfer is completed, the second transfer circuit group is operated to be held in the second data register group. Data is sequentially transferred to the outside, and the second read circuit is operated to simultaneously transfer data from a plurality of memory cells of the second memory cell array while the data of the first data register group is being transferred. A control for performing a read operation and controlling the first read circuit to operate so as to simultaneously read from a plurality of memory cells of the first memory cell array while the data of the second data register group is being transferred. A non-volatile multilevel memory device comprising: a circuit. 2. The first detection circuit, wherein the control circuit detects that a specific data register of the first data register group is designated during a transfer period by the first transfer circuit group, and the second detection circuit. A second detection circuit that detects that a specific data register of the second data register group is designated during the transfer period of the second transfer circuit group, and a second memory according to the output of the first detection circuit. 2. The nonvolatile multi-valued memory device according to claim 1, wherein reading from the cell array is started, and reading from the first memory cell array is started according to the output of the second detection circuit. 3. A first and a second memory cell array composed of a plurality of non-volatile memory cells capable of writing a multi-valued analog amount, and a first and a second data composed of a plurality of data registers holding digital data. First and second register groups and a plurality of write circuits for writing analog amounts corresponding to the data held in the first and second data register groups to the first and second memory cell arrays, respectively. Write circuit group and digital data sequentially input in a predetermined cycle are sequentially set in the first data register group, and after the setting is completed, digital data sequentially input in a predetermined cycle is set in the second data register. The data is sequentially set in each data register of the group, and the second write circuit group is operated during the data setting period for the first data register group. A plurality of memory cells of the first memory cell array are operated by simultaneously writing to a plurality of memory cells of a second memory cell array and operating the first write circuit group during a data setting period of the second data register group. A non-volatile multi-valued memory device, comprising: a control circuit for controlling simultaneous writing to cells. 4. An n memory cell array composed of a plurality of nonvolatile memory cells capable of writing multi-valued analog amounts, and an n data register group provided corresponding to each of the n memory cell arrays. , N reading circuit groups for reading the analog amounts written in the n memory cell arrays and setting digital data corresponding to the analog amounts in the n data register groups, respectively.
N transfer circuit groups for transferring the digital data held in the data register groups to the outside, and the m-th (m = 1, m = 1,
2, ..., N) The transfer circuits are operated to sequentially transfer the data held in the mth data register group to the outside, and after the transfer is completed, the (m + 1) th transfer circuit group Is operated to sequentially transfer the data held in the (m + 1) th data register group to the outside and at the same time while the data in the mth data register group is being transferred, the (m + 1) th data register group is transferred. A non-volatile multi-valued memory device, comprising: a control circuit for operating the th reading circuit to control reading from a plurality of memory cells of the (m + 1) th memory cell array at the same time. 5. The control circuit includes a detection circuit for detecting that a specific data register of the m-th data register group is designated during the transfer period by the m-th transfer circuit group, and the detection circuit According to the output of the circuit, the (m +
5. The non-volatile multi-valued memory device according to claim 4, wherein reading is started from the 1) th memory cell array. 6. An n memory cell array composed of a plurality of nonvolatile memory cells capable of writing multi-valued analog amounts, an n data register group composed of a plurality of data registers for holding digital data, and the plurality of memory cell arrays. The analog quantity corresponding to the data held in the data register group is written in the plurality of write circuits for writing in the plurality of write circuits, and the digital data sequentially input at a predetermined cycle are written. Mth (m = 1, m = 1
2, ..., n) are sequentially set in the data register group,
After completion of the setting, digital data sequentially input in a predetermined cycle is sequentially set in each data register of the (m + 1) th data register group, and a data setting period for the (m + 1) th data register group is set. And a control circuit for controlling the m-th write circuit group to operate so as to simultaneously write to a plurality of memory cells of the m-th memory cell array. .