TW400523B - Non-volatile multi-value memory device - Google Patents

Abstract

A data register 20, a resistant voltage-divided circuit 21, a decoder 22, and a comparator 23 are allocated. The data register 20 holds input digital data. The resistant voltage-divided circuit outputs analog voltage. The decoder 22 decodes the contents in the data register and selectively outputs one of the multiple analog voltages. The comparator 23 compares the output of the decoder with the analog measurement reading from a memory cell. The data needed to be written is set into the data register 20. The analog measurement corresponding to the setting data is written into the memory cell in writing mode. The digital data which are updated from the preset values are set to the data register 20 orderly in reading mode. The comparator 23 applies comparison in each setting and stops the digital data setting according to the comparison result. The data register 20 obtains digital data corresponding to the analog measurement read from the memory cells. The circuit construction can be simplified and the circuit scale is decreased.

Description

annex

Spear 'part 屮 A il and 1 \ .T eliminate f, · A

The whole body of the square body is re-recorded, and the structure of the circle is issued by the circle of the road. The use of the 9th version is 成 成 应> L '«5] 1 body, 5 zhen, five blocks, and horizontal latches. Examples of writing and reading by Qun Luzheng This is a table showing the reading and writing of Qun Qin by reading 6 national time chess. Example _ Shi Zhishi's Ming at the time of the start of the display of the timetable formula 7 Chess into the writing mode of the model to write the way 霣 Example of writing 0 reading the truth. _ _ This sequence shows the timetable of the 〇 〇 movement of the model of the model 0 way to write the example of the implementation of the implementation of the clear version. Table 9 shows the example of the number of materials and materials entered in the case of _. Example 0 of the assets issued by the corresponding response. The example of the drawing in the 10th circle of the drawing table is the example of the memoir of the type 0, which is true. Mingfa's version is shown in Table 11

H An example of a single anger written by a person with a round personality. Shi Zhiming issued this display. 2 1 Drawing a thief Xi Rui Li Ming 1 '8 first AD converter 2 ADPCMI8 encoder 3 read-write control path 4 No. 2DA converter 5 No. 2 AD converter 6 EEPR0M 7 ADPCM decoder 8 No. 1DA converter g Micro-brainer 10 Address generation circuit 20 Asset register 21 Resistor circuit This paper is described in this paper阄 National Standards (CNS) Λ4 specification (210X297 mm) 9 (Revised page) 3 8 3 6 2 (诮 Read the precautions on the back before filling in this page) ii Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 __B7_. _ V. Description of the invention (3)? Yg BH 々 坊 fg IS Μ This invention is a non-volatile multi-value memory of EEPROM (Electrically Erasable Progra ^ Bable ROM), which is intoxicated and uses memorable multi-value information. Device. Μ 沣 坊 术 is a non-volatile memory device such as EEPR0M with a floating gate. By controlling the amount of charge injected into the floating W pole, the threshold level is changed. The method of memorizing analog or multi-valued information in the body cell (menor cell). For example, in Japanese Patent Publication No. Hei 4-500576 (W0 90/00801, PCT / US 8 9/0 2 9 2 2), the analog signal of all persons is analyzed by an analog sample hold circuit. One aspect of implementing sample-and-hold is to inject charge into the floating gate of the non-volatile memory sheet "Supply high-power transcriber, and after injection, read the analog signal corresponding to the injected charge and the analog signal of sample-and-hold. For comparison, until the two analog quantities are consistent, the supply of gingival rush is repeatedly written, so that the analog quantity corresponding to the turn-in analogy f-calendar is recorded in the memory cell. And the 'write pulse is a step-like pulse that slowly rises in voltage level over the time of transmission. Furthermore, the analog sample-and-hold circuit described above is a pair of one in each column of the aemory array. The majority of the analog samples are kept in order to get the mold in order _into the period of the analog signal * maintained in the other party ’s sample hold the analogy of the letter »at the same time memorized in the memory single hip fr?! I (ae π 〇ry cell array) 0 unlu — ^ LI,? T! II ^ --- (Please read the precautions on the back before filling out this page) This paper size is applicable to China National Standard (CNS) Λ4 specification (210X297 mm) 3 38362 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) * '1 and »The multi-valued memory is > The memory of the analogous amount of memory I The use of writing and reading is and The same structure as described in the Bulletin 0 I The aforementioned M In the previous example 9 Because the analog signal input is directly used, please compare it to the oil sample 1 There is a problem with the reliability of the data retention by the circuit. 0 Please read 1 1 first. • The retention time of the data in the analog sample and hold circuit cannot be extended. Sr 1 1 is too long, so the input analog signal is kept in order. Note on sampling and holding 1 1 After the circuit, the analog quantity of the sample holding circuit that is held by the majority will be filled again at the same time. When writing to the majority of the memory cells, the written memory sheet can be written at the same time. The number becomes less. 01 I On the other hand, the processing of reading is performed directly by the analog signal from the memory unit 謓 1 1I. It is connected to the simple rotation, so it starts when the analog signal Ί is transmitted to the outside. There is no problem in reading, but if the time taken by 1 memory order body is longer than the data transfer rate to the outside, then 1 1 cannot be read. Get to 0 1 1 Here, even if you start to read out before the transfer, you may read out the unnecessary 1 information in advance to form a wasteful action. Therefore, there is also a question of when to start reading 1 I is the most appropriate question 0 1 1 1 Moreover, in the previous conventional examples above, the analog quantity corresponding to the 1 1 ratio signal of the rotation is written in the only memory cell, so the injection amount of the m-pole charge to the floating 1 1 must be small. Control * Because of this, it is necessary to prepare the characteristic 1 1 stable memory cell and complex write circuit 0 1 | Also as other conventional examples, such as in the fair 4-5 729 4 1 I The digital data is latched by the precious material latch circuit at the same time 1 1 | ί and the multi-value memory state of the redemption memory unit is set and the input corresponds to the memory 1 1 This paper size applies to the Chinese national standard (CNS ) A4 specification (210X 297 mm) 4 38362 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives printed A7 B7 V. Description of the invention (5): a state amplifier for the digital value of the state »and the sensing The rotation of the amplifier and the data held by the data latch circuit are compared by the comparator. * The nonvolatile multi-value memory device has been implemented following the writing of the multi-value information of the memory until the two contents are consistent. However, in this configuration * because the data is held digitally through the data latch circuit, its reliability is high, but a special sense amplifier that reads out multiple-valued memory states and generates digital turns out must be set up * As a result, the circuit configuration is complicated. Moreover, the comparator is bound to become larger due to the comparison of digital data. The present invention aims to provide a high-maintenance reliability that must be written in the nonvolatile multi-value memory to maintain the reliability. * Simplify the circuit configuration to become a memory device with a small circuit scale. . In order to achieve this object, the nonvolatile multi-value memory device of the present invention or an analog signal recording device using a memory cell capable of analog quantity memory has the characteristics described below. The present invention is provided with the following features: The input analog signal is converted by a predetermined sampling period into an digit-numbered AD converter, and each of the aforementioned memory cells (m: integer) which respectively stores the majority of the analog quantity. The fflemory array of memory and the digits of n-bits (integers of n: n > m) output by the aforementioned .AD converter are round-entered data divided by each n / m-bit, The segmented data is converted into corresponding analog quantities and written in the aforementioned m memory single lines respectively ^ L1τ · ν * ^ (Please read the precautions on the back before filling out this page) This paper size applies Chinese national standards (CNS ) Α4 specification (210X297 mm) 5 3 8 362 A7 B7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the invention (6) >. 'B writing circuits in column 1 »I, etc. are Special emblem 〇I According to the present invention, because the sampling analogy is converted by 1-n / m digits and divided into the memory of the majority, it can be briefly read at the same time as the circuit is written. Reduce the effect of zero of the memory cell 0 Back 1 1 Furthermore, it is temporarily stored by the data because it becomes the analog signal directly recorded in the memory even if the analog signal is converted into a digital signal Refill 1 device (d at aregister). M Digital mode retention method. Therefore, the reliability of data retention and page retention is improved. 0 1 I. Furthermore, the present invention has a 1 1 I by writing a large number of analogous quantities. The foregoing non-volatile notes 1 The order of n memory monomers formed by Yi Dan 艏 and corresponding to the i memory monomers I number of resources 1 1 register group 1 1 and read and write the analog quantity of the remaining ranks of i memory sheets and set! 1 I to m of digital resources of the analog quantity are respectively set in the aforementioned i I output circuit groups of 1 digital register group 1 I 1 1 > λ and η transfer circuit groups that will transfer the digital data held in the 1 information register register group outward 1 1 1 1 Μ and the j-th (j = 1 2… j) the aforementioned transfer circuit is operated to sequentially transfer the data of the aforementioned data register group holding 1 1 to j to the outside t 1 1 after the transfer is completed Operate the aforementioned transfer circuit of (J + 1) and keep 1 | transfer the data of the temporary data register group of (J + 1) to the outside in sequence while transferring I to J Period of data of the aforementioned data register group 1 1 This paper size applies Chinese national standards CNS) A4 specification (210X 297 mm) 6 38362 A7 B7 Printed by the Central Consumer Procurement Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. V. Description of the invention (7) 1 丨 内 内 Makes the aforementioned readout circuit No. (J + 1) If you want to implement the method of reading the majority of the memory cells in the rank of the aforementioned memory cells No. < J 4 1) at the same time, I control the control circuit t please 1 is a special person 0 read 1 1 then The present invention is to write the most non-volatile memory notes with the possibility of writing a large number of analogous quantities of back Λ 1 1 multi-values. Please fill in 1 | 1 memory cell composed of monomers 1 M and hold digital data The majority of the data registers are written on this page. 1 枓 The register group 1 I and the data corresponding to the data register group held in the majority 1 1 I ratio are written in Narrated majority Recalling the majority of the single write circuits of the i write circuit group M and the digital assets ordered by a predetermined cycle in turn. For the jth (j = 1 2… j) the aforementioned assets Register group 1 1 Sets sequentially the digital data input by the scheduled encounter period after the end of the setting. 1 1 It is expected that each data register of the aforementioned data register group (J = 1) will be in order! Privately, while setting the I I, the descriptive data at the (j + 1) station, the data setting period of the register group makes the aforementioned write circuit group of the jth action and the aforementioned 1 1 I memory of the mth The way most of the memory cells perform the writing operation at the same time is to control the 1 1 1 control circuit 1 and so on. 0 1 1 According to the present invention, it is possible to simultaneously perform 1 1 line writing while maintaining the reliability of the data. The number of incoming memory cells has been greatly expanded. It is possible to transfer the read-out multi-valued information even when the read-out time of the multi-valued information in the memory 1 is compared with the read-out value of the multi-valued information. 1 I can transfer the read-out multi-valued information without setting the gap time. 1 1 paper size Applicable to China National Standard (CNS) A4 specification (210X297mm) 7 38362 A7 B7 Printed by the Shell Consumer Cooperative of the Central Samples Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) /. '1 9 Action 0 I Furthermore »The present invention is a voltage generating circuit having a data register 1 which holds the digital data held in 1 and a voltage analog output voltage which reads most of the first attention 1 1 Η and will be Λ.Λ Describe the content of the data register and decode it to correspond to the content. 1 1 Write the optional analogue voltage of the majority of the analog voltages 1 1 and multi-valued analog values. The nonvolatile memory cell 9 is filled with 1K and the comparator 1 1 Μ is used to compare the voltage corresponding to the analog quantity read by the memory cell with the output voltage of the decoder installed on the previous page and corresponding to It is characterized by the comparison result of the comparator and the writing circuit 1 which writes the analog quantity of the memory sheet I 1 1 and the like. Order to maintain the reliability of data retention in accordance with the present invention »Simplify the circuit 1 1 The structure can reduce the size of the circuit. In particular, the DA in the book-entry mode is changed to 1 and the AD conversion process in the book-out mode can be achieved by using the same circuit configuration I to achieve a simpler circuit.化 〇1 1 Brief description 1 I FIG. 1 Circuit diagram of a write circuit (readvright 1 1 ci Γ C u it) of a practical example of the present invention 0 1 1 FIG. 2 shows the left and right in the embodiment of the present invention— * 'pair of memory ranks 1 1 and a block diagram of its peripheral circuits 〇 1 1 FIG. 3 shows the left side of the memory ranks and its surroundings in the embodiment of the present invention Block diagram of the JI circuit 0 1 1 I 4 The sub decoder (subdec 〇der) of the real cell example of the present invention 1 1 This paper uses the Chinese National Standard (cns) M specifications (21〇χ29) 3 8 3 62 Accessories

Spear 'part 屮 A il and 1 \ .T eliminate f, · A

The whole body of the square body is re-recorded, and the structure of the circle is issued by the circle of the road. The use of the 9th version is 成 成 应> L '«5] 1 body, 5 zhen, five blocks, and horizontal latches. Examples of writing and reading by Qun Luzheng This is a table showing the reading and writing of Qun Qin by reading 6 national time chess. Example _ Shi Zhishi's Ming at the time of the start of the display of the timetable formula 7 Chess into the writing mode of the model to write the way 霣 Example of writing 0 reading the truth. _ _ This sequence shows the timetable of the 〇 〇 movement of the model of the model 0 way to write the example of the implementation of the implementation of the clear version. Table 9 shows the example of the number of materials and materials entered in the case of _. Example 0 of the assets issued by the corresponding response. The example of the drawing in the 10th circle of the drawing table is the example of the memoir of the type 0, which is true. Mingfa's version is shown in Table 11

H An example of a single anger written by a person with a round personality. Shi Zhiming issued this display. 2 1 Drawing a thief Xi Rui Li Ming 1 '8 first AD converter 2 ADPCMI8 encoder 3 read-write control path 4 No. 2DA converter 5 No. 2 AD converter 6 EEPR0M 7 ADPCM decoder 8 No. 1DA converter g Micro-brainer 10 Address generation circuit 20 Asset register 21 Resistor circuit This paper is described in this paper阄 National Standards (CNS) Λ4 specification (210X297 mm) 9 (correction page) 3 8 3 6 2 (诮 Read the precautions on the back before filling in this page) ii ^ A &quot; 41- ^ m η Elimination of cooperation 卬 A7 B7 V. Description of the invention (9_1) 22 Decoder 23 Comparator 24 Latching circuit 25 _ Output buffer 26 '27 ， 28, 36, 37 M0S 霣 Crystal β 29 Analog switch 30 Input and output 31 '32' 33 &gt; 42 &gt; 44 ANDM pole 34 Inverter 35 Lecture and write overseas circuit 38 '39' 40 '41 HAND gate 45 _into 60 memory 100 X address decoder 200, 250 Y address decoder 300 Read and write circuit 400 Second dump circuit 500 First edit circuit 600 Block selector 700 times 701, 702 HAO Gate 703 AND Pole 800 Control Path 80 1 Down Counter 6R '6L Memory << Rank 1 00RU' 100RL &gt; 100LU '100LL X Address Decoder Group 300 RU' 300RL '300LU &gt; 300LL Read Write circuit group 600 RU '600RL' 600LU '600LL block selector device group 700RU' 700 RL '7 00LU &gt; 7 00LL sub-decoder group work hard! 5 shows the outline of using the sound recording and reproduction device of the present invention Square painting. In this device * the analog audio signal input first * in the recording mode * is converted into 12-bit digital audio data through the sampling period predetermined by the 1AD converter 1M converter • through the AD of the next stage PC Ｍaka code 2 (encoder) encodes 4 digits of digitized data • and the data is sent to the reader

It-—i * —— m: · 1 ϋ n Ί— in .K Hi. I--II Ding * * τ (Please read the precautions on the back before filling this page) Sincerity of this paper】 屮 Valve country Standard soap (CNS) 8 4 specifications (2 丨 χ 297 mm) 9-1 (revised page) 38362 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the invention (10); The digitally compressed data of 3.4 bits in the read-write control circuit is internally converted to an analog signal by the second DA converter, and the analog signal is written in EEPR0M6. On the other hand, in the reproduction mode, the analog signal is generated by the EEPR0M6 via the read-write control circuit 3, and the second AD converter 5 in the M is converted into 4-bit digital compression data. The 4-bit digital compressed data is decoded into 12-bit digital audio data by the ADPCM decoder 7, and further, the 12-bit digital audio data is converted into an analog signal by the first DA converter 8 in the next stage. It is released by the M 轚 sounds such as the horns not shown in the figure. In addition, the 20-bit address for writing and reading of EEPR0M6 is generated by the address generation circuit 10 according to a command such as input from the microcomputer 9 and supplied to the EEPR0M6 and the read-write control circuit. 3. Next, a specific configuration of the transcription circuit 300 included in the transcription control circuit 3 is shown in FIG. In FIG. 1, the data register 20 is composed of a D flip-flop circuit, that is, it is taken from the output of the ADPCM codec 2, and the upper or lower 2 of the 4-bit digital compression data 2-bit data register that is held by bits • Resistor divider circuit 21 is a reference voltage Vref divided by VI to V4 (V1 &lt; V2 &lt; V3 &lt; V4). In order to decode the content of the data register 20, the decoder 22 selectively outputs any voltage M from VI to V4 corresponding to its content. The comparator 23 compares the two voltages with the analog voltage Vdec output by the decoder 22 to the non-inverting terminal +, and the calendar Vm read by the memory 60 of EEPR0M6 to the inverting terminal for one round. The latch circuit 24 directly outputs the output of the comparator 23 during the time when the timing clock RWCK4 becomes the Η level. In this paper scale, the Chinese National Standard (CNS) Α4 grid (210 × 297 mm) 10 38362 I ---- ------------ ir ------ Knowing-I (Please read the notes on the back before filling out this page) Central Standards Bureau, Ministry of Economic Affairs Chinese National Standard (CNS) A4 specification (210X297 mm) 38362 A7 _B7 _ ^ _ V. Description of the invention (n)} When the L level drops, the comparator wheel will be out of the latch and the latch will be sent out during the L level Of_out. In addition, the turn-out scale 25 is a slow-weighing device required to output the contents of the asset register 20, and the digital data that is held in the data register 20 will be transferred to the outside, and furthermore, it will be divided by a resistor. The circuit 21 and the decoder 22 constitute a second DA liquid changer 4 shown in FIG. Each of the memory cells 60 of EEPR0M6 is a split gate type split cell with a floating gate FG. * Write is performed by injecting charge into the floating gate FG, and by drawing Attention is paid to the elimination of the charge of the floating M-pole FG. Each memory cell 60 is such that its suction (&lt; ^ 3 丨 1 ») 0 is connected to the bit line 81 ^ 1,812, one, and the source S is connected to the power supply lines SL1, SL2, ..., control The gate CG is connected to the block lines WL1, WL2, .... Each of the element lines BL1, BL2,... Is an X address decoder 100 that resolves the upper 4-bit X address ADRX [8: 5], selects any 1 line, and connects it to the reverse terminal of the comparator 23 . The word line WL1, WL2, ... and the power lines SL1, SL2, ... are respectively connected to Y address decoders 200 and 250 which decode the 11-bit Y address [10: 0], and these decoders 200 250 is a variety of piezoelectric voltages supplied by the second sugar voltage generating circuit 400. These cadmium voltages include the high-voltage voltage Vn vl for writing and the high-voltage Vhv2 for erasure. In addition, the address decoders 100, 200, 250 are input as RWCK3, RWCK4 * WBE, etc. as timing signals. In addition, the term "sucking pole * end pole" here refers to the operating state at the time of reading. Three kinds of cadmium pressures VBH, VBLH, and VBLL (VBH &gt; VBLH &gt; VBLL) are supplied to the bit lines BL1, BL2, ... so that the road 11 is generated by the first bias voltage. I I ^ _ _ ^ (Please (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 __B7 __ ^ ____ V. Description of Invention (12) /

After 500 rounds, these bias voltage supply lines are respectively inserted with P channel M0S transistor 26, Η channel M0S and crystal 27, and N channel M0S transistor 28M for recovery. In addition, the output side of the wheel of these pseudo crystals is' only connected to ON at the time of writing to the analog opening 29, and the output of the analog opening 29 is connected to the input / output line 30 of the χ address decoder 100. The key of the P channel M0S transistor 26 is a key with the key __ into the latch circuit 24 and the C0MP and the gate 31 with the key out. For the channel M0S with the M and 27 poles of the hips 28 and 28 ' The outputs of the AND gates 32 and 33 are applied, respectively. For AND poles 32 and 33 · —The input side enters into and out of ANDW 棰 31, and for the other round of the ANDM pole 32, input the upper bit D1 of the data supplied to the data register 2 0 from the negative The inverter 34 reverses the signal 'at the other input terminal of the AND pole 33' and directly inputs the upper bit of the material supplied to the data register 20, and writes it into each memory. The analog quantity of 60 is used as the ephemeris, and the read-out voltage generating circuit composed of a resistance voltage dividing circuit is set to 35 °. The voltage dividing point P is passed through the channel MOS of 0H only when the comparator 23 is compared. 36, and wired to X address decoder 100 in and out 30. Between the input line 30 and the ground, it is set to supply the ground potentials to the bit lines BL1, BL2, ... when the data of the memory is erased, and the bits BL1, BL2, ... become ground potentials via the control signal VBE0N. Zhiyao channel M0S transistor 37. Here, the read / write path 300 shown in FIG. 1 is to manage 8 memory single hip Ueiory cells in the X address direction as a block management, and each block configuration is used to detect the situation of its own block. The block selection path 600 ° is the block of the block N0. 0 shown in FIG. 1, and the block selector 6000 is the AHD detected by the case where the lower 6-bit X address ADRX [5: 0] is all [0]. The size of the ultra-thin paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 12 38362 I- n ϋ nn I i ^ inu ϋ n X /, (Please read the precautions on the back before filling this page) Ministry of Economic Affairs Printed by the Central Bureau of quasi-government Shellfish Consumer Cooperative A7 B7 V. Description of Invention (i 3):,; ... Composition. Furthermore, in Sa 1, HAND pole 38 is the input clock RWCK2 and latch enable signal LATEH and BSED from block selector 600 respectively, and NAHD pole 39 is the time clock RWCK3 and the read enable signal REAEN 2 and the rotation of the C0MP, HAND gate 40 are, respectively, the output BSEL of the human block selector 600 and the output possible signal 2REAEH2. NAHDM pole 42 is _ CKCK3 and wrightenable signal WRIEH2 respectively at the time of person. 0RW pole 43 is the input of human readout signal REAN2 and writer possible signal WRIEH2, AND 閛 pole 44 is the output of key time clock RVCK4 and 0R 閛 pole 43 respectively. In addition, when the output IS of the NAND gate 41 is added to the D flip-flop circuit constituting the data register 20, the output of the sinker CK, and the output of the HAND gate 40 is used as the 0H- of the output scale 25. The 0PF control signal is applied, and the output of the AND gate 42 is applied as the 0H-0FF control signal of the analog switch 29. The output of the AND gate 44 is applied to the gate of the high-frequency (M0S) crystal 36. Below K, referring to the sequence garden of circle 8 and country 9, the writing survey and the writing operation of the writing circuit 300 are explained. The bias conditions for each operating state of the memory 60 are shown in circle 11. First, before writing, enter the latch mode (latch · 0 (1 β) required for the data register 20 to latch the data. In this mode, 2-bit digital data D1, D0 are inputted. At the same time as the line 45 is sent out, the address ADRX, ADRY of the data EEPR0M6 needs to be written. It is sent out by the address generation circuit 10 of FIG. 5, and the signal LATEN indicating the latch-style chess becomes the level. The outputted X address The middle and lower 6-bit ADRX [5: 0] and its own block H0 are the same, when 'install ^ 丨 order _. ^. (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 size (210X297 mm) 13 3 8362 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 _ B7_____ V. Description of the invention (14); The output of the block selector 600 becomes a level. For example, in Figure 1 The block selector 600 makes the blocks N0 0 consistent, that is, ADRX [5: 0] all output 0 level. Because of this, the output of the pole 38 at the rising point HAND of the sampling pulse balance RWCK2 becomes the L level, The output of the HAND pole 41 has also become the level. Because of this, the positive and negative D of the actual register 20 is formed. «A clock is applied to the clock terminal CK of the road, and the input data D1, D0 are taken into the data register 20. When the access is finished, the signal WBE becomes the level, the N channel M0S, the crystal tilt 37 0N, _ The input and output lines 30 become the ground potential. At the X address decoder 100, the bit line selected by the X address ADRX [8: 5] is connected to the input and output line 30, and the bit nickel BL becomes 0V. On the other hand The high-voltage bias Vhv2 for erasure is applied to the selected word line WL via the Y address demaser 250, and the mold source SL is marinated by the Y address decoder 200 with 0V, so the selected memory sugar becomes eliminated. That is, the charge of the floating gate FG of the memory 60 is drawn. After this elimination, the actual writing chess mode is entered. In the writing horizontal mode, the signal WJUEH2 is shown in 圔 8 (c). Because of this, the period during which the clock RWCK3 becomes the level as shown in FIG. 8 (d) is that the release of the AHD gate 42 becomes the level. Furthermore, since the latch circuit 24 is initially set at Because of this, the output of the AND gate 31 also becomes the level. Because of this, the analogy of opening «29 0Ν, the P channel M0S transistor 26 becomes 0FF °. When the upper bit D1 of the input data is "0", since the output of the and transistor 32 becomes the Η level, the N-channel M0S transistor 27 0H is biased by B? IKVblh as shown in Fig. 8 (f). Μ29, input line 30, X address resolver 100 is supplied to the selected bit line BL. Otherwise, input I ------, 1T ------ ^-_ (Please first Read the notes on the reverse side and fill out this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 14 3 836 2 Printed by A7 _ ._B7 _____ of the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs Explanation (1 5) 'When the upper bit D1 of the input data is [1] • Since the output of the AHD pole 33 becomes the high level, the N-channel MOS transistor 28 is turned ON, and the bias voltage Vbll is opened by analogy. 29, input and output line 30, the X address deblocker supplies to the selected bit line BL. While the clock RWCK3 is at the threshold level, the high voltage Vhvl (circle 8 (h)) is supplied to the power line SL selected by the ¥ address resolver 200, and is selected by the address resolver 250. The zigzag character 袅 WL is supplied to VB2 (circle 8 (g)), thereby satisfying the write bias condition shown in 圏 11, and writing to the memory pass 60 is performed. That is, the injection of the electric charge to the floating gate FG of the memory 臞 60 is started. Secondly, the clock RWCK3 rises, so that the clock RVCK4 becomes the level shown in _3 (e). Since the output of the AND I «pole 42 becomes the L level and the output of the AND pole 44 becomes the level, the analogy is made. Open 29 OFF, channel M0S, and crystal 36 ON, so that the output bias voltage generating point 35 of the circuit 35 is connected to the input and output line 30. The potential of the voltage dividing point P is set to a voltage Vrefh slightly higher than V4 when the channel M0S transistor 36 is OFF. Furthermore, in this state, VB1 is applied to the selected word line "WL" via the Y address decoder 250, and 0V is added to the source line SL by the Y address decoder 200. Therefore, the selected memory The body 60 is in a read state. Because of this, corresponds to the floating gate injected into the selected memory? The voltage Vie of the load 6 is obtained from the input line 30. The voltage Vb is compared with the output voltage Vdec of the decoder 22 at the comparator 23. The decoder 22 corresponds to the latch on the asset register 20 According to the data, any one of the four analog voltages VI to V4 sent from the resistor divider circuit 21 is selected, and the selected analog voltage is output to the non-inverting terminal of the comparator 23. Applicable to China Paper Standard (CNS) A4 (210 X 297 mm) on this paper scale „Λ 15 38362 --------------- IT ------ ^ ~ · ~ (Please read the notes on the back before filling out this page) The paper size printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative Co., Ltd. The paper size applies to the Chinese National Standard (CNS) Α4 specification (210X297 mm) 3 8 362 A7 B7 V. Invention Explanation (16) ;, Therefore, the relationship between the data D1, DO and the divided voltage values VI ~ V4 is shown in Fig. 10. The comparison result is set as VdeC &gt; Va, and the output of the comparator 23 maintains the Η level, which is repeated here. The write operation according to the aforementioned clock RWCK3 and the read and comparison operation according to the clock RWCK4 are performed. The repeated output voltage Vm for the increase in the charge injection amount of the floating gate FG through the repetition of the write operation is shown in FIG. 8 (f). When Vdec recognizes Vm, as shown in Figure 8U), the output of the comparator 23 reverses to become the L level, and the output of the circuit C0MP of the latch circuit 24 also becomes the L level. Because the AND gate 31 The output is reversed from the L level to the L level, and the P channel M0S transistor 26 becomes 0N. Furthermore, the output of the AND gate 3 2, 3 3 turns to the L level, and the 2 H channels M0S Transistors 27, 2δ are turned off. As a result, when the clock RWCK3 is brought to the Η level, the bias voltage VBH is supplied to the bit line BL of the memory via the analog switch 29 (see FIG. 8 (f)). That is, As shown in Figure 11, the write bias condition is broken, and the write operation is stopped. As mentioned earlier, in the write mode, the selected memory 60 is used to memorize 4 values corresponding to 2-bit input digital data. Here, FIG. 12 is a graph showing the relationship between the number of write pulses η and the memory current Ir during the aforementioned write operation, and the curve a shows the application of the bias voltage Vblh to the sink electrode, and the curve b This shows the case where the bias voltage Vbll is applied to the sink electrode. When the write pulse number η increases, the amount of charge injection to the floating gate increases, so that the threshold voltage Vt of the memory increases, and thus the memory current Ir However, since the charge injection of the floating gate is reduced slowly per pulse, the reduction rate of the memory current is also slowly reduced. Here, a higher voltage is used as the employment voltage applied to the sink. H BL Η 16 — ^, 1τ ------ '^.-(Please read the notes on the back first (Fill in this page again.) Printed by A7 _B7 __ of the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (17):,; / .. In the case of curve a, · approximately 15 vibrations correspond to The memory current value of the data "0,1" becomes 80μA, and the readout voltage Vb of V2 can be obtained by approximately K during reading, but in order to obtain the memory current 60μA (corresponding to the data [1,0]) At the current value of the read voltage V3), a write pulse of 60 pulses or more must be applied. However, in the circuit configuration shown in FIG. 1, when the upper bit D1 of the data is [1], the bias voltage for the sink electrode is switched from Vblh to a lower voltage.

Vblh, so 1 pulse is equivalent to the increase of charge injection to the floating gate, as shown in curve b. From about 4 pulses, the memory current 60 μA corresponding to the data [1,0] can be obtained, corresponding to the data [ 1,1] memory current 40μA (current value corresponding to the readout voltage V4) is also obtained by about 11 pulses. That is, by switching the value of the bias voltage supplied to the sink electrode in accordance with the writing data, the writing operation can be performed in a short time. Next, the operation in the scoop-out mode will be described with reference to FIG. 9. In the readout mode, first, since the signal XSET (Fig. 9 (c)) becomes the Η level, all initial values are set for the data register 20, [1] (Fig. 9 (e)). As shown in 9 (f), the wheel-out corresponds to all analog voltages V4 of [1]. Here, when the clock RWCK4 becomes the Η level as shown in FIG. 9 (g), the bias condition for the memory 60 becomes the same condition as the read operation when the write mode is used, so it corresponds to the injection into the selected The voltage Vm of the charge of the floating gate of the memory is obtained at the inverting terminal of the comparator 23, and the mold voltage Vm is compared with the voltage V4 of the decoder 22. As a result of comparison, if Vm> V4, the output of the comparator 23 and the latch circuit 24 of the latch circuit 24 becomes the L level, so the output of the NAHD gate 39 becomes the high level. At this time, because the HAND gate paper size is applicable China National Standard (CNS) A4 specification (210X 297 mm) '17 38362 --------- k ------: 111, ------ 4 (Please read the note on the back first Please fill in this page again) A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (18): The output of 38 is fixed at the Η level, and the output of the NAND gate 41 becomes the L level. The data register 20 is maintained in a state of "lj" without performing a latching operation. On the other hand, when the comparison result is VmSV4, the output COMP of the comparator 23 and the latch circuit 24 becomes a high level, as shown in Fig. 9 (a) When the clock RWCK3 becomes the Η level, the rotation of the HAND gate 39 becomes the L level. Because of this, the NAHD gate 41 outputs a clock signal to the data register 20 and supplies it to the data input line 45. The data is latched by the data register 20. Such a data input line 45 is a down counter 801 shown in FIG. 2 in the read mode. Every time the clock RWCK4 drops, the data of "10j," 01j, "00", "Dl, DO" are sequentially rotated. Therefore, the data "10" is next to the data "11". Figure 9 (e) The latch shown in the figure is latched to the data register 20. In this way, the output Vdec of the decoder 22 is reduced to the voltage V3 as shown in FIG. 9 (f), and when the clock RWCK4 becomes the level again, the voltage Vb and the voltage V3 corresponding to the analog amount read by the memory are moved. Comparison. In addition, when Vm> V3, the output of the comparator 23 and the latch circuit 24 is reversed, and the COMP level is reversed to the AL level. Thereafter, the latch is held in the data register 20 without performing a latch operation [1 0]. When the comparison result V m S V3, the output COMP of the comparator 23 and the latch circuit 24 maintains a high level, so the next data [01] is latched in the data register 20, and the voltage V2 and Vm are compared by the comparator 23 . As a result of this comparison, the content of the data register 20 at Vm &gt; V2. Fixed at [0 1], the last data [0 0] at V m SV 2 is latched by the data latch 2 0, thereby comparing the voltages Vm and VI. The voltage VI is set to about 0V, and in the last comparison, it becomes Vm &gt; VI so that the content of the data register 10 is fixed at [00] --------- ^ K ----- i. ^- ----- i (Please read the precautions on the back before filling out this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 18 3 8 362 A7 B7 Staff Consumption of Central Bureau of Standards, Ministry of Economic Affairs Printed by the cooperative V. Description of the invention (19) 1 1 As mentioned before, the voltage Vn corresponding to the analog quantity read from the memory is | Via the data register 20 $ Resistor divider circuit 21 • Decoder 22 ^ Comparing I converter 23, NAND gate 39 9 NAND gate 41 performs AD conversion 9 After the output is slowed down, 1 punch 25 is transferred to the outside 0, that is, f is constituted by such circuits. First read 1 2 AD converter 5 〇Notes on the back 1 1 Here »As mentioned above, in the read-write circuit 300, the 2-digit digital asset section is changed to 1 1 and the analog value of 4 is written in 1 memory 9 but by ADPCM Code item refill 1 device 2 The actual digital data output is 4 digits. 0 This page is installed here. • In this example, t is shown in Figure 2. The 4 digits of digital data in rotation \ ^ 1 I The upper 2 digits in the data are stored on the right. The memory rank 6R t lower 2 bits 1 1 I is stored in the left memory rank 6L 0 Of course. Yes. The memory in the two ranks is 1 9 implemented by the transcription circuit 300 described in FIG. Digital data ordering and conversion into analog values of 4 values &gt; Multi-value memory in each memory 0 1 1 2 9 80 0 Wired to microcomputer (a) &gt; ADPCM encoder 2 and 1 1 ADPCM decoder 7 control circuit, the control circuit 8 00 is »Contains the down counting value for AD conversion during the round-out 1 and the counter 801 and the address 1 I generating circuit 10, which respectively sends out 9-bit X addresses ADRX, 11-bit Y-bit 1 1 I address ADR Y, 4-bit data at the same time, output various clock signals 1 1 and The control signal, or t temporarily fetches digital data corresponding to an analog quantity of 1 1 read from the memory ranks »Periodically, the effect sent to the ADPCM decoder 7 is 0 1 1 Furthermore» The memory rank 6R on the right side, On the upper side, there are 1 1 block selection group 6 00 RU, read and write circuit group 300 Ru, X address decoder group 100 1 I Ru sub-decoder 7 00 R υ, etc. * The structure becomes symmetrical in the memory ranks 1 1 Under the 6R, configure the block selection group 600RL, and the read-write circuit group 3 00 RL 1 1 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 19 38362 Employees of the Central Government Bureau of the Ministry of Economic Affairs Consumption cooperative seal A7 __B7__ 5. Description of the invention (20): '/, X-address decoder group iORL, secondary decoder 7001 ^ and so on. Regarding the memory on the left, "Ranking 6L and the Right Two", likewise, 60 blocks are set on the upper and lower sides to select the group 600Lu, the read-write circuit group 3 00 Lu, the X address resolver group 100 Lu, and the decoder 7. 〇Lu · and Fang Xun select group 600LL, read-write circuit group 30LL, X-address decoder group 100LL, sub-resolution processor 700LL, and so on. In addition, the circuit configuration of the right memory single row matrix 6R and the left memory single row matrix 6L are exactly the same, and the input address signals are also the same, so these memory pickle rows behave exactly the same. The Y address decoders 200 and 250 have the same configuration as shown in the circle 1. In addition, although not shown in FIG. 2, the second dump circuit 400 is provided in the read / write circuit group 'as in the garden 1, thereby supplying the decoders 200, 250 with bias voltage calendars Vhvl, Vhv2, and the like. Here, 圔 3 indicates the details of the left memory cell rank 6L and the peripheral circuits. In 3, the memory cell rank 6L is divided and managed by 32 blocks at the top and bottom respectively. These parties are lost, and the block selector BS, the transcription circuit R / W, the X-address decoder X-ADEC, etc. are configured respectively. Because of this, the block selection group 600LU and 6001 ^ are respectively composed of 32 block selectors BS, the read and write circuit groups 300Lu and 300L are each composed of 32 涸 read and write circuits R / W, and the X address decoder Groups 100 Lu and 100LL are each composed of 32 X-address decoders X-ADEC. The read / write circuit R / W of each block shown in FIG. 3 is exactly the same as the read / write circuit 300 shown in circle 1. The X-address decoder X-ADEC is also completely the same as the X-address decoder 100 shown in FIG. 1. The same composition. However, since the block selector BS has to detect that it has chosen its own block, only when the X address ADRX [5: 0] representing its own block H0. The paper size of this site is applicable to China National Standards (CNS) A4 specifications (210 × 297 mm)-20 38362 X Packing | Ordering | .V (Please read the notes on the back before filling this page) Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative A7 __B7__ V. Description of the invention (21): / Bingcheng. Below K, the operation in the data write mode will be described with reference to FIG. 6. First, the addresses sent by the address generation circuit 10 in FIG. 2 are sequentially updated, so the lower 6-bit X address ADRX [5: 0] is changed as shown in FIG. 6 (b), and the block selector on the upper side Group 6 0 0 Lu, with the change of the X address ADRX [5: 0], from square to H0, 0 to N. 31, the selectors of the block selectors B S0 to BS 31 are sequentially displayed BSEL becomes the level. During this period, as shown in Fig. 6 (c), (d), the latch possible signal LATEN and the writer potential signal VRIEN2 supplied to the read-write circuit group 300Lu on the upper side become the Η level and the L level, respectively. The data register 20 in each of the read / write circuits R / W corresponding to the blocks N0. 0 to N0. 31 sequentially latches the sampled data. Furthermore, as shown in III · 6 (b), when the X address ADRX [5: 0] is updated, this time in the lower block selector group 600LL, the change of the X address ADRX [5: 0] is redeemed by Blocks H0. 32 to N. 63 sequentially make the selection outputs of the block selectors BS32 to BS63 become the Η level. During this period, as shown in FIG. 6 (e), the latch possible signal LATEN becomes the Η level, so The read-write group 300LL on the lower side is the data register 20 in each of the writing circuits ϋ / W corresponding to the blocks No. 32 to No. 63, and sequentially latches the sampled data. Moreover, during this period, at the same time, the read-write possible signal VRITEN2 for the read-write circuit group 300Lu on the upper side is set to a level as shown in FIG. 6 (d), so each block K0. 0 ~ N0. 31 is simultaneously pickled Row write operation. However, each block is that the X address decoder X-ADEC selects any one bit line BL according to the X address ADRX [8: 5] which supplies the upper 8 bits to the X address decoder X-ADEC, Y address decoder 200, 250 selects any one power medium SL and block line WL. As a result, for the selection on the upper side, the Chinese national standard (CNS) A4 specification (210X297 mm) 21 38362 ^-( (Please read the notes on the back before filling out this page)

• ft m HI Printed by Shellfish Consumer Cooperative, Central Bureau of the Ministry of Economic Affairs A7 ___B7__ V. Description of Invention (22) y No. 3 2 The employment record is written at the same time as the MS line. After writing, the address ADRX [5: 0] is, and it returns to [0] again to sequentially update the address. Therefore, the 32 samples of the next round of sampling data are for each block of the upper-side transcription group 300LU. The data registers 20 are sequentially latched. During the execution of such a latching action, in the Hengheng writing group 300LL, the writing possible signal VRITEN2 becomes the level, so the selected memory list is in the full block H0.32 ~ N0.63 on the lower side. The body performs a write operation at the same time. In this way, the latching operation and the writing operation of data are alternately performed in the upper ft writing circuit group 300LU and the lower reading and writing circuit group 300LL. Therefore, even if the writing operation is longer than one sampling time, there can be no gap time. In this state, the write operation is efficiently performed. Next, an operation in the read mode will be described with reference to FIG. 7. First, the sub-decoder 700LU is, as shown in the real media of 圄 4, NAHD 棰 701, K and the input address ADRX [5] from the input X address ADRX [5: 2] and The output of NAND gate 701, NAND gate 702, M, and input read mode always become the level of the signal. The output of REAEH and HAND gate 702 is used to output the possible signal REAEH2 shown in Figure 1. AND 閜 pole 703 and so on. In addition, as the secondary decoder 700LL, the alternate address ADRX [5] as shown by the dotted line is different from the secondary decoder 700LU in that one point of the inverted signal is different, and the other parts have the same configuration.

Here, when the horizontal mode is displayed, the address ADRX [5: 0] is updated as shown in H7 (b). When the address becomes [60], the rotation of each element of ADRX [5: 2] becomes the horizontal level. Therefore, the output of the secondary decoder 700LU is that the output of the NAND gate 701 becomes the L level, because of this. The output of the HAND 閛 pole 702 becomes the * level * because of this AND n. I 丨 "'I— III -..... . I- n-........ I _ 'U3--β &lt;-(Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) Α4 specification (210X297 22 38 362 Central Standards Bureau®, Ministry of Economic Affairs®: Printed by the Industrial and Consumer Cooperatives A7 B7 V. Description of the Invention (23) ', the output REAEN2 of the gate 703 becomes the level as shown in circle 7 (c). Therefore, the read-write circuit group of the above two, 7 00 LU, starts reading from 32 memory cells of N0.0 ~ N0.31 at the same time. The read operation is longer than 1 sampling period (the address is updated by only 1) Period), in this case it takes about 3 sampling periods, which ends before the address returns to [0]. Here, during the period when the NAND gate 701 is at the level, the address continues from [60] to [ 63], when the address returns to [0], the rotation becomes L level. But In the period from [0] to [31], ADRX [5] always becomes the L level, so the key output of HAND gate 702 becomes the Η level, and the output REEN2 of the sub decoder 7 00LU is as shown in Figure 7. (c) Continue to maintain the nibble level. When the address ADRX [5: 0] is changed from [0] to [31], the nibble bits are sequentially selected by the block selector BS of the blocks N0.0 to N0.31. Therefore, the output buffer 25 (refer to FIG. 1) of the transfer circuit is opened in the corresponding transcription circuit R / W, and the contents of the data register 20 are sequentially rotated. On the other hand, in the secondary decoder 700LL, when the address ADRX [5: 0] becomes [28], since the output of each bit of ADRX [4: 2] in the reverse rotation of address ADRX [5] becomes the level, HAND gate 701 The output becomes the level. Because of this, the output of the NAHD gate 702 becomes the level, because the output REAN2 of the AHD gate 703 becomes the level shown in Figure 7 (d). Because of this, the reading on the lower side The write circuit group 300LLM 32 memory cells started to praise at the same time. Moreover, the rotation of the NAND gate 701 is maintained until the address reaches [31], and the level is maintained at L, but it becomes the L level when it reaches [32]. ADR from address [32] to [63] The reversing wheel of X [5] always becomes the L level. During this period, the output REAEH2 of the lower read-write circuit group 300LL is as shown in Figure 7 (d) nnnnmnm----II 1 I [* ^ τ * (Please read the precautions on the back before filling out this page) The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 23 38 36 2 A7 __B7 _'_ V. Description of the invention (24) :, ; /.- as shown, following Myanmar to maintain the level of Η. In addition, the period during which the address is changed from [32] to [63] is that, since the block selectors BS of the blocks Η0.32 to Η0.63 are sequentially rotated out of the Η level, the corresponding read / write circuits R / W activates the key generator 25 (refer to FIG. 1), which is a transfer circuit, and sequentially outputs the contents of the asset register 20. As described above, the aforementioned sub-decoders 700LU and 700LL are part of a control circuit that is controlled by forming together with the control circuit 800 and other data on the upper and lower sides of the memory rank 6L. The sub-decoder 700L is, The transfer circuit group formed by the round-out buffer provided in the transfer circuit group 300LU constitutes the transfer memory group 6L of the transfer memory group formed by the round-out element punch provided in the transfer-write circuit group 300LU. During the period of data on the upper side, the detection circuit of the fixed data register (box Η0.28) in the read-write circuit group 300LU on the upper side has been designated. In addition, the secondary decoder 700LU is a transfer circuit formed by an output buffer provided in the transfer read-write circuit group 300LL by a transfer circuit group formed by an output element punch provided in the transcription circuit group 300LL. Group transfer memory, during the period of the data on the lower side of the single row 6L, has been specified in the written circuit group 300LL on the lower side (please read the precautions on the back before filling this page). * 11 Central Standards of the Ministry of Economic Affairs贝 ϊ / ο 6 read and output UL test of block road electrical testing and inspection 7 of the code reading and writing of the code, which is used as a tool to temporarily store the materials in the storage. The letter can be printed according to the reference. / IV The ECA (L 6 column on the side of the line is remembered to the beginning of the rise as a response to the 2 NEAER letter can be output \ — / \ 7 d / V 7 Figure according to the reference / IV reading side test 6 check the line L body OL memory 70 register at the start of the code pair solution from the first time to the sample from the period before the sample 4 The materials of the current round must be started by this Such as 3 8 362 This paper size applies Chinese National Standards (CNS) A4 specifications (210X297 mm) A7 B7 V. Description of the invention (25):,; In the readout mode, there is a row and a row of memories on the right side of the memory. According to the gap, it is said to be empty, so it is used to say. If there is no but in, say that the three rows of the row memory are remembered by Zuo Ming. The same phase and phase L all 9 \ J finished the line is also made (please read the precautions on the back before filling out this page) Binding. Order 丨 4 The paper printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, is printed on paper that applies Chinese national standards (CNS ) A4 size (210X297 mm) 25 3 836 2

Claims (1)

«... ..---_ ··.«-·, 4 Amendment H3 Annex III Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs No. 851 09979 (Patent Application) (Application for the Amendment to the Profit Model) (88 January 1 ί)) 1. A kind of non-volatile multi-value memory device &gt; A data register (C iataregister) with * to hold the entered digital data, and the analog pressure generated by the rotation of the majority霣 路 t and decoding the content of the aforementioned data register corresponding to the content M. Selective output * &gt;-Describes any of the analogies of the majority 霣 懕-the decoder (dec 〇der), 多 and multi-valued Write the analog value of the possible non-volatile memory of the single cod (η e οι 0 Γ yce 11), and compare the voltage corresponding to the analog * withdrawn by the memory unit with the output voltage of the decoder. The comparator f Μ and the writing circuit for writing the analogous amount of the aforementioned memory cell in response to the comparison result of the comparator * are the best ones. If you ask for a patent, please refer to # 1. The recorded non-volatile multi-value memory device t also has a control circuit 9. When the control circuit is in the write mode, the settings for the JLJL ·. Description data register must be written in the description memory «Zhi 9 The aforementioned write path is operated to write an analog amount corresponding to the data set in the aforementioned data register to the aforementioned memory cell at the same time. 1 When reading in horizontal mode, t is a number that is sequentially updated from a predetermined value. Materials are set sequentially »Every time t is set, the comparison operation is performed by the aforementioned comparator» Corresponding to the comparison result • Stop applying the Chinese National Standard (CNS) to the aforementioned paper size of the described data register Α4 Specification (210 X 297 male ¢) 1 «... ..----_ ··.«-·, 4 Amendment H3 Annex III Employee Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs will print No. 851 09979 虢 Patent Application蒹 Application for the revised version of the Lee Fanpu (January 88, 1). — A non-volatile multi-value memory device with a data register (C iataregister) that holds the entered digital data, and The analogy of the majority analogy generates the path t and decodes the contents of the foregoing data register to correspond to the content M. Selective output * &gt;-Describes any of the analogies of the majority—the decoder (dec 〇der), Η and multi-valued analog values are written into the possible non-volatile recorded single cod (η e οι 0 Γ yce 11), and the voltage corresponding to the analog * given by the memory unit is compared And the previous solution The comparator's fM, which is pressed by the wheel of the device, and the writing circuit for writing the analogous amount of the aforementioned memory cell in response to the comparison result of the comparator, etc. are special ones. Patent Model _ The non-volatile multi-value memory device t described in item 1 also has a control circuit 9 When the control circuit is in the write mode, for the JLJL ·. The description data register settings must be written in the description单 料 9 of the memory list «causes the aforementioned writing path to operate and writes an analogous amount corresponding to the data set in the aforementioned data register to the aforementioned memory cell at the same time. The digital data whose values are updated in order are set sequentially »Every time t is set, the comparison operation is performed by the aforementioned comparator» Corresponding to the comparison result • Stop the aforementioned paper size of the aforementioned data register Applicable to China National Standard (CNS) A4 specification (210 X 297 male ¢) 1 Η 1g0 of the control-reading style bill made by the bit class The information of the material is the number of digits, and the memory is worthy of memorizing. I «No, it is recorded in the item II. Before the production pressure is explained> 0 The nature of the setter does not play well (1 of the list: a number of lines are prepared with multiple tools, and the set of recordable records can be recalled. It ’s worthwhile to make a lot of structures, and you ca n’t set it up. 1 Recall the 2nd and the e-rank. Set up the line list. Recall the 2nd and the 1X. The group should store the temporary materials and the M and the 2nd. And remember that the number of the yellow number of the group number device is temporarily compared with the data in the class capital. The 2 is written in the first response and the praise pair 1 and the number M is compared with the previous value. : Λ category should be printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs, the Ministry of Economic Affairs, and will print out a few days ago. The delivery group to the 1211 route to the 2nd electric order 1 &amp; Ξ delivery and the first transfer of capital to the first group of the first group before the transfer of the deposit and preservation department to make temporary transfers to Information 1 The capital transfer 2 The first transfer to the insured will be the same as the transfer of the transfer department. The outward order of the transfer department is described in the first paragraph of the information, and the device is temporarily stored. Shan Yiyi's 2 Records of the Group of Records are stored temporarily before the deposit, listed in the Bank of China 2 Intermediate Phases of the Interpretation of the Records of the Archives before the transfer of 2 transfers of the first group of records, the deposit is praised in front of the device For the time being, if the material is used for pickling, the same paper size applies the Chinese National Standard (CNS) A4 specification (210X297 public love). 2 H3 Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs. Before the first test of the equipment, the formula 1 should be described. Pre-fixer material storage, recalling the detection of the third party recorder, the value of the pre-growth and the setting of the temporary position, and the value of the pre-gl detection. The code body pressure sequence is compared with the pre-set defeat value. The content of the solution list is based on the pre-determined data in the multi-checked M of the previous fund. The "precisely-determined ft" line should be written in the middle of the previous comparison. Shi Shui survives the losing S2 ratio and stops at the same time when the U is sent. The number of classes i is not temporary. When the Fsg transition is stopped, the pressure is the same as the choice of 1. A new set of results will be sent from the group that should be included in the group, and the second code of the group recorded in the group will be included in the record. The predecessor's predecessor compares the order of the group U electricity 1 prepared by the competitor, and the content of the single item with the single item in the single item can be assigned to the 4th item in the first item. Each 枓 忆 4 is a 霣 M_ count. The twelfth category of the first should be recorded, and the second one should be sent in the second, and the circle should be described in the device. The pre-register should be placed in the circle of the electric transfer I. The first way of the micro fan 1 Compression 1 is described by the pre-existing logarithmic system 1; Literati is the first one to compare the temporary electricity ratio to that of the temporary electricity. The first internal control system of Leekang is to describe the material ratio and response, and it is expected that the former will be specifically described by M and the time »Control, etc. Before speaking _ with the type of device and automatic pair, please forward ^ The application of single phase M, which is described in the following paragraphs, must be specially applied. The f-way memory system is set to 1 before the solution is stored as set to 1 | 霣 5.6 This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 public goods) 3 H3 The Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs printed the trip to Qianji Jiji, and it will be temporarily reserved when it is in control. The material is recalled, the previous mode is set as the tester, and the single-channel sequence of the fixed material is recorded. The data is recorded at the beginning of the 2nd gl. The temporary storage is planted. The pre-funded group 1 is channeled and opened. It is expected that the non-data S2 written by the line number device of the 2nd line will be written, and the first group of electricity will be used to write the storage fiber «listed. Count the number of lines in the first row of Jfilffii, which are stored in the same way before writing, and finally the number of rows that are temporarily paired to the number of rows. The first entry is set to the first row. Lan Yi, a vigilant body, can be set up in front of multiple groups, and it can be described as a single check. * Remember that the memorable device should be in order, and the order of the first 2 groups is 1 * 11. Load the SB material and deposit it in the «I Yiquyi 111 Shiji No. No. of the first recalled S2 asset temporarily holding the writing period between the scheduled materials 2 霣 群 群 群 群 群 群 群 群 群 群 群 群 料 料 料 料 料 料 料 料 保前 The value of the previous value of 入 τ, which is the value of the first deposit device in the depository period, is a number. The temporary storage of the power distribution is set out in the writing. Deposited in «^ in multiple types of holding M2 should be set to 1 line before the set number of materials is temporarily set. If you wait, you should guarantee the single pair of properties and the pre-funded materials in the amount of nests. The value of the initial value of the pair is from 1 to 1 and the capital contribution pair is described. The single electric power and the electric power are recorded and the number and type i (and each round before the entry is converted to 2Jg and &quot; 2 It is not written by the group of M of fiK that the sequence is written to make the record control rank ^. _. A kind of single material is based on the time between the group device 1 and the description 2 The one of the one is a memory structure listed in the period device The paper size of the paper produced in the same period is applicable to the Chinese national standard (c NS) A 4 specifications (210 X 297 gong) 4 H3 Employee Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs: Multi-phase interpretation of printed equipment The fixed material sequencer recalls that the preface 21η «9 of the previous description should be set to the top of the list, which should be listed in front of the sex list, and the temporary value of the electrical phase will be described. ; S memorize the number of groups before sending funds, the content code «Press Walker wave JSIB, the road of the _ of the capital to write the road to solve the order S, the road is not fT9l of the material group report number issued The fruit of this group of plants I I 涸 Finance of the pre-producer} before the self-produced device in the output of the quantitative system: the number of η digits to read the place + 1 of the various production and storage should be S2 comparison control and more JH description The number of temporary 11) group (&gt; of the temporary pair type, compared to the ^ before the first material Yang · # 器 第} containing group materials and choose 1 to write, can ΒίΒΜ into the volume. η asset group: save the 7th code of the road, the code of the first comparator, the path of the writer, ** temporarily, (m sSW solution, K, 31, comparison, install, unli, u1sm, 2 materials The first entry in Rong Zhe's previous writing recalls the reading of this reading. NM = l is funded in 72 »than 1 and is described by * 3, which is £« $: | £ in Yu and ^ 4 (| | It is said that in the M2 category, the predetermined value ratio @ ^ 懕, shall be sent to the previous one_ and the description of the device shall be more than η @ 对 群 对 U in ηβ · The transfer will be the first one held by Fan 1 before the number corresponding to the different type of record, and Li Diduo will temporarily save the stock of the value component of the sound and make a a description Output and material ratio and 1 lose and »more than one structure and temporary ratio ηβ and rotation and first rotation, please input the spring type before it, but not the reason Ｍ Department M will apply for the group: 涸 的 器 器 忆 种 * 贲 Before the outside and outside the road, if a 1 pair of code is recorded, it is listed in the direction of the paper. The paper size applies the Chinese National Standard (CNS) A4 specification. (210X297 princes) 5 H3 Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs; «Will print the forefront of the outfitting way} Recorded in advance-the system of the pre-numbered body recall system * 1 structure List and (1 with &gt; in the single number body control record to send the special U character group M number, +1 pair of al) the value of the first device 发, ^, after (0, * 1 ^ Record the first +1 memory system group to save the deposit note group at the first time to send the U memory control device to temporarily remember the road before the last period of time to transfer the description of the beginning of the deposit formula The presence of U in the set makes the front move temporarily. : Count J, the funder sets up the U number, and if it is not stated, the person who writes it will write the number of the order. When the order is stored, the internal number will be issued before the number, and the number of keys will be more. 1) The characteristics of the road that contains the measurement of the first group of temporary capital, can describe the period in which the material is placed, and the B + 1 line of the inspection number can be described.贲 U will send the β to the U service to send the materials to the place where the material is temporarily placed and the material will be transferred. The test item will be read and written 51 £. Based on the same test as 9, the counting position B, the group W of the write-protection group, and the physical index of the group, the ratio of the value of the column ^ number ^ to the list of other devices ^ group to make a list.圏 1 In the front of the multi-category holding shunt wheel_store 0 The sequence of the response between the sequence memory of the dynamic memory of the paradigm of the dynamic memory, the sequence of the sequence is temporarily 1 The value of a single issue is composed by W by quantity and according to the special description of the material flr, and it is saved according to the special description of the material flr. And remember that it is not the case of βMMM class. · Meeting)% of the readings are more than one application, and the type of the material is η € 2. The way of the previous +1 group description is as follows. It is expected that the paper size of U will be determined according to the Chinese National Standard (c NS) A4 (210 X 297). 6 H3 Μ Printed by the employee welfare committee of the Central Standards Bureau of the Ministry of Economic Affairs.装 U ^ 该 .., 憧 U rewrites the recall system as »1 &gt;, rewrites the recall before the change 1: saves the value j before the change of the value π (贲 more than Μ points and For many, let ’s say that the capacity of the sexual behavior is the same as before. I write the 7C inner cell hair into the .. Extract it, and separately &amp; yuan The t / j converter does not produce a multi-line _ bit and the i / converter is more compact. The fixed device / jfi device is more specific than the load device. The ratio of 1 to the memory is compared to that of the device. The device is replaced by the device: _ The device of the temporary changer. The device is used to record the change in the memory of the change in the memory number. Single. Remember the letter D »Remember the ADM, 12 devices, and blame the" transformation ratio of 13 and the ratio of the ratio of the value of AD ») to the right. The first converter is DA and the special device is recorded.擞 Multi-category before »Xianlie Zheyuan << change in the amount of material that should be exchanged for the characteristics of the garden is divided into the line of the emblem Fan into AD temporarily compared with the variable that should be entered into the fund is issued by ^ _ «[^ Change« Terry writes the description of the materials, guarantees the analogy, reads the sounds, writes the sounds, and so on, and the beta (and 夂 changes the order to describe the former and the relevant and specific and the way out is numerous). Μ.JM} Please refer to the materials listed above and submit them to the list of electricity types. If you hold a single claim, you will need to make a unitary system. • · This paper size applies to Chinese national standards CNS) A4 specification (210 X 297 public) 7 H3 Printed by the Staff Welfare Committee of the Central Standards Bureau of the Ministry of Economic Affairs The special solution is recorded in the same material and the material is recorded. The content before the content is written horizontally, and the person who has the value before the temporary value is more than one in the body. The nature of the material is written before the number of orders. The number of speciality road funding is issued in the setting of the memory of the stop by the stop. The road is recorded in the new account. The description should be more time-determined, and the predetermination of the predecessor will be done before the system that does not distinguish between non-constructed classes. The temporary load control direction of the obstructed items will be recorded according to the set number of loaded elements. It is worth to set a record of 0M to write a lot of records, and set the writing to be set in the reading of the book. The description of the item path is set to ft before each material item path item EE before, 14¾ device path ratio, and Zi Yi 14 霣 1 due to the device. The system of deposits should be recorded. The first birth is a logarithmic recorder when face-to-face access is allowed for the code holder. A microblogging writing device is used to solve the problem in the industry insurance. Before the horizontal deposit was made by Terry, Lei Ji and the capital for the monograph and the pre-existence of the temporary move for the monograph for the monograph K in the input etc. Before the other equipment, the equipment should be prepared before the application should be requested Shen, Yu • Accountability vs. Controlling Application. Applying for the temporary selection of the alternatives, such as the temporary deductions • ·. This paper size applies to China National Standard (CNS) A4 (210X297 public goods) 8