JPH0969046A - Controller for loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate an unnecessary time due to a program which performs no process, etc., while eliminating the program. SOLUTION: This controller has 1st, 2nd, and 3rd stacks 101, 102, and 103 and a control means for a program counter 104 which counts the frequency of execution of a loop with a matching between the address value of the counter 104 and an end address pointed by a stack pointer(SP) in the 2nd stack 102, makes a comparison to check whether the end address pointed by the SP is the same as the end address of a one-stage higher loop instructed with a one-less value of the SP in the 2nd stack 102 when the counted frequency reaches the frequency instructed by the SP in the 3rd stack 103, and executes a program by decreasing the value of the SP to 1 or a high-order loop and sending out the start address of a loop indicated by a new SP as the output of the program 104 when the comparison result indicates that the addresses are the same and the frequency is equal to a one-stage higher frequency or a frequency higher than it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for controlling the execution of a program having a loop in controlling the execution of a program designated by a program counter in an integrated circuit such as a CPU and a DSP.

[0002]

2. Description of the Related Art When a program having the same content is repeated, it is usual to change the address indicated by a program counter (hereinafter referred to as a PC) and loop the program to repeatedly execute the same program. As one of the modes of executing this loop, an instruction is executed from an address having a predetermined instruction (machine language) indicating the beginning of the loop, and the end address of the loop set by the predetermined instruction (hereinafter referred to as end address). ) Change the address to
There is a method in which the contents up to the end address are repeatedly processed n times (n is a positive integer) the number of times specified by the predetermined instruction. This method can be used, for example, in correspondence with a for statement, a while statement, etc. in C language, and the capacity of a program such as software (in this case, a machine language generated by an assembler or a compiler is actually used). ) Is intended to be reduced.

FIG. 4 is a flowchart showing the operation of hardware such as a CPU and a DSP for the above-mentioned conventional loop start instruction.

First, the hardware fetches the contents of the program indicated by the PC (reference numeral 40 in FIG. 4).
1), the PC is updated (for example, the value of the PC is incremented by 1) (reference numeral 402 in the figure). Then, if the program is in a loop, it is determined whether the PC is the end address (reference numeral 403 in the figure). If it is the end address, the stored number of loops is updated (reference numeral 404 in the figure), and it is determined whether or not the processing has been performed the designated number of times (reference numeral 4 in the figure).
05). If processing has not been performed the specified number of times,
P to the start address of the loop to repeat the loop
Update the value of C. Then, returning to the portion indicated by reference numeral 401 in the figure, the operation of updating to the value of the PC and fetching the program of the next step is repeated.

Further, when a loop of a program is in a nested state, it is called a loop nest, and another loop (hereinafter, referred to as a parent loop) in a loop process (hereinafter, referred to as a parent loop).
Child loop) processing is multiplexed in one or more stages.
Next, the most simplified one with one nest will be described. With such loop nesting, the parent loop begins and the child loop begins during the execution of the parent loop. When the child loop ends, the PC fetches the program of the child end address indicated by the PC, and the PC updates the fetched end address. The updated PC value indicates the value obtained by adding 1 to the child end address. Then, when the loop ends for the specified number of times at the child end address, the child loop is ended, the contents of the program at the address "child end address + 1" indicated by the PC are fetched, and the parent loop is executed. Return.

However, at this time, if the parent and child end addresses are the same, the PC adds 1 to the child end address, that is, 1 to the parent end address, after the child loop ends normally. It shows the added value and exits the parent loop without returning to the parent loop.
Therefore, a contradiction occurs as a loop nest.

Therefore, conventionally, there is a restriction that the end addresses of the parent and the child are not the same, and a value obtained by adding 1 to the end address of the child, that is, an unprocessed program (eg, NOP instruction) at the end address of the parent, etc. The placement of avoids getting out of the parent loop without returning to the parent loop.

[0008]

As described above, the unprocessed program (for example, NOP instruction) is stored in the parent end address.
Although the contradiction can be avoided by using, etc., two new problems arise. One is that the unprocessed program is placed, so that the capacity is wasted, and the other is that the execution step takes extra time. This extra time is represented by “(machine cycle time of NOP etc.) × (specified number of loops n)”, and when the parent's number of loops n is large, the decrease in processing speed due to the extra time becomes significant. . This is especially true for DSP
It becomes a serious problem when high-speed processing is required.

In view of the above, an object of the present invention is to provide means for eliminating the extra time generated by eliminating a program for no processing or the like in response to such a problem.

[0010]

A loop control apparatus according to the invention of claim 1 controls a loop of a program by controlling a program counter for instructing addresses of programs to be sequentially executed. A first stack for storing the start address of the loop of the program, a second stack for storing the end address of the loop, and a third stack for storing the number of times of the loop. The number of executions of the loop is counted by matching the stack, the address value by the counter, and the end address designated by the stack pointer of the second stack, and the number of executions of the loop obtained by the counting is the number of executions of the third stack. If the number of loops indicated by the stack pointer is reached, the end indicated by the stack pointer If the address is the same as the end address of the one-step higher loop indicated by the stack pointer minus one in the second stack, and if the result of the comparison is the same, the loop execution count is one step higher. When the number of executions of the loop is equal to or higher than the number of executions of the loop, the value of the stack pointer is decreased to 1 or the upper loop, and the start address of the loop indicated by the new stack pointer is changed. And a program counter control means for executing the program as an output of the program counter.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the control means of the program counter has a counter for giving an address of a program to be sequentially executed by counting. A switch for switching the count value of the counter and the start address stored at the position designated by the stack pointer in the first stack to be the output of the program counter;
In the stack of, the end address comparison circuit for determining whether it is equal to the last address of the loop from the end address stored at the position indicated by the stack pointer and the count value of the counter, and the number of times the loop is executed is counted. , A loop number determination circuit for determining whether or not the counted number of loop executions is equal to the number of loops stored in the position designated by the stack pointer in the first stack, and the stack pointer Parent end address comparison circuit for determining whether the generated end address is equal to the end address of the loop one step higher than the value indicated by the stack pointer in the second stack, and the number of times the loop is executed Is a parent loop count determination circuit for determining whether it is equal to the execution count of the loop one step higher, An address comparison circuit, a loop count determination circuit, a parent end address comparison circuit, and a stack pointer controller that decrements the stack pointer value by 1 when the results of the determinations of the parent loop address determination circuit are equal. , The program is executed by using the start address of the loop indicated by the new stack pointer reduced by 1 by the controller as the output of the program counter from the switch.

In the loop control device according to the invention of claim 3 of the present application, in addition to the configuration of claim 1, the control means of the program counter includes a counter for giving an address of a program to be sequentially executed by counting. A switch for switching the count value of the counter and the start address stored at the position designated by the stack pointer in the first stack to be the output of the program counter;
In the stack of, the end address comparison circuit for determining whether it is equal to the last address of the loop from the end address stored at the position indicated by the stack pointer and the count value of the counter, and the number of times the loop is executed is counted. , A loop number determination circuit for determining whether or not the counted number of loop executions is equal to the number of loops stored in the position designated by the stack pointer in the first stack, and the stack pointer The parent end address comparison circuit for determining whether the generated end address is equal to the end address of the upper loop indicated by a value smaller than the value indicated by the stack pointer in the second stack, and the number of times the loop is executed, Parent loop count judgment circuit for judging whether it is equal to the execution count of the upper loop, and end address When the comparison circuit, the loop number determination circuit, and the parent end address comparison circuit are equal, the value of the stack pointer is decremented by 1 until a higher loop where the determination results of the parent loop number determination circuit are equal. A stack pointer controller is included, and the program is executed by using the start address of the loop indicated by the new stack pointer reduced by the controller as the output of the program counter from the switch.

According to a fourth aspect of the present invention, in addition to the configuration of the first aspect, the instruction indicating the start of the loop of the program has an information bit indicating the number of nest stages of the loop, The control means of the program counter is characterized in that the nest of the loop is judged from the information bit when there is an instruction indicating the start of the loop.

In the loop control device according to the invention of claim 5 of the application, in addition to the structure of claim 1, the instruction indicating the start of the loop of the program is the end address of the loop and the end address of the loop one step higher. And an information bit indicating whether or not is the same, and the control means of the program counter determines the nest of the loop from the information bit when an instruction indicating the start of the loop is given. The control device for the loop according to claim 1.

According to the loop control device of the present invention, the program is executed by using the loop start address indicated by the new stack pointer as the output of the program counter, as described above. This allows the end address of the loop to be the same when the loops of the program are nested.

In particular, according to the loop control device of the third aspect of the present invention, even when two or more loops are nested, the end address of the loop can be the same.

In the loop control device according to the fourth aspect of the present invention, the number of nest stages is indicated by the information bit, so that the control means of the program counter loops from the information bit when there is an instruction indicating the start of the loop. You can judge the nesting of.

According to the loop control device of the present invention, the information bit indicates whether or not the end address one step higher is the same, so that when the instruction to start the loop is issued, the information is sent. It is possible to judge the nest of a loop from bits.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, showing a portion for obtaining an output of a program counter (hereinafter referred to as a PC) that controls an address of a program to be executed in an integrated circuit such as a CPU or a DSP. The output of the PC is controlled by hardware.

The apparatus shown in FIG. 1 has a stack area composed of register files. Here, each stack 1
It is assumed that 01, 102, 103 can be stacked in n stages of 0, 1, ..., N. The stack area 101 stores the start addresses of loops 0 to n,
The stack area 102 stores the end addresses A0 to An of the loops of the loops 0 to n, and the stack area 103
Stores the number of times C0 to Cn of each loop 0 to n. During execution of a certain loop, these stacks sequentially store a value each time a predetermined instruction (machine language) indicating the beginning of the loop is executed. Note that this predetermined instruction has an information bit of the number of nest levels in the machine word in the process of converting the content (program) described by software such as assembler and compiler into the machine word. You can judge the nest by. The other parts form the control means of the program counter.

Then, these stacks 101, 102,
103 is a loop stack pointer (hereinafter referred to as LS)
The value of the item at the position (0 to n) designated by is extracted. The parts other than these stacks form the control means of the program counter.

Loop stack pointer controller 1
06 is for controlling the value m of LS.

The loop nest decision circuit 124 receives the output LS of the controller 106 at its input,
This is to determine the nesting state of the loop. The value m (0 to n) of this LS is the stack 10 of the loop at that time.
The number of stages 1, 102, 103 is shown, which is equivalent to the state of the nest of the loop currently being executed. For example, when the value m of LS is 0, there is no loop and there is no nesting. When the value m of LS is 1, there is a loop but there is no nesting, and when the value m of LS is 2 or more, it is a looping state. Yes and there is nesting, then there is a nesting depth of LS value m. The nest determination result of this loop is given from the nest determination circuit 124 to the switch switching determination circuit 107.

The PC counter 104 is for generating the address of the program to be executed, and is output as the PC value via the switch 108. Although the value of the PC counter 104 is incremented by 1, the start address of the loop indicated by the value m of LS among the start addresses stored in the stack 101 is taken in at the beginning of execution of the loop. It has become.

The end address comparison circuit 105 is the LS of the stack area 102 storing the address generated by the PC counter 104 and the loop end address.
That value m is indicated the value A _m is for comparing the loop end address A _m that is currently nested. As a result, it is determined whether the program being executed is the end of the loop, and the result is given to the LS controller 106, the switch switching determination circuit 107, and the loop number determination / update circuit 123.

In the end address comparison circuit 105,
Address generated by PC counter 104 and LS value m
If they are different as a result of comparison with the loop end address pointed to by the
Is output as the value of and the instruction of the next step is fetched. This corresponds to reference numeral 403 in FIG. 4, and is a branch in the case of “NO”. As a result of comparison, these are the same, that is, the value of the PC counter 104 indicates the loop end address and indicates the end of the loop. The result at this time is given to the LS controller 106, the switch switching determination circuit 107, and the loop number determination / update circuit 123, and the process of ending the loop is performed.

The parent end address comparison circuit 121 determines whether the end address of the loop is the same as the end address of the loop one step higher than the loop when the loop is in the nested state. The parent end address comparison circuit 121 uses the LS value m of the stack area 102.
And A _m current loop-end address pointed, L
One less than the value m of S, that is, the loop end of the parent
It is determined from the address _Am-1 whether the current loop and the parent loop, which is one step higher than the current loop, are the last of the loop, and the result is the controller 106 of the LS.
The switch switching determination circuit 107 and the loop count determination
It is provided to the update circuit 123.

The loop number judging / updating circuit 123 counts and obtains the number of times the value of the PC counter 104 becomes the loop end address from the comparison result of the end address comparing circuit 105. The current loop count (Cm), which is the contents of the stack area 103 indicated by the value m, is compared. Then, it is determined whether or not the number of loops of the program currently being executed is the last, and the result is given to the LS controller 106 and the switch switching determination circuit 107. When the number of loops is the last, the value m of LS is decreased to update the position of the stack, and the value of PC is output as the loop start address at the position of the new stack 101.

The parent loop number judging circuit 122 stores the loop number counted by the loop number judging / updating circuit 123 as the parent loop number when there is a predetermined instruction indicating the start of the loop. The stored value is the LS value m
It is determined whether or not the parent loop is the last by comparing with the parent loop count C _m−1 of the stack area 103 indicated by a smaller value. The result is given to the LS controller 106 and the switch switching determination circuit 107, and is used together with the result of the loop number determination / update circuit 123.

The switch changeover judging circuit 107 judges by the nest judging circuit 124, the end address comparing circuit 105, the end address comparing circuit 105, the parent end address comparing circuit 121, the loop number judging / updating circuit 123, and the parent loop number judging circuit 122. Switch (SW) 1 from the result
08 switching control, and is either the address from the PC counter 104 via the SW 108 or the start address of the loop indicated by the LS value m among the start addresses stored in the stack 101. Is output as. The value of the PC indicates the address of the program to be executed, and the control according to the value is performed in the integrated circuit such as the CPU or DSP.

Next, the operation of this circuit will be described.

When the program is not in a loop, the value m of LS is 0, the address from the PC counter 104 is output as the PC, and the program is sequentially executed while incrementing the address. This is the operation of reference numerals 401 and 402 in FIG.
In the case of “NO” in 03, the process is branched.

During execution of the program, if there is a predetermined instruction indicating the beginning of the loop, the value m of LS is incremented, and the start address, end address,
The number of loops C0 to Cn is the stack 101, 102, 1
It is stored at the position indicated by the value m of the LS of 03. And P
The program is sequentially executed while incrementing the address and fetching the instruction of the next step until the value of C becomes the end address of the loop.

When the value of PC becomes the end address of the loop, it coincides with the end address A _m of the current loop and is detected by the end address comparison circuit 105. Then, the loop number determination / update circuit 123 determines the number of loops of the program currently being executed.
This is equivalent to the branch from reference numeral 403 to reference numeral 404 in FIG.

When the number of loops of the program currently being executed is smaller than the number of loops Cm, that is, when the number of loops is not the last, the value of LS, m, remains unchanged,
The start address of the loop in the stack area 101 indicated by the value m of LS is output as a PC, stored in the PC counter 104, and the program is executed sequentially while fetching the instruction of the next step from the start of the loop. Is repeated. In this way PC
It is updated and executed with the current loop start address in the stack area 101 indicated by the value m of S. This is equivalent to the branch in the case of “NO” of reference numeral 405 in FIG.

When the number of loops of the program currently being executed is the same as the number of loops Cm, that is, when the number of loops is the last, this is indicated by reference numeral 405 "YE" in FIG.
It is equivalent to the branch in the case of "S". However, in this embodiment, in the parent end address comparison circuit 121 and the parent loop number determination circuit 122, the PC value at that time is the parent loop end address A _m−1 and the parent loop number C _m−1.
It is determined if both of the values of are last. This point is a feature of the embodiment.

When the number of loops of the program currently being executed is the same as the number of loops Cm, the number of loops is the last, so the loop number determining / updating circuit 123 determines that the number is the last, and the LS controller 106 reduces the value m of LS by 1. Then, the parent end address comparison circuit 121 determines whether the value of PC is the end address of the parent loop of the loop.

When the PC value is not the end address of the parent loop of the loop, the SW 108 outputs the value of the PC counter 104 as the PC value. And
When the value of the PC counter 104, that is, the value of PC is incremented by 1 and the address is incremented, the loop is exited and the process returns to the parent loop. The program is sequentially executed while fetching the next step instruction for this parent loop.

If the value of PC is the end address of the parent loop of the loop, the loop being executed is the last one, and the end of the loop of the parent of the loop having the address indicated by PC is the end of the loop. Although it is an address, the parent loop is not always finished. Therefore, the value of LS m
Is 2 or more, that is, the nesting state is 2 or more, the parent loop number determination circuit 122 determines whether or not the parent loop number C _m−1 is the last.

When the parent loop count C _m-1 is not the last, the same as when the LS value m is 1, that is, the nesting state is 1, the process is running, and the parent loop is Since it is not finished, LS in the stack 101
The start address of the parent loop stored in the position indicated by the value (m-1) obtained by decrementing the value m of 1 by 1 is selected,
It is output as the value of PC by SW108. And
This start address is fetched as the initial value of the PC counter 104, and the PC counter 1 is set by the SW 108.
The value of 04 is output as the value of PC. Then, the value of the PC counter 104, that is, the value of PC is incremented by 1 and the address is incremented, whereby the operation is repeated from the beginning of the parent loop.

When the parent loop count C _m-1 is the last, the parent loop is finished, so the stack 101
Of these, the start address of the parent loop stored in the position indicated by the value (m−2) obtained by reducing the value m of LS by 2 is selected, and the start address of the parent loop is selected by the SW 108.
Is output as the value of. Then, similarly, this start address is fetched as the initial value of the PC counter 104, and the value of the PC counter 104 is set to P by the SW 108.
It is output as the value of C. By increasing the value of the PC counter 104, that is, the value of PC by 1 and incrementing the address, the operation is repeated from the beginning of the parent loop of the parent loop.

In the case of this embodiment, there are three types of PC values to be updated at the address where the loop ends, and there are three branches, but the address where the loop and its parent loop end are the same. Even if there is, it is possible to judge the execution state of the loop, set the value of the PC, and execute the correct processing according to each branch.

As described above, even if the end addresses of the loops which are continuously nested are the same, the correct branch destination address can be set from the address where the loop ends.

In this embodiment, it is possible to use the case where the end addresses of the loops in the nest state are the same in succession in two cases.
If the same number is greater than two, some usage restrictions are applied at the time of compilation, or a plurality of end address comparison circuits and parent loop count determination circuits are provided for use. It will be possible.

FIG. 2 shows a block diagram of the second embodiment.

In the first embodiment, the end address of the loop is up to two in succession, but in the present embodiment, the nest state is comprehensively judged and improved so as to make multiple branches. This is one example. It should be noted that the same reference numerals will be used for the same or equivalent constituent elements as those of the first embodiment, and the description thereof will be omitted.

Also in this second embodiment, there are stack areas 101, 102 and 103 for storing the start address, end address and number of times of the loop, which are the controller 10 of the loop stack pointer (LS).
It is controlled by 6. As in the case of the first embodiment, the value of the stack is stacked in the order of 0, 1, ..., N and is located at the position (0 to n) pointed to by the loop stack pointer (hereinafter referred to as LS). Are taken out. These values are the same as in the first embodiment described above.
It is provided to the end address comparison circuit 105 and the loop count / update circuit 131. The end addresses of the loops and the number of loops stored in the stacks 102 and 103 are all provided to the LS vector determination circuit 132.

The loop count / update circuit 131 is the first
The number of times the value of the PC counter 104 becomes the loop end address is counted and obtained from the comparison result of the end address comparison circuit 105, and the stack area indicated by the obtained number and the value m of LS The content of 103 is compared with the current loop count (Cm).
Then, it is determined whether or not the number of loops of the program currently being executed is the last, and the result is given to the LS controller 106 and the switch switching determination circuit 107. When the number of loops is the last, the LS vector determination circuit 132 decreases the value m of LS to update the position of the stack, and outputs the value of PC as the loop start address of the position of the new stack 101. .

The LS vector determination circuit 132 switches based on the loop end address and the loop count stored in the stacks 102 and 103, the comparison result of the end address comparison circuit 105, and the loop count / update circuit 131. It controls switching of the (SW) 108, and gives the LS controller 106 how much to change the loop stack pointer. In this way, the LS vector determination circuit is made to input all the data of the end address comparison result in the current loop, the specified number of times end determination result, the end address accumulated in the stack of the loop, and the number of times. Therefore, switching control of the switch 108 as described later is performed.

Next, the operation of this circuit will be described.

When the program is not in the loop, the value m of LS is 0, the address from the PC counter 104 is output as PC, and the program is sequentially executed while incrementing the address. Then, during execution of the program, if there is a predetermined instruction that indicates the beginning of a loop, the value m of LS is incremented, and the start address, end address, and loop count C0 to C of that loop are obtained.
n is stored in the position indicated by the LS value m of the stack 101, 102, 103. In FIG. 4, operations up to reference numerals 401 and 403 are performed.

[0052] The value of the PC becomes the end address of the loop, coincident with the end address A _m of the current loop is detected by the end address comparator circuit 105. Then, the loop count / update circuit 131 determines the number of loops of the program currently being executed. In FIG. 4, this is equivalent to the branch from reference numeral 403 to reference numeral 404.

When the number of loops of the program currently being executed is smaller than the number of loops Cm, that is, when the number of loops is not the last, the value of the value LS of m remains unchanged,
The start address of the loop in the stack area 101 indicated by the value LS of the LS is output as a PC, stored in the PC counter 104, and the program is executed sequentially while fetching the instruction of the next step from the start of the loop. Is repeated. In this way PC
It is updated and executed with the current loop start address in the stack area 101 indicated by the value m of S. This is equivalent to the branch in the case of “NO” of reference numeral 405 in FIG. The process up to this point is the same as in the first embodiment.

When the number of loops of the program currently being executed is the same as the number of loops Cm, that is, when the number of loops is the last, this point is indicated by reference numeral 40 in FIG.
This is equivalent to the branch in the case of “YES” of 5. However, in this embodiment, the determination by the LS vector determination circuit 132 is different.

First, in the LS vector determination circuit 132,
The PC value at that time is the end address A of the parent loop.
Both the number of loops C _m-1 of the value of the _m-1 and the parent whether the last is determined.

When the number of loops of the program currently being executed is the same as the number of loops Cm, the number of loops is the last, so the LS vector determination circuit 132
Then, the LS controller 106 decrements the LS value m by 1. If the value of PC is not the end address _Am-1 of the parent loop of the loop, SW
The value of the PC counter 104 is output by 108 as the value of the PC. Then, when the value of the PC counter 104, that is, the value of PC is incremented by 1 and the address is incremented, the loop is exited to return to the parent loop. The program is sequentially executed while fetching the next step instruction for this parent loop.

When the value of PC is the end address _Am-1 of the parent loop of the loop, the loop being executed is the last one, and the address indicated by the value of PC is the parent of the loop being executed. This is the address of the end of the loop. In this case, the same determination is made for the parent loop that is 2 smaller than the value m of LS. That is, the LS vector determination circuit 132 further determines whether or not the parent loop count C _m-2 is the last, and determines whether the PC value is further equal to the parent loop end address A _m-2. To be done.

When the loop count C _m-2 is not the last or the end address A _m-2 is not reached, the value m of LS is reduced by 2, that is, m-2, and the processing of the parent loop is further executed. . Otherwise, a similar determination is made for the parent loop that is 3 less than the LS value m.

As described above, when the loop count is the last and the end address, the value of LS is reduced until the loop count is not the last or the end address, and the loop stored in the stack indicated by the value of LS Processing is performed at the start address or at the address obtained by incrementing the PC value.

FIG. 3 is a diagram showing an operation example of the vector determination circuit 132. As shown on the left side of the figure, the address data A0, A1, ..., Am-1, Am are stacked on the stack 102 of the loop end address (the stack is A0 →
An are stacked in the order of An), and as shown near the center of the figure, the data of the number of loops is C0, C1, ..., Cm-1, Cm,
, Cn are stacked on the stack corresponding to the number of loops and indicate the value m of the pointer LS indicating the current loop reference.

First, based on the comparison result of the end address comparison circuit 105 and the judgment result of the loop count / update circuit 131 that the designated number of times has ended, the vector judgment circuit 132 determines that the end address is reached when the current loop ends. Vector amount (Va) and vector amount (Vc) for the number of loops.

The vector amount Va is determined in the shallow direction of the nest (Am- with reference to the end address Am of the current loop).
1, Am-2, ..., A0), the number of nest stages up to an end address different from the end address Am is shown. This is the number of nest stages when the end address Am is the same as the end address of the parent loop.

The vector amount Vc is the designated number of times Cm of the loop.
Is a value indicating the end, the shallow direction (Cm-1, Cm-2, ..., C0) of the nest with reference to the value m of LS.
In the order of), the number of times the loop is specified is the end of the loop.

When the number of nest stages (vector amount) is 2, the vector amount for changing the LS value m at the loop end address Am is as shown on the right side of the figure.
It is as follows.

When Va> Vc When Vc Va = Vc When Va or Vc When Va <Vc Va For other states as well, from the end address comparison result and the determination result of the specified number of times, LS The value m is changed and updated.

Thereafter, the SW counter signal output from the vector determination circuit 132 is used for the PC counter 104 or L.
The loop start address indicated by the value m of LS from the S controller 106 is switched to the value of PC. In the case of this embodiment, there are many types to be updated in the PC, which means multi-branching.

Even in the case of this embodiment, even if the end address of the loop, its parent loop and its parent loop are the same at the address where the loop ends, the execution state of the loop is judged and PC You can set the value of and execute the correct processing according to each branch.

As described above, even if the end addresses of the loops that are continuously nested are the same, the correct branch destination address can be set from the address where the loop ends.

As described above, according to the present invention,
By setting a plurality of addresses to be set in the PC in the control of the loop using hardware, it is possible to perform multi-branching in accordance with the processing state. Therefore, it is possible to eliminate extra time while eliminating unprocessed programs such as NOP instructions used in the conventional technique.

[0070]

As described above, according to the loop control device of the inventions of claims 1 to 3, as described above,
By executing the program by using the start address of the loop indicated by the new stack pointer as the output of the program counter, the end address of the loop can be made the same when the loop of the program is nested. it can.

Particularly, according to the loop control device of the third aspect of the present invention, even when two or more loops are nested, the end address of the loop can be the same.

In the loop control device according to the invention of claim 4, the number of nest stages is indicated by the information bit, so that the control means of the program counter loops from the information bit when there is an instruction indicating the start of the loop. You can judge the nesting of.

According to the loop control device of the fifth aspect of the present invention, the information bit indicates whether or not the end address of the next higher stage is the same. It is possible to judge the nest of a loop from bits.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a diagram showing an operation example of a vector determination circuit 132.

FIG. 4 is a diagram showing an operation of hardware such as a CPU and a DSP in a flowchart.

[Explanation of symbols]

101, 102, 103 stacks, 104 counter, 105 end address comparison circuit, 106 loop stack pointer controller, 107 switch switching determination circuit, 121 parent end address comparison circuit,
122 parent loop number determination circuit, 123 loop number determination / update circuit, 124 nest determination circuit

Claims (5)

[Claims] 1. A loop control device for controlling a loop of the program by controlling a program counter for designating an address of a program to be sequentially executed, which stores a start address of the loop of the program. A second stack for storing the end address of the loop, a third stack for storing the number of times of the loop, an address value by the counter and the second stack The number of executions of the loop is counted according to the match with the end address indicated by the stack pointer, and the number of executions of the loop obtained by the counting is the number of executions of the loop indicated by the stack pointer of the third stack. If the number is the number of times, the end address designated by the stack pointer is the second It compares the same as the end address of a loop of one stage higher instructed by one less of the stack pointer of the stack, when the same result of the comparison, the number of executions of the loop,
When the number of executions of the loop one level higher or equal to the number of executions of the loop higher than this, is equal to the value of the stack pointer, the value of the stack pointer is decreased to 1 or the upper loop, and the loop indicated by the new stack pointer A control device for a loop having a program counter control means for executing the program by using a start address as an output of the program counter. 2. The control means of the program counter, a counter for giving an address of a program to be sequentially executed by counting, a count value of the counter, and an instruction of the stack pointer in the first stack. A switch for switching the start address stored in the position to the output of the program counter, the end address stored in the position designated by the stack pointer in the first stack, and the count value of the counter An end address comparison circuit for determining whether it is equal to the last address of the loop, counting the number of executions of the loop, and the number of executions of the loop obtained by counting is the stack pointer in the first stack. Determines if it is equal to the number of loops stored in the position pointed to by And a loop number determination circuit for determining whether the end address indicated by the stack pointer is equal to the end address of the loop one step higher than the value indicated by the stack pointer in the second stack by one. Parent end address comparison circuit for determining, the execution count of the loop, the parent loop number determination circuit for determining whether the execution count of the loop one step higher than the loop, the end address comparison circuit, the loop A stack pointer controller that decrements the value of the stack pointer by 1 when the results of the determinations of the number of times determination circuit, the parent end address comparison circuit, and the parent loop number determination circuit are equal, Start of loop indicated by new stack pointer decremented by controller Controller of the loop of claim 1, wherein the dress from the switch the execution of the program as an output of the program counter. 3. The control means of the program counter, a counter for giving an address of a program to be sequentially executed by counting, a count value of the counter, and an instruction of the stack pointer in the first stack. A switch for switching the start address stored in the position to the output of the program counter, the end address stored in the position designated by the stack pointer in the first stack, and the count value of the counter An end address comparison circuit for determining whether it is equal to the last address of the loop, counting the number of executions of the loop, and the number of executions of the loop obtained by counting is the stack pointer in the first stack. Determines if it is equal to the number of loops stored in the position pointed to by And a loop number determination circuit for determining whether the end address indicated by the stack pointer is equal to the end address of the upper loop indicated by a value smaller than the value indicated by the stack pointer in the second stack. A parent end address comparison circuit for performing, the number of times the loop is executed, a parent loop number determination circuit for determining whether it is equal to the number of times the upper loop is executed, the end address comparison circuit, the loop number determination circuit And a controller of a stack pointer that decrements the value of the stack pointer by 1 up to the upper loop where the determination result of the parent loop number determination circuit is equal when the parent end address comparison circuit is equal. , A new stack pointer reduced by the controller Controller of the loop of which the start address of the loop from the switching program counter of claim 1, wherein the execution of the program as an output represented. 4. The instruction indicating the start of the loop of the program has an information bit indicating the number of nest stages of the loop, and the control means of the program counter controls when the instruction indicating the start of the loop is received. 2. The loop control device according to claim 1, wherein the loop nest is determined from the information bit. 5. The instruction indicating the start of the loop of the program has an information bit indicating whether or not the end address of the loop is equal to the end address of the next higher stage of the loop, and the control means of the program counter. 2. The loop control device according to claim 1, wherein said loop bit is judged from said information bit when there is an instruction indicating the start of said loop.