JPH0965211A - Correlated double sampling circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate noise due to fluctuation in an output signal of an image pickup device in the correlated double sampling circuit for a solid-state image pickup device. SOLUTION: A solid-state image pickup device 10 is driven by a horizontal transfer pulse 112 and a horizontal reset pulse 111 including jitter and generated from a timing generating circuit 11 to provide an output of a CCD output signal 12, and a feed-through part and a video signal part of the signal 12 has fluctuation due to the jitter of the drive pulses. A delay circuit 13 (14) receives the horizontal transfer pulse 111 (horizontal reset pulse 112) and provides an output of a sampling pulse 131 (141) with the same fluctuation as that of the feed- through part and the video signal part of the signal 12 to a correlated double sampling circuit 15. The correlated double sampling circuit 15 samples and holds the CCD output signal 12 by using the sampling pulses 131, 141. Thus, a video signal without noise due to fluctuation in the CCD output signal 12 is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a correlated double sampling method for reducing noise in a video signal output from the solid-state image pickup device.

[0002]

2. Description of the Related Art A solid-state image pickup device such as a charge-coupled device (CCD) has a two-dimensional matrix of image pickup elements arranged corresponding to pixels constituting one screen, and its column is connected to a vertical transfer section. The vertical transfer unit is connected to the horizontal transfer unit. The CCD transfers the charge of the image sensor on one scanning line from the vertical transfer unit to the horizontal transfer unit in response to the vertical transfer pulse.
In response to the horizontal transfer pulse, the electric charge is transferred to the floating capacitor of the output section, and thus the video signal of one pixel unit is output. The floating capacitor is cleared by the horizontal reset pulse every time the signal of one pixel is output. Therefore, the CCD output signal is composed of, for each pixel, a reset component generated by resetting the floating capacitor, a feedthrough portion on which the correlation noise of the horizontal reset pulse is superimposed, and a video signal portion. The correlated double sampling (CDS) method is a noise removal method that samples and holds the feedthrough portion and the video signal portion of the CCD output signal and inputs them to the differential amplifier, and the correlation noise is removed from the sampled signal. is there.

Japanese Patent Laid-Open No. 35672/1993 teaches a solid-state image pickup device in which a single pulse is generated from a horizontal reset pulse and a horizontal transfer pulse and used as a sampling pulse for correlated double sampling. Japanese Unexamined Patent Publication No. 62-108679 discloses an imaging device in which a pulse having a predetermined phase with respect to a clamp pulse and a reset pulse is used as a sample hold pulse for correlated double sampling.

[0004]

The horizontal transfer pulse and the horizontal reset pulse for driving the CCD and the pulse for driving the preamplifier (correlated double sampling circuit) each include jitter. Noises such as whiskers and ringing generated from the timing signal generator and peripheral circuits at the time of horizontal reset operation and horizontal transfer operation are also randomly mixed in these pulses. The CCD output signal's feed-through part and video signal part, which are output by the CCD in synchronization with these pulses, also have fluctuations due to the jitter of the horizontal reset pulse and horizontal transfer pulse, respectively. If the jitter has periodicity, it appears as a step in the video signal. These are eventually mixed in the video signal as random noise.

When the feed-through portion and the video signal portion of the CCD output signal are sampled and held by the correlated double sampling circuit, another noise other than the correlation noise is mixed in the video signal. If sampling is performed so that the drive pulse of the correlated double sampling keeps a constant timing with respect to the CCD output signal, this can be detected as a constant offset. However, if there is jitter in the drive pulse itself of the correlated double sampling, the amount of this jitter differs between pixels, so it is not removed and is mixed in the video signal as another noise.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide a correlated double sampling method in which noise contamination in a video signal due to jitter of a drive pulse of a charge coupled device is minimized. .

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention proposes that when a charge coupled device is driven, noise such as beard and ringing mixed in a signal is synchronized with a drive pulse of the charge coupled device. In consideration of this, by using the pulse generated in synchronization with the drive pulse of the charge-coupled device as the drive pulse used in the processing system of the CCD output signal such as the correlated double sampling circuit, the influence of jitter is reduced. To remove.

Particularly, according to the following method, the influence of jitter can be completely eliminated. That is, since the charge-coupled device is driven by the horizontal reset pulse and the horizontal transfer pulse, noise synchronized with these two types of pulses is mixed in the signal component. That is, noise synchronized with the horizontal reset pulse is applied to the feedthrough portion and noise is applied to the signal portion with the horizontal transfer pulse. Normally, correlated double sampling is used to generate a video signal, but a pulse synchronized with the horizontal reset pulse is used for the clamp that holds the feedthrough portion, and a horizontal transfer pulse is used for the sample hold that holds the signal portion. Use synchronized pulses. This makes it possible to prevent noise from being mixed into the output video signal due to jitter.

Since the horizontal reset pulse and the horizontal transfer pulse that drive the charge transfer device have jitter, CC
The D output signal has a fluctuation that is synchronized with these drive pulses. According to the present invention, since the delay means generates the pulse of the correlated double sampling from the drive pulse of the charge transfer device, the sampling pulse has the same fluctuation. Since the correlated double sampling means samples and holds the CCD output signal with this sampling pulse having the same fluctuation, it is possible to output the video signal in which the noise which would have been generated by the fluctuation in the prior art is minimized.

According to the present invention, the charge transfer device extracts the feedthrough portion and the video signal portion of the output signal output in response to the horizontal reset pulse and the horizontal transfer pulse by sampling pulses, respectively, and extracts the extracted portions. A correlated double sampling circuit for inputting to a differential amplifier and outputting a video signal includes delay means for delaying a horizontal reset pulse and a horizontal transfer pulse to generate a sampling pulse, and a sampling means for outputting the output signal by the delay means. And sample and hold means for extracting by pulse.

According to the present invention, the correlated double sampling circuit receives the output signal instead of the delay means and generates a sampling pulse from a signal portion of the output signal which is synchronized with the horizontal reset pulse. Delay means may be included.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the correlated double sampling method according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a functional block diagram showing an embodiment of the correlated double sampling system according to the present invention, and FIG. 2 is a diagram showing signal waveforms appearing at respective parts thereof. In the following description, the reference signs of signals are represented by the reference signs of the connecting lines in which they appear.
In this embodiment, a charge coupled device (CCD) is used as an image pickup device.
Having 10. The charge-coupled device 10 is a two-dimensional solid-state image pickup device in this embodiment, and has a two-dimensional matrix (not shown) of image pickup elements arranged corresponding to the pixels forming one screen, and the column thereof is vertical. The vertical transfer unit is connected to the transfer unit, and the vertical transfer unit is connected to the horizontal transfer unit. Charge coupled device
Reference numeral 10 is a floating capacitor (not shown) in the output section, which transfers the charges of the image pickup device on one scanning line from the vertical transfer section to the horizontal transfer section in response to the vertical transfer pulse, and in response to the horizontal transfer pulse 112. , And the video signals in units of one pixel are sequentially output from the output 12. The floating capacitor is cleared by the horizontal reset pulse every time the signal of one pixel is output.

As shown in FIG. 2, in the one pixel period T of the output signal 12, the timing generation circuit (TG) of the charge coupled device 10 is used.
11 is composed of a reset component a synchronized with the horizontal reset pulse 111, a feedthrough portion b, and a video signal portion c synchronized with the horizontal transfer pulse 112. In the following description, signals are designated by the reference signs of the connecting lines in which they appear.

Returning to FIG. 1, this embodiment has two delay circuits.
(DLY) 13 and 14. One delay circuit 13 receives the horizontal reset pulse 111 from the timing generation circuit 11 and outputs a sampling pulse 131 delayed by time t ₁ (FIG. 2) from this pulse 111, and outputs this sampling pulse 131 to a correlated double sampling circuit (CDS). ) It is a delay circuit that outputs to 15. As can be seen from FIG. 2, the length of the delay time t ₁ is selected in this embodiment so that the end of the time t ₁ from the rise of the horizontal reset pulse 111 is sufficiently long in the feedthrough portion b. The other delay circuit 14 includes a timing generation circuit 11
Is a delay circuit for receiving a horizontal transfer pulse 112 from the sampling pulse 141 and delaying this pulse 112 by a time t ₂ and outputting the sampling pulse 141 to the correlated double sampling circuit 15. In this embodiment, the length of the delay time t ₂ is the horizontal transfer pulse 112.
The trailing edge of the time t _{2 from} the trailing edge of is selected so as to sufficiently cover the video signal portion c.

The correlated double sampling circuit 15 samples and holds the feed-through portion b of the CCD output signal 12 in response to the sampling pulse 131 at the above timing,
Further, it is a noise removing circuit which samples and holds the video signal portion c in response to the sampling pulse 141 and outputs these sampled and held signals from its output 143 to a differential amplifier (DAP) (not shown).

FIG. 3 is a waveform diagram during operation of the circuit shown in FIG. As shown in the figure, the horizontal reset pulse 111 and the horizontal transfer pulse 112 may include jitter superimposed from the timing generation circuit 11 and its peripheral circuits. When the charge-coupled device 10 is driven by such a pulse, the feed-through portion b and the video signal portion c of the CCD output signal 12 have noises n1 and n2 due to jitter and fluctuations J1 and J2 as illustrated in FIG. including. Therefore, the delay circuits 13 and 14 generate sampling pulses 131 and 141, which are linearly generated by the jittered pulses 111 and 112, respectively, as shown by the dotted lines in FIG. is there. The correlated double sampling circuit 15 samples the parts b and c of the input signal 12 with the sampling pulses 131 and 141 thus having the corresponding wobbles J1, J2. As a result, the correlated double sampling circuit 15 can output the sample hold signal 143 that cancels the fluctuations J1 and J2. Therefore, the output 143 outputs the video signal in which the noise due to the fluctuation of the CCD output signal is minimized.

FIG. 4 shows a configuration example of the delay circuits 13 and 14 shown in FIG. 1, and FIG. 5 is a waveform diagram showing the operation thereof. FIG.
In, the delay circuits 13 and 14 may have the same configuration except the element value, and have a switch 20 that responds to the horizontal reset pulse 111 or the horizontal transfer pulse 112 from the timing generation circuit 11. Switch 20 is a normally take the connection state shown in the figure, a reset circuit for charging this by connecting a capacitor 23 to a direct current (DC) power supply 21 of the voltage V _C to the voltage V _C. A constant current source circuit 24 is also connected to the capacitor 23. The constant current source circuit 24 has an adjustable output current. Horizontal reset pulse 111 or horizontal transfer pulse 112
Takes a significant state, the switch 20 becomes a non-connection state or an open state, and the capacitor 23 is rapidly discharged at a constant rate by the constant current circuit 24. Further, when the pulse 111 or 112 goes into an insignificant state, the connection state shown in the figure is established and the capacitor 23 is reset to the voltage V _{C of the} power supply 21. Therefore,
The charging voltage of the capacitor 23 takes the form of the waveform 26 shown in FIG.

The output 26 of the capacitor 23 is the pulse generation circuit 25.
Is input to The pulse generation circuit 25 has two threshold voltages V _A
And V _B are set, the charging voltage 26 is set to the threshold voltage V _A and V _B
A delayed pulse 27 having a pulse width W is generated in a section W intersecting with. The delayed pulse 27 becomes the sampling pulses 131 and 141 of the correlated double sampling circuit 15. The threshold voltages V _A and V _B of the pulse generation circuit 25 are variable, and as can be seen, by changing the threshold voltages V _A and V _B ,
Sampling pulse 13 with desired delay time D and pulse width W
You can get 1 and 141. Further, by adjusting the variable constant current source circuit 24 to change the charging current, the sampling pulses 131 and 141 can be similarly made to have a desired delay time D and pulse width W. In this embodiment, the delay pulse is generated by charging the capacitor 23, but the delay pulse can be similarly generated by discharging.

A pulse generating circuit 1 having a structure as shown in FIG.
3 and 14 are suitable for integrated circuits. In addition, if such a circuit is formed by an integrated circuit, the circuit can have high performance,
A compact and low power consumption system can be realized at low cost.

The delay circuit 30 shown in FIG. 6 is another configuration example applied to the delay circuits 13 and 14 in the embodiment shown in FIG. 1, and FIG. 7 shows its signal waveform. The delay circuit 30 has a low-pass filter (LPF) 31, which is a waveform that receives the output pulse 130 separately output by the timing generation circuit 11 in synchronization with the pixel period T and converts it into a sine wave 137. It is a conversion circuit. This sine wave 137 is a high pass filter.
Input to (HPF) 32 and low pass filter (LPF) 33. The high-pass filter 32 has a predetermined phase shift, for example,
The output signal 132 of (-90 + Δ) ° is output to the mixer 33, and the low-pass filter 34 gives a predetermined phase shift, that is, Δ ° in this example, to the input signal 137, and this is given as the signal 134 to the variable gain amplifier. Output to the mixer 33 via 35.

The mixer 33 is controlled by increasing or decreasing the gain of the variable gain amplifier 35.
The mixing ratio of the input signals 132 and 134 in the signal changes, and the delay time D of the output signal 133 of the mixer 33 can be made variable by this. The output 133 of the mixer 33 is connected to the drive input of the pulse generator circuit 36. Pulse generator circuit 36
7 has a threshold voltage V _A for pulse generation, and outputs a sampling pulse 136 with a pulse width W when the voltage of the input signal 133 exceeds the threshold voltage V _A. The pulse generation circuit 36 has a variable threshold voltage V _A , and the pulse width W can be set to a desired value by adjusting this. Thus, a sampling pulse 136 having a delay D and a pulse width W is generated at the output 136. This sampling pulse 136 is used as the sampling pulses 131 and 141 of the correlated double sampling circuit 15. Since the delay circuit 30 having such a configuration handles a small-amplitude analog signal, unlike the delay circuits 13 and 14 shown in FIG. 4, a jump noise is generated from other circuits or another circuit is passed through the clock wiring. There is no defect such as giving noise to.

FIG. 8 is a functional block diagram of another embodiment of the correlated double sampling method according to the present invention, and FIG. 9 is a signal waveform diagram of the circuit shown in FIG. Elements similar to those shown in FIGS. 1 and 2 are designated with the same reference numbers. The circuit of this embodiment has a single delay circuit 60, and its input is a CCD.
It is the same as the embodiment shown in FIG. 1 except that it derives the two sampling pulses 161 and 161 of the correlated double sampling circuit 15 from the output signal 12.

As described above, the reset component a and the feedthrough portion b of the CCD output signal 12 have the fluctuation J1 (FIG. 3) caused by the horizontal reset pulse 111. Delay circuit
The CCD 60 receives the CCD output signal 12, detects the reset component a, and outputs sampling pulses 161 and 162 to the correlated double sampling circuit 15 with delay times D ₁ and D _{2 respectively} from the reset component a. To do. As can be seen from FIG. 9, the length of the delay time D ₁ is selected in this embodiment so that the end of the time D ₁ from the rise of the reset period a is sufficiently long in the feedthrough portion b. Also delay time
In the present embodiment, the length of D ₂ is selected so that the end of time D ₂ from the rise of the reset period a is sufficiently long for the video signal portion c.

The feed-through portion b and the video signal portion c of the CCD output signal 12 have fluctuations J1 and J2, respectively.
It is included. The sampling pulses 161 and 162 generated by the delay circuit 60 from the CCD output signal 12 include the fluctuation J1. The correlated double sampling circuit 15 receives the CCD output signal 12 and samples the feedthrough portion b and the video signal portion c of the CCD output signal 12 in response to the sampling pulses 161 and 162,
The sampled and held output signal 143 is output to the differential amplifier. Therefore, the correlated double sampling circuit 15
Since the CCD output signal 12 is sampled with the sampling pulses 161 and 162 containing the corresponding wobble J1, this wobble J1 can be canceled out for the feedthrough part, which allows the output signal 143 to have a more jitter-impacted image. Become a signal.

As described above, according to the embodiment of the present invention, by performing the correlated double sampling in which the influence of the jitter is eliminated, it is possible to prevent the noise from being mixed into the video signal due to the variation of the sampling position and the pulse width. . Furthermore, since the correlated double sampling is performed by the sampling pulses 131 and 132 synchronized with the driving pulses 111 and 112 of the charge-coupled device 10, the driving pulses 111 and 112 are not generated due to periodic jump noise or sudden jump noise. Even if it fluctuates, it does not affect the output video signal.

Further, conventionally, a pulse for correlated double sampling was separately generated in the timing generation circuit for generating the drive pulse of the charge coupled device, but in the embodiment of the present invention, a pulse for correlated double sampling is generated. It is not necessary to separately generate the pulse in the timing generation circuit 11. for that reason,
Conventionally, the pulse driving was constant, but in the embodiment of the present invention, the pulse for correlated double sampling has an arbitrary delay amount and pulse width regardless of the driving pulses 111 and 112 of the charge-coupled device 10. Can be changed.

[0027]

As described above, according to the present invention, the noise generation due to the fluctuation of the output signal from the charge-coupled device which is the object of sampling in the correlated double sampling method of the solid-state imaging device is minimized, and the solid-state imaging device The image quality of the output video signal can be improved. The present invention can be applied not only to video signals but also to any application as long as it is a charge-coupled device that reads out signals by correlated double sampling.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a configuration of an embodiment of a correlated double sampling method according to the present invention.

FIG. 2 is a time chart useful for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a signal explanatory diagram showing signal fluctuation and noise according to the embodiment.

FIG. 4 is a diagram showing a configuration example of a delay circuit in the embodiment.

5 is a time chart of the delay circuit shown in FIG.

FIG. 6 is a diagram illustrating another configuration example of a delay circuit.

7 is a time chart of the delay circuit shown in FIG.

FIG. 8 is a functional block diagram similar to FIG. 1, showing the configuration of another embodiment of the correlated double sampling method according to the present invention.

9 is a time chart similar to FIG. 2, which is useful for explaining the operation of the embodiment shown in FIG.

[Explanation of symbols]

 10 Charge coupled device 11 Timing generator circuit 13, 14, 30, 60 Delay circuit 15 Correlated double sampling circuit

[Procedure amendment]

[Submission date] September 11, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

FIG. 4 shows a configuration example of the delay circuits 13 and 14 shown in FIG. 1, and FIG. 5 is a waveform diagram showing the operation thereof. FIG.
In, the delay circuits 13 and 14 may have the same configuration except the element value, and have a switch 20 that responds to the horizontal reset pulse 111 or the horizontal transfer pulse 112 from the timing generation circuit 11. Switch 20 is a normally take the connection state shown in the figure, a reset circuit for charging this by connecting a capacitor 23 to a direct current (DC) power supply 21 of the voltage V _C to the voltage V _C. A constant current source circuit 24 is also connected to the capacitor 23. The constant current source circuit 24 has an adjustable output current. Horizontal reset pulse 111 or horizontal transfer pulse 112
When the switch is in an insignificant state, the switch 20 is in a non-connection state, that is, an open state, and the capacitor 23 is charged by the constant current circuit 24 at a constant rate. Also, pulse 111 or 112
Becomes significant , the connection state shown in the figure is established and the capacitor 23 is rapidly reset to the voltage V _{C of the} power supply 21. Therefore,
The charging voltage of the capacitor 23 takes the form of the waveform 26 shown in FIG.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

The delay circuit 30 shown in FIG. 6 is another configuration example applied to the delay circuits 13 and 14 in the embodiment shown in FIG. 1, and FIG. 7 shows its signal waveform. The delay circuit 30 has a low pass filter (LPF) 31, which is a pulse 13 which the timing generation circuit 11 separately outputs in synchronization with the pixel period T.
It is a waveform conversion circuit that receives 0 and converts it to a sine wave 137. This sine wave 137 is a high pass filter (HPF) 32
And low-pass filter (LPF) 33. The high pass filter 32 has a predetermined phase shift, for example (-90 + Δ).
The output signal 132 of ° is output to the mixer 33, and the low-pass filter 34 applies a predetermined phase shift, that is, Δ ° in this example, to the input signal 137, and this is given as the signal 134 via the variable gain amplifier 35 to the mixer 33. Output to.

Claims (6)

[Claims] 1. A feed-through portion and a video signal portion of an output signal output by a charge transfer device in response to a horizontal reset pulse and a horizontal transfer pulse are extracted by sampling pulses, respectively, and the extracted portion is output to a differential amplifier. In a correlated double sampling circuit which inputs and outputs a video signal, the circuit delays the horizontal reset pulse and the horizontal transfer pulse to generate the sampling pulse, and the output signal of the delay unit. A correlated double sampling circuit, comprising: a sampling and holding means for sampling with an output sampling pulse. 2. A charge transfer device extracts a feedthrough portion and a video signal portion of an output signal output in response to a horizontal reset pulse and a horizontal transfer pulse by sampling pulses, respectively, and extracts the extracted portion to a differential amplifier. In a correlated double sampling circuit that inputs and outputs a video signal, the circuit includes a delay unit that receives the output signal and that generates the sampling pulse from a signal portion of the output signal that is synchronized with the horizontal reset pulse. A correlated double sampling circuit, comprising: sample-hold means for extracting the output signal with a sampling pulse output from the delay means. 3. The circuit according to claim 1 or 2, wherein the delay means has a capacity, and a charging / discharging means for charging / discharging the capacity, and two threshold values for charging the charging / discharging means. Or detecting a first time point and a second time point that intersect the amount of discharge, and delay time substantially equal to a period from the start of charging / discharging to the first time point, and a time interval between the first time point and the second time point. And a pulse generating means for generating the sampling pulse with a pulse width substantially equal to the correlation double sampling circuit. 4. The correlated double sampling circuit according to claim 3, wherein at least one of the first and second threshold values of the pulse generating means is variable. 5. The circuit according to claim 1 or 2, wherein the delay means is a first reset signal from the horizontal reset pulse or the horizontal transfer pulse.
And a second sine wave generating means for generating a sine wave of the first and second sine waves whose phase is shifted from the first sine wave by a predetermined angle.
And a pulse generating means for mixing the first and second sine waves at a desired mixing ratio to generate a sampling pulse having a phase delay from the horizontal reset pulse or the horizontal transfer pulse. A correlated double sampling circuit including: 6. The correlated double sampling circuit according to claim 5, wherein the pulse generating means has a variable mixing ratio.