JPH0965145A - Picture signal decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate processing time to a level similar to the case of performing decoding by an optional picture element number while performing decoding by a simple circuit by interrupting decoding when the picture element number of decoding completed picture elements reaches the picture element number of one line informed before decoding is started while decoding one line. SOLUTION: The picture element number of the decoding block length of a decoding circuit 10 is M picture elements. A picture signal memory 12 tentatively stores picture signals after decoding and the picture signals 15 for the picture element number L are outputted corresponding to information for indicating the picture element number L of one line from a line register 7. An output counter 13 counts decoding completed picture element number information 14 and outputs the counted information 16 to a decoding control circuit 11. The decoding control circuit 11 compares the information of the picture element number L of one line from the line register 7 with the counted information 16 from the output counter 13 and outputs interruption signals 17 for instructing the interruption of decoding when they match or when the counted information 16 becomes larger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal decoding circuit, and more particularly to an image signal decoding device for decoding an encoded image signal obtained by encoding an image signal having a variable length of one line.

[0002]

2. Description of the Related Art Conventionally, the length of one scanning line when manipulating an original is fixed as in the case of a facsimile, whereas the compression block length of an image compression device incorporated therein is also fixed, which causes a problem. There wasn't. On the other hand, the length of one scanning line can be changed, and the number of pixels in one block (the number of pixels in one line or the number of some pixels in one line) of an input image signal can be changed according to the size of a document or a figure. In this case, it is necessary that the compression block length of the image compression device (the number of pixels of one block to be compression-encoded by the compression device) is variable. However, such an image compression apparatus has a drawback that the circuit becomes complicated. Therefore, even if the one block length of the image signal is variable, a coding device and a decompressing device that perform compression coding using the same image compression device as in the case where the one block length of the image signal is not variable and decompress it into the original image are provided. , JP-A-56-154874.

The image signal encoding circuit disclosed in this publication is designed so that the number of pixels of an input image signal of an arbitrary number L of pixels in one line matches a fixed number M of pixels in one line (M
-L) pixels of fixed level values (for example, white pixels) are added to generate an image signal of the number of pixels M, and the image signal is encoded. M is the number of 1-block-length pixels (compressed block length) of pixels to be compressed by the encoding circuit. When the compressed and generated encoded data is decoded, a fixed one-line image signal of M pixels of one line is obtained by the decompression circuit, and then the original image signal of the number L of one-line pixels is extracted from the M pixels. .

[0004]

The first problem of the above-mentioned prior art is that after a fixed image signal of M pixels of one line is obtained, the number of pixels L of any one line is selected from the M pixels. The fact that the image signal is taken out lowers the decoding efficiency when the number L of pixels in one arbitrary line is extremely small. The reason is that when the image signal in which the number of pixels L in one line is arbitrarily changed is handled and the difference from the number of pixels L in the fixed one line is not extremely large,
There is almost no effect, and there is the effect that the circuit can be made a simple configuration by decoding with fixed pixels, but when the difference from the number of pixels L is extremely large, it is actually unnecessary (M
-L) This is because the influence of the pixel decoding time appears significantly.

The picture signal decoding apparatus according to the present invention has (ML) fixed level value pixels until a fixed number M of pixels of one line is obtained for an input picture signal of an arbitrary number L of pixels of one line. In a decoding device that decodes encoded data after adding, while performing decoding with a simple circuit,
The purpose is to speed up the processing time to the same level as when decoding is performed with an arbitrary number of pixels.

[0006]

According to the picture signal decoding apparatus of the present invention, for an input picture signal of an arbitrary pixel number L of one line, the number of picture elements is fixed (M−L). In the decoding device for decoding the encoded data after adding the pixel of the fixed level value of, while decoding one line, the number of pixels of the decoding completion pixel is When the number of pixels L of one line notified from the higher-level device is reached, the decoding is interrupted so that the decoding can be performed with a simple circuit by using a fixed coding block length, but with an arbitrary number of pixels. The processing time is shortened to the same level as when decoding is performed.

More specifically, the picture signal decoding apparatus has (ML) fixed levels for an input picture signal of an arbitrary number L of pixels per line until the number M of pixels of a fixed line is reached. In a decoding device that decodes encoded data that has been encoded after adding value pixels, a line register that stores the number of pixels L of one line at the time of outputting an image signal input from a higher-level device, and an input from the higher-level device A coded data memory that stores a fixed amount of coded data, an output counter that counts the number of pixels after decoding, and a decoding control circuit that instructs the interruption of decoding when the line register and the output counter are compared and match. And a decoding circuit capable of interrupting decoding in accordance with an interruption instruction from the decoding control circuit, and an image signal memory for temporarily storing the image signal after decoding.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

According to the embodiment of the present invention, when the number of pixels for which decoding has been completed reaches the number of pixels for one line L notified from the host device before the start of decoding while decoding one line, By suspending decoding, the decoding processing time is shortened to the same level as when decoding with an arbitrary number of pixels, while performing decoding with a simple circuit that uses a fixed coding block length. .

FIG. 1 is a block diagram of an encoding device corresponding to the image signal decoding device according to the present invention. In the figure, an input image signal 1 is an image signal of 1 line L pixels output from an image input device, an image processing system, or the like. For example, A
When scanning 4 sizes at 8 lines / mm, L is 172
It becomes 8. The pixel signal addition unit 2 has a number of pixels for the input image signal 1 that is the compression block length M (for example, 2) of the compression unit 4.
(M−L) pixels are added so as to match 048), and the image signal 3 of a total of M pixels is output to the compression unit 4. However, M ≧ L. The signals of the (ML) number of pixels to be added are preferably white pixel signals. In general, in the case of a signal obtained by scanning a document, the end of one line is often white, and when run length coding is used as the compression coding method of the compression unit 4, the length of the last white run. The number of orchids does not change, although it is slightly longer. Therefore, the compression encoding efficiency is almost the same as when the compression block length is fixed.

The compression unit 4 has M that matches the compression block length.
The pixel image signal 3 is subjected to compression processing, and compression encoded data 5 is output. In the case of a facsimile machine, this compression-coded data is sent to a transmission line after being modulated by a modulation circuit or as a high speed digital signal.

FIG. 2 is a block diagram of a picture signal decoding apparatus which is an embodiment of the present invention with respect to the coding apparatus of FIG. Referring to FIG. 2, the embodiment of the present invention includes a line register 7 for storing the number L of pixels per line received as control information 6 from a receiving circuit or another higher-level device, and a compression code from the encoding device of FIG. The coded data memory 8 that stores the same amount of data as the coded data 5 in a fixed amount, the decoding circuit 10 that reads the content of the coded data memory and decodes the original image signal, and the 1 stored in the line register 7. A decoding control circuit 11 for controlling decoding based on the line pixel number L and the output of the output counter 13, an image signal memory 12,
And an output counter 13.

The decoding circuit 10 decodes the compression coded data and outputs it to the image signal memory 12, and also outputs the number of pixels for which decoding has been completed as the decoding completed pixel number information 14. The number of pixels of the decoding block length of the decoding circuit 10 is M pixels. The image signal memory 10 temporarily stores the decoded image signal, and outputs the image signal 15 for the number L of pixels according to the information indicating the number L of pixels per line from the line register 7. The output counter 13 counts the decoding completed pixel number information 14, and the decoding control circuit 3 receives the count information 16
Is output. The decoding control circuit 11 uses the line register 7
The information of the number of pixels L of one line from the above and the count information 16 from the output counter 13 are compared, and when they match or the count information 16 becomes larger, the interruption signal 17 for instructing the interruption of the decoding is output. The decoding circuit 10 interrupts the decoding in accordance with the interruption signal 11 from the decoding control circuit 3.
Next, the operation will be described in detail with reference to the block diagram of FIG. 2 and the operation flowchart of FIG.

When the decoding process is started, first, the number of pixels L of an arbitrary line is input from the host device and the line register 7 is input.
(Process 101). Next, the compression coded data is started to be input from the host device and stored in the coded data memory 8 (process 102). When the compression coded data is accumulated in the coded data memory 8 for one line or more, the decoding circuit 10 starts the decoding (process 103). After starting the decoding, the decoding circuit 10 outputs the decoding completed pixel number information 14 while accumulating the image signal of the decoding completed pixel in the image signal memory 12. The output counter 13 counts the decoding completion pixel number information 14, and the decoding control circuit 11 compares this count value with the pixel number L of any one line from the line register 7 to obtain the decoding completion pixel number. When the count value of is smaller than L, the decoding is continued (processing 104N), and when the decoding completed pixel matches L or becomes larger than L (processing 10).
4Y), the interruption signal 17 for instructing the interruption of decoding is given to the decoding circuit 10 to interrupt the decoding (process 105). As a result, when the decoding circuit 10 decodes the image signal for L pixels of one line, the decoding circuit 10 stops the decoding and does not decode the image signal of the additional pixel for (ML) pixels. .

When the coded data memory 8 contains the image signal of the decoding completion for the number L of pixels of the next one line, the decoding circuit 10 controls the image signal memory 12 to generate the image signal. The decoded image signal of the current line stored in the memory is read and output (process 106). Furthermore, the decoding circuit 1
0 indicates that data of a line that has not been decoded is stored in the encoded data memory 8, that is, if the input data is not decoded for all lines (process 107).
N), returning to the decoding start operation (process 103) to restart the decoding, and when the decoding of all lines is completed (process 107Y), the process ends.

[0016]

As described above, according to the present invention, the number of pixels in one line after decoding can be arbitrarily set by the host device, and the decoding process is interrupted when decoding is performed up to the set number of pixels. As a result, even if the number of pixels in any one line is much smaller than the number of pixels in a fixed one line, efficient decoding can be performed. The reason is that even if the number of pixels in any one line is extremely small with respect to the number of pixels in a fixed one line, the decoding process is interrupted at the time when the decoding reaches any one line in the present invention. By doing so, the processing time does not decrease because the decoding from the arbitrary one-line pixel to the fixed one-line pixel is not performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a picture signal encoding device corresponding to a picture signal decoding circuit according to the present invention.

FIG. 2 is a block diagram showing a picture signal decoding circuit which is an optimum embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of the image signal decoding circuit shown in FIG.

[Explanation of symbols]

 5 Input Data 6 Control Information 7 Line Register 8 Encoded Data Memory 10 Decoding Circuit 11 Decoding Control Circuit 12 Image Signal Memory 13 Output Memory 14 Decoding Complete Pixel Number Information 15 Image Signal

Claims (3)

[Claims] 1. A fixed number of pixels M per line for an input image signal having an arbitrary number L of pixels per line (ML).
In a decoding device that decodes coded data that has been coded after adding pixels of fixed number of fixed level values, while decoding one line, the number of pixels of decoding completed pixels is before the decoding starts. An image signal decoding apparatus characterized in that, when the number of pixels L of one line notified in advance is reached, decoding is interrupted. 2. For an arbitrary input image signal of the number L of pixels on one line, a fixed number M of pixels on one line is obtained (ML).
In a decoding device for decoding coded data that has been coded after adding pixels of fixed number of fixed level values, means for storing the number L of pixels of one line notified in advance, and storing a certain amount of coded data An encoded data memory, counting means for counting the number of pixels after decoding, a decoding control circuit for instructing interruption of decoding when the count value of the counter reaches the number of pixels L, the encoding A picture signal decoding device including: a decoding circuit for decoding the encoded data from the data memory, interrupting the decoding in accordance with an interruption instruction from the decoding control circuit, and decoding the image signal of the next line. . 3. An image signal memory for accumulating an image signal decoded by the decoding circuit, wherein the encoding circuit stores the content stored in the image signal memory when an interruption of the encoding is instructed. The image signal decoding apparatus according to claim 2, wherein the image signal decoding apparatus issues an instruction to read.