JPH096440A - Rush current prevention circuit - Google Patents
Rush current prevention circuitInfo
- Publication number
- JPH096440A JPH096440A JP7151416A JP15141695A JPH096440A JP H096440 A JPH096440 A JP H096440A JP 7151416 A JP7151416 A JP 7151416A JP 15141695 A JP15141695 A JP 15141695A JP H096440 A JPH096440 A JP H096440A
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- JP
- Japan
- Prior art keywords
- circuit
- capacitor
- power
- current
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は突入電流防止回路に係わ
り、特にスイッチング電源の入力ラインにＦＥＴを直列
に接続し、該ＦＥＴのゲート電圧をコンデンサの充電電
圧で制御して電源接続時における突入電流を抑圧する突
入電流防止回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inrush current prevention circuit, and in particular, an FET is connected in series to an input line of a switching power source, and the gate voltage of the FET is controlled by a charging voltage of a capacitor to inrush the power source. The present invention relates to an inrush current prevention circuit that suppresses a current.
【０００２】[0002]
【従来の技術】スイッチング電源等の電源とよばれるも
のには、入力フィルタに大容量コンデンサが接続されて
おり、電源投入時に瞬間的に過大な電流が流れ、入力ヒ
ューズの溶断やブレーカのトリップ、入力コネクタの溶
着等の物理的障害、又、その際に電流変化によってノイ
ズが混入し装置障害を誘発する恐れがある。このため、
スイッチング電源ではこの電源投入時における突入電流
を抑制する必要がある。2. Description of the Related Art In what is called a power supply such as a switching power supply, a large-capacity capacitor is connected to an input filter, and when a power supply is turned on, an excessively large current flows momentarily, and the input fuse is blown or a breaker trips. There is a possibility that a physical obstacle such as welding of the input connector, or noise at the time due to a change in current may mix in and cause a trouble in the device. For this reason,
In a switching power supply, it is necessary to suppress the inrush current when the power is turned on.
【０００３】図８は突入電流防止回路を備えた従来のス
イッチング電源の構成図である。図中、１は直流電源、
２はスイッチ、３は負荷に並列に接続される大容量のコ
ンデンサ、４はトランス、５はチョッピング用のスイッ
チを構成するＦＥＴ、６は負荷、７は整流平滑回路であ
り、トランス４の二次側交流電圧を整流、平滑化して一
定の直流電圧を負荷に供給するものである。ＦＥＴ５を
オン・オフして、直流電源１から供給される直流電圧を
チョッピングすると、オン時間に応じて負荷に供給する
直流電圧を制御できる。従って、負荷電圧を検出し、該
負荷電圧と希望直流電圧とを比較し、負荷電圧が小さく
なるとＦＥＴ５をオンし、負荷電圧が大きくなるとＦＥ
Ｔ５をオフすることにより負荷６に一定の希望直流電圧
を供給できる。８は電源接続時における突入電流を抑圧
する突入電流防止回路であり、８ａはスイッチング電源
の入力ラインに直列に接続されたＦＥＴ、８ｂは該ＦＥ
Ｔのゲート電圧を充電電圧により制御するコンデンサ、
８ｃは抵抗であり、コンデンサ８ｂとでＣＲ時定数回路
を構成するもの、８ｄは放電抵抗、８ｅはツェナーダイ
オードである。FIG. 8 is a block diagram of a conventional switching power supply having an inrush current prevention circuit. In the figure, 1 is a DC power supply,
Reference numeral 2 is a switch, 3 is a large-capacity capacitor connected in parallel to a load, 4 is a transformer, 5 is an FET that constitutes a switch for chopping, 6 is a load, and 7 is a rectifying / smoothing circuit. It rectifies and smoothes the side AC voltage and supplies a constant DC voltage to the load. By turning on / off the FET 5 and chopping the DC voltage supplied from the DC power supply 1, the DC voltage supplied to the load can be controlled according to the ON time. Therefore, the load voltage is detected, the load voltage is compared with the desired DC voltage, the FET 5 is turned on when the load voltage becomes small, and the FE becomes large when the load voltage becomes large.
A constant desired DC voltage can be supplied to the load 6 by turning off T5. Reference numeral 8 is an inrush current prevention circuit that suppresses inrush current when the power supply is connected, 8a is an FET connected in series to the input line of the switching power supply, and 8b is the FE.
A capacitor that controls the gate voltage of T by the charging voltage,
Reference numeral 8c is a resistor, which forms a CR time constant circuit with the capacitor 8b, 8d is a discharge resistor, and 8e is a Zener diode.
【０００４】電源投入時、コンデンサ８ｂの充電電圧は
図９（ａ）に示すようにＣＲ時定数回路の時定数ＣＲ1
に応じて指数関数的に増大し、それに応じてＦＥＴ８ａ
の導通度、換言すれば、ドレイン・ソース間の抵抗値が
∞からオン抵抗値まで変化する。これにより、ＦＥＴ８
を流れる電流が漸増し、電源投入時における突入電流を
抑圧できる。一方、電源切断時には、コンデンサ８ｂの
充電電荷は放電抵抗８ｄを介して時定数ＣＲ2により放
電される。When the power is turned on, the charging voltage of the capacitor 8b is, as shown in FIG. 9 (a), the time constant CR 1 of the CR time constant circuit.
Exponentially increasing in accordance with the
In other words, the resistance value between the drain and the source changes from ∞ to the on resistance value. As a result, FET8
The current that flows through the power supply gradually increases, and the inrush current when the power is turned on can be suppressed. On the other hand, when the power is turned off, the electric charge charged in the capacitor 8b is discharged through the discharging resistor 8d with the time constant CR 2 .
【０００５】[0005]
【発明が解決しようとする課題】以上のように従来の突
入電流防止回路によれば、電源投入時における突入電流
を抑圧できる。しかし、電源断時には（図９の時刻ｔ0
参照）、コンデンサ８ｂの端子電圧は時定数ＣＲ2で指
数関数的に漸減し、時刻ｔ1になってやっとＦＥＴ８ａ
のスレッショールドレベルＶTH以下になる。すなわち、
電源切断時には時間（ｔ1−ｔ0）が経過しないとＦＥＴ
８ａはオフしない。このため、図９（ｂ）に示すよう
に、電源の瞬断（瞬間的に電源オフ、しかる後、直ちに
電源オンする状態）が発生すると、ＦＥＴ８ａがオフす
る前に再び電源がオンする状況になり、大きな突入電流
が流れてしまう。以上より、従来は突入電流防止回路が
ついているにもかかわらず電源瞬断時には突入電流が流
れ、回路の入力部を完全に防止しきれないという問題が
あった。従って、本発明の目的は、電源瞬断時における
コンデンサの放電時間を早くし、ＦＥＴのリセットを瞬
時に行うことにより、電源瞬断時における突入電流の発
生を防止でき、回路上に発生するノイズを軽減し、安全
で誤動作のない安定化電源を提供することである。As described above, the conventional inrush current prevention circuit can suppress the inrush current when the power is turned on. However, when the power is turned off (time t 0 in FIG. 9).
See), the terminal voltage of the capacitor 8b is exponentially decreasing with the time constant CR 2, when doing so at time t 1 FET 8a
Threshold level V TH or less. That is,
When the power is turned off, the time (t 1 −t 0 ) must elapse before the FET
8a does not turn off. Therefore, as shown in FIG. 9B, when the power is momentarily cut off (the power is momentarily turned off and then immediately turned on), the power is turned on again before the FET 8a is turned off. And a large inrush current will flow. From the above, there has been a problem that, although the conventional inrush current prevention circuit is provided, an inrush current flows at the time of a momentary power failure and the input portion of the circuit cannot be completely prevented. Therefore, an object of the present invention is to shorten the discharge time of the capacitor at the time of a power supply interruption and to instantaneously reset the FET, thereby preventing the occurrence of an inrush current at the time of a power supply interruption and to prevent the noise generated on the circuit. Is to provide a stable and safe malfunction-free stabilized power supply.
【０００６】[0006]
【課題を解決するための手段】図１は本発明の原理説明
図であり、（ａ）は構成図、（ｂ，（ｃ）は波形図であ
る。１１は直流電源、１２はスイッチ、１３は負荷に並
列に接続される大容量のコンデンサ、２０は電源接続時
における突入電流を抑圧する突入電流防止回路である。
突入電流防止回路２０において、２１はスイッチング電
源の入力ラインに直列に接続されたＦＥＴ、２２は該Ｆ
ＥＴのゲート電圧を充電電圧により制御するコンデン
サ、２３はコンデンサ２２に充電電流を供給する電流供
給回路、２４はコンデンサに並列に接続されたトランジ
スタ等のスイッチング素子、２５はコンデンサ２２の充
放電を制御する充放電制御回路である。1 is a diagram for explaining the principle of the present invention, in which (a) is a configuration diagram, (b, (c) are waveform diagrams, 11 is a direct current power source, 12 is a switch, and 13 is a switch. Is a large-capacity capacitor connected in parallel to the load, and 20 is an inrush current prevention circuit that suppresses an inrush current when the power source is connected.
In the inrush current prevention circuit 20, 21 is an FET connected in series to the input line of the switching power supply, and 22 is the F
A capacitor that controls the gate voltage of ET by a charging voltage, 23 is a current supply circuit that supplies a charging current to the capacitor 22, 24 is a switching element such as a transistor connected in parallel to the capacitor, and 25 is a capacitor 22 that controls charging and discharging. It is a charging / discharging control circuit.
【０００７】[0007]
【作用】充放電制御回路２５は、電源接続時にスイッチ
ング素子２４をオフし、電流供給回路２３からの電流に
よりコンデンサ２２を充電させる。又、充放電制御回路
２５は、電源切断時にスイッチング素子２４をオンし、
コンデンサ２２の充電電荷を該スイッチング素子を介し
て瞬時に放電させる。これにより、電源投入時には、Ｆ
ＥＴ２１のドレイン・ソース間の抵抗値が∞からオン抵
抗値まで変化し、電源投入時における突入電流を抑圧す
る。一方、電源切断時（時刻ｔ0）には、スイッチング
素子２４を介してコンデンサ２２の充電電荷が瞬時に放
電し、ＦＥＴ２１のゲート電圧は時刻ｔ1でスレッショ
ールドレベルＶTH以下になり、該ＦＥＴ２１を瞬時にリ
セットする。この結果、電源切断後、直ちに電源が接続
（時刻ｔ2）されても、既にＦＥＴ２１はリセットされ
ているため、突入電流を抑圧できる。The charge / discharge control circuit 25 turns off the switching element 24 when the power supply is connected, and charges the capacitor 22 with the current from the current supply circuit 23. Further, the charge / discharge control circuit 25 turns on the switching element 24 when the power is cut off,
The electric charge charged in the capacitor 22 is instantly discharged through the switching element. As a result, when the power is turned on, F
The resistance value between the drain and source of the ET21 changes from ∞ to the on-resistance value, and suppresses the inrush current when the power is turned on. On the other hand, when the power is turned off (time t 0 ), the electric charge charged in the capacitor 22 is instantaneously discharged via the switching element 24, and the gate voltage of the FET 21 becomes equal to or lower than the threshold level V TH at time t 1. The FET 21 is instantly reset. As a result, even if the power source is connected (time t 2 ) immediately after the power source is turned off, the FET 21 has already been reset, so that the inrush current can be suppressed.
【０００８】[0008]
（Ａ）本発明の第１実施例 図２は本発明の突入電流防止回路を備えたスイッチング
電源の要部構成図である。１１は直流電源、１２はスイ
ッチ、１３は負荷（図示せず）に並列に接続される大容
量のコンデンサ、２０は電源接続時における突入電流を
抑圧する突入電流防止回路である。突入電流防止回路２
０において、２１はスイッチング電源の入力ラインに直
列に接続されたＦＥＴ、２２は該ＦＥＴのゲート電圧を
充電電圧により制御するコンデンサ、２３はコンデンサ
２２に充電電流を供給する電流供給回路（抵抗）であ
り、コンデンサ２２とでＣＲ時定数回路を構成する。２
４はコンデンサに並列に接続されたＰＮＰトランジス
タ、２５はコンデンサ２２の充放電を制御する充放電制
御回路、２６はツェナーダイオードである。(A) First Embodiment of the Present Invention FIG. 2 is a configuration diagram of a main part of a switching power supply provided with an inrush current prevention circuit of the present invention. Reference numeral 11 is a DC power supply, 12 is a switch, 13 is a large-capacity capacitor connected in parallel to a load (not shown), and 20 is an inrush current prevention circuit for suppressing an inrush current when the power supply is connected. Inrush current prevention circuit 2
In 0, 21 is an FET connected in series to the input line of the switching power supply, 22 is a capacitor that controls the gate voltage of the FET by the charging voltage, and 23 is a current supply circuit (resistor) that supplies a charging current to the capacitor 22. Yes, the capacitor 22 forms a CR time constant circuit. Two
Reference numeral 4 is a PNP transistor connected in parallel with the capacitor, 25 is a charge / discharge control circuit for controlling charge / discharge of the capacitor 22, and 26 is a Zener diode.
【０００９】充放電制御回路２５は、抵抗２５ａ，２５
ｂで構成された抵抗分圧回路とダイオード２５ｃを有し
ている。抵抗分圧回路はコンデンサ２２と並列に接続さ
れ、抵抗で分圧した電圧をトランジスタ２４のベースに
入力する。ダイオード２５ｃは、トランジスタ２４のエ
ミッタと抵抗分圧回路の接続ラインに直列に接続され、
電源接続時に純バイアスされ、電源切断時に逆バイアス
されるようになっている。又、抵抗２５ａの降下電圧は
ダイオード２５ｃの降下電圧（例えば０．６Ｖ）以下で
ある。The charge / discharge control circuit 25 includes resistors 25a and 25a.
It has a resistance voltage dividing circuit constituted by b and a diode 25c. The resistance voltage dividing circuit is connected in parallel with the capacitor 22, and the voltage divided by the resistance is input to the base of the transistor 24. The diode 25c is connected in series with the connection line of the emitter of the transistor 24 and the resistance voltage dividing circuit,
It is designed to be purely biased when the power is connected and reverse biased when the power is turned off. The voltage drop across the resistor 25a is less than or equal to the voltage drop across the diode 25c (eg, 0.6V).
【００１０】電源投入時、トランジスタ２４のベース・
エミッタ間は逆バイアスされるから、該トランジスタ２
４はオフし、コンデンサ２３は電流供給回路（抵抗）２
３を介して時定数ｃｒで充電される。コンデンサ２２ｂ
の充電電圧は図３に示すように時定数ｃｒに応じて指数
関数的に増大し、それに応じてＦＥＴ２１の導通度、換
言すれば、ドレイン・ソース間の抵抗値が∞からオン抵
抗値まで変化する。これにより、ＦＥＴ２１を流れる電
流が漸増し、電源投入時における突入電流が抑圧され
る。一方、電源切断時には、トランジスタ２４がオンす
る。このため、コンデンサ２２のの充電電荷は図３に示
すように瞬時に放電し、ＦＥＴ２１のゲート電圧はスレ
ッショールドレベルＶTH以下になり、ＦＥＴ２１は瞬時
にリセットされる。従って、以後、電源が接続されて
も、既にＦＥＴはリセットされているため、突入電流を
抑圧できるWhen the power is turned on, the base of the transistor 24
Since the emitter is reverse biased, the transistor 2
4 is turned off, and the capacitor 23 is a current supply circuit (resistor) 2
It is charged with a time constant cr via 3. Capacitor 22b
3, the charging voltage of the FET 21 increases exponentially according to the time constant cr, and accordingly, the conductivity of the FET 21, that is, the resistance value between the drain and the source changes from ∞ to the ON resistance value. To do. As a result, the current flowing through the FET 21 gradually increases, and the rush current when the power is turned on is suppressed. On the other hand, when the power is turned off, the transistor 24 is turned on. Therefore, the charge of the capacitor 22 is instantly discharged as shown in FIG. 3, the gate voltage of the FET 21 becomes lower than the threshold level V TH , and the FET 21 is instantly reset. Therefore, after that, even if the power supply is connected, since the FET has already been reset, the inrush current can be suppressed.
【００１１】（Ｂ）本発明の第２実施例 図４は本発明の第２実施例の突入電流防止回路を備えた
スイッチング電源の要部構成図であり、図２の第１実施
例と同一部分には同一符号を付している。第２実施例に
おいて、第１実施例と異なる点は電流供給回路２３の構
成である。第１実施例では電流供給回路２３をＣＲ時定
数回路を構成する抵抗で構成したが、第２実施例では電
流供給回路２３を定電圧源構成としている。電流供給回
路２３において、２３ａはＰＮＰトランジスタ、２３ｂ
はトランジスタ２３ａのベースに一定の電圧を入力する
ツェナーダイオード、２３ｃ，２３ｄは抵抗である。電
流供給回路２３は電源投入時、一定の電流をコンデンサ
２２に供給し、該コンデンサの端子電圧を直線的に増加
する。これにより、ＦＥＴ２１のゲート電圧も直線的に
増加してスレッショールドレベルＶTHになるまでドレイ
ン・ソース間の抵抗値は∞からオン抵抗値まで変化し、
ＦＥＴ２１を流れる電流が漸増し、電源投入時における
突入電流が抑圧される。尚、電源切断時における動作は
第１実施例と同様である。図５は第２実施例の変形例で
あり、放電用のトランジスタ２４をダーリントン接続構
成にして放電時間を早めたものである。(B) Second Embodiment of the Present Invention FIG. 4 is a block diagram of the main part of a switching power supply having an inrush current prevention circuit according to a second embodiment of the present invention, which is the same as the first embodiment of FIG. The same reference numerals are given to the parts. The second embodiment differs from the first embodiment in the configuration of the current supply circuit 23. In the first embodiment, the current supply circuit 23 is composed of the resistors forming the CR time constant circuit, but in the second embodiment, the current supply circuit 23 is a constant voltage source structure. In the current supply circuit 23, 23a is a PNP transistor, and 23b.
Is a Zener diode for inputting a constant voltage to the base of the transistor 23a, and 23c and 23d are resistors. When the power is turned on, the current supply circuit 23 supplies a constant current to the capacitor 22 and linearly increases the terminal voltage of the capacitor. As a result, the gate voltage of the FET 21 also increases linearly and the resistance value between the drain and source changes from ∞ to the on resistance value until the threshold level V TH is reached,
The current flowing through the FET 21 gradually increases, and the inrush current when the power is turned on is suppressed. The operation when the power is turned off is the same as in the first embodiment. FIG. 5 shows a modification of the second embodiment, in which the discharging transistor 24 is arranged in a Darlington connection to shorten the discharging time.
【００１２】（Ｃ）本発明の第３実施例 図６は本発明の第３実施例の突入電流防止回路を備えた
スイッチング電源の要部構成図であり、図２の第１実施
例と同一部分には同一符号を付している。第３実施例に
おいて、第１実施例と異なる点は電流供給回路２３の構
成である。第２実施例では電流供給回路２３を定電流源
構成としている。電流供給回路２３において、２３ａ′
はＮＰＮトランジスタ、２３ｂ′はトランジスタ２３
ａ′のベースに一定の電圧を入力するツェナーダイオー
ド、２３ｃ′，２３ｄ′は抵抗である。電流供給回路２
３は電源投入時、一定の電流をコンデンサ２２に供給
し、該コンデンサの端子電圧を直線的に増加する。これ
により、ＦＥＴ２１のゲート電圧も直線的に増加してス
レッショールドレベルＶTHになるまでドレイン・ソース
間の抵抗値は∞からオン抵抗値まで変化し、ＦＥＴ２１
を流れる電流が漸増し、電源投入時における突入電流が
抑圧される。尚、電源切断時における動作は第１実施例
と同様である。図７は第３実施例の変形例であり、放電
用のトランジスタ２４をダーリントン接続構成にして放
電時間を早めたものである。以上、本発明を実施例によ
り説明したが、本発明は請求の範囲に記載した本発明の
主旨に従い種々の変形が可能であり、本発明はこれらを
排除するものではない。(C) Third Embodiment of the Present Invention FIG. 6 is a block diagram of a main part of a switching power supply having an inrush current prevention circuit according to a third embodiment of the present invention, which is the same as the first embodiment of FIG. The same reference numerals are given to the parts. The third embodiment differs from the first embodiment in the configuration of the current supply circuit 23. In the second embodiment, the current supply circuit 23 has a constant current source configuration. In the current supply circuit 23, 23a '
Is an NPN transistor, and 23b 'is a transistor 23.
Zener diodes 23c 'and 23d' for inputting a constant voltage to the base of a'are resistors. Current supply circuit 2
3 supplies a constant current to the capacitor 22 when the power is turned on, and linearly increases the terminal voltage of the capacitor 22. As a result, the gate voltage of the FET 21 also linearly increases and the resistance value between the drain and the source changes from ∞ to the on resistance value until the threshold level V TH is reached.
The current flowing through the power supply gradually increases, and the rush current at power-on is suppressed. The operation when the power is turned off is the same as in the first embodiment. FIG. 7 shows a modified example of the third embodiment, in which the discharging transistor 24 has a Darlington connection configuration to shorten the discharging time. Although the present invention has been described above with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention described in the claims, and the present invention does not exclude these.
【００１３】[0013]
【発明の効果】以上本発明によれば、スイッチング電源
の入力ラインに直列に接続されたＦＥＴと、該ＦＥＴの
ゲート電圧を充電電圧で制御するコンデンサと、コンデ
ンサに充電電流を供給する電流供給回路と、コンデンサ
に並列に接続されたスイッチング素子と、コンデンサの
充放電を制御する充放電制御回路とにより突入電流防止
回路を構成し、電源接続時にスイッチング素子をオフ
し、前記電流供給回路からの電流によりコンデンサを充
電させると共に、電源切断時にスイッチング素子をオン
し、コンデンサの充電電荷を瞬時に放電させるようにし
たから、電源投入時における突入電流を抑制できると共
に、電源の瞬間的なオン・オフ時における突入電流も抑
圧することができる。この結果、入力ヒューズの溶断や
ブレーカのトリップ、入力コネクタの溶着等の物理的障
害、又、その際の電流変化によって生じるノイズによる
装置障害の誘発を防ぎ、安全で高性能な安定化電源を提
供することができる。As described above, according to the present invention, the FET connected in series to the input line of the switching power supply, the capacitor for controlling the gate voltage of the FET with the charging voltage, and the current supply circuit for supplying the charging current to the capacitor. And a switching element connected in parallel with the capacitor, and a charge / discharge control circuit that controls the charging / discharging of the capacitor to form an inrush current prevention circuit, which turns off the switching element when the power supply is connected, and supplies the current from the current supply circuit. The capacitor is charged by the switch, and the switching element is turned on when the power is turned off so that the charge stored in the capacitor is instantaneously discharged, so that the inrush current when the power is turned on can be suppressed and when the power is turned on and off momentarily. The inrush current at can also be suppressed. As a result, it provides a safe and high-performance stabilized power supply by preventing physical obstacles such as blown input fuse, trip of breaker, welding of input connector, etc., and device trouble caused by noise caused by current change at that time. can do.
【００１４】又、本発明によれば、充放電制御回路を、
コンデンサと並列に接続され、抵抗分圧した電圧をトラ
ンジスタ（スイッチング素子）のベースに入力する抵抗
分圧回路と、トランジスタのエミッタと抵抗分圧回路の
接続ラインに直列に接続され、電源接続時に純バイアス
され、電源切断時に逆バイアスされるダイオードとで構
成し、しかも、電流供給回路を、ＣＲ時定数回路、ある
いは、定電流源回路、あるいは、定電圧源回路により構
成したから、突入電流防止回路を簡単、安価に構成する
ことができる。Further, according to the present invention, the charge / discharge control circuit includes:
It is connected in parallel with the capacitor and is connected in series with the resistance voltage divider circuit that inputs the resistance-divided voltage to the base of the transistor (switching element) and the connection line between the transistor emitter and the resistance voltage divider circuit. Inrush current prevention circuit, which is composed of a diode that is biased and reverse biased when the power is turned off, and the current supply circuit is composed of a CR time constant circuit, a constant current source circuit, or a constant voltage source circuit. Can be configured easily and inexpensively.
【図１】本発明の原理説明図である。FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】本発明の突入電流防止回路を備えたスイッチン
グ電源の要部構成図である。FIG. 2 is a main part configuration diagram of a switching power supply including an inrush current prevention circuit of the present invention.
【図３】コンデンサの端子電圧説明図である。FIG. 3 is an explanatory diagram of a terminal voltage of a capacitor.
【図４】本発明の第２実施例構成図である。FIG. 4 is a configuration diagram of a second embodiment of the present invention.
【図５】第２実施例の変形例である。FIG. 5 is a modification of the second embodiment.
【図６】本発明の第３実施例構成図である。FIG. 6 is a configuration diagram of a third embodiment of the present invention.
【図７】第３実施例の変形例である。FIG. 7 is a modification of the third embodiment.
【図８】従来の突入電流防止回路を備えたスイッチング
電源の構成図である。FIG. 8 is a configuration diagram of a switching power supply including a conventional inrush current prevention circuit.
【図９】従来の問題点を説明する波形図である。FIG. 9 is a waveform diagram illustrating a conventional problem.
１１・・直流流電源 １３・・大容量コンデンサ ２０・・突入電流防止回路 ２１・・ＦＥＴ ２２・・コンデンサ ２３・・電流供給回路 ２４・・スイッチング素子（トランジスタ） ３５・・充放電制御回路 11-DC power supply 13-Large-capacity capacitor 20-Inrush current prevention circuit 21-FET 22-Capacitor 23-Current supply circuit 24-Switching element (transistor) 35-Charge / discharge control circuit
Claims (3)
を直列に接続し、該ＦＥＴのゲート電圧をコンデンサの
充電電圧で制御して電源接続時における突入電流を抑圧
する突入電流防止回路において、 電源接続時に前記コンデンサに充電電流を供給する電流
供給回路と、 コンデンサに並列に接続されたスイッチング素子と、 電源接続時に該スイッチング素子をオフし、前記電流供
給回路からの電流によりコンデンサを充電させると共
に、電源切断時にスイッチング素子をオンし、コンデン
サの充電電荷を放電させる充放電制御回路を備えた突入
電流防止回路。1. A FET is provided in an input line of a switching power supply.
Is connected in series, and the gate voltage of the FET is controlled by the charging voltage of the capacitor to suppress the inrush current when the power source is connected. In a current supply circuit that supplies the charging current to the capacitor when the power source is connected, , A switching element connected in parallel with the capacitor, when the power supply is connected, the switching element is turned off, the capacitor is charged by the current from the current supply circuit, and the switching element is turned on when the power is turned off to charge the capacitor Inrush current prevention circuit with charge / discharge control circuit for discharging.
あり、 前記充放電制御回路は、前記コンデンサと並列に接続さ
れ、抵抗分圧した電圧をトランジスタのベースに入力す
る抵抗分圧回路と、トランジスタのエミッタと抵抗分圧
回路の接続ラインに直列に接続され、電源接続時に純バ
イアスされ、電源切断時に逆バイアスされるダイオード
を有する請求項１記載の突入電流防止回路。2. The switching element is a transistor, the charge / discharge control circuit is connected in parallel with the capacitor, and a resistance voltage dividing circuit for inputting a resistance-divided voltage to the base of the transistor, an emitter of the transistor, The inrush current prevention circuit according to claim 1, further comprising a diode that is connected in series to a connection line of the resistance voltage dividing circuit, is purely biased when the power supply is connected, and is reversely biased when the power supply is cut off.
で構成されたＣＲ時定数回路、あるいは、定電流源回
路、あるいは、定電圧源回路である請求項１又は請求項
２記載の突入電流防止回路。3. The inrush current prevention according to claim 1, wherein the current supply circuit is a CR time constant circuit configured with the capacitor, a constant current source circuit, or a constant voltage source circuit. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15141695A JP3256412B2 (en) | 1995-06-19 | 1995-06-19 | Inrush current prevention circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15141695A JP3256412B2 (en) | 1995-06-19 | 1995-06-19 | Inrush current prevention circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH096440A true JPH096440A (en) | 1997-01-10 |
| JP3256412B2 JP3256412B2 (en) | 2002-02-12 |
Family
ID=15518142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15141695A Expired - Fee Related JP3256412B2 (en) | 1995-06-19 | 1995-06-19 | Inrush current prevention circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3256412B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319850A (en) * | 2001-04-23 | 2002-10-31 | Yokogawa Electric Corp | Multi-point signal output device |
| JP2007055488A (en) * | 2005-08-25 | 2007-03-08 | Kawasaki Heavy Ind Ltd | Flap of vehicle |
| JP2007272873A (en) * | 2006-03-30 | 2007-10-18 | Power Integrations Inc | Method and apparatus for in-rush current limiting circuit |
| JP2008099426A (en) * | 2006-10-11 | 2008-04-24 | Yokogawa Electric Corp | Switch circuit |
| JP2009060722A (en) * | 2007-08-31 | 2009-03-19 | Hoshizaki Electric Co Ltd | Rush-current preventing circuit and power supply device |
| JP2009268244A (en) * | 2008-04-24 | 2009-11-12 | Canon Inc | Rush current reduction circuit and power supply unit having the same |
| WO2015084333A1 (en) * | 2013-12-03 | 2015-06-11 | Hewlett-Packard Development Company, L.P. | Limiting inrush of current to a capacitor based on an interval |
| US9318972B2 (en) | 2014-03-10 | 2016-04-19 | Fujitsu Limited | Power circuit |
| KR102654693B1 (en) * | 2022-11-15 | 2024-04-04 | 한화시스템 주식회사 | Inrush current limiting apparatus for avionics equipment receiving AC power at power interrupt status and electric power supply having the same |
-
1995
- 1995-06-19 JP JP15141695A patent/JP3256412B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319850A (en) * | 2001-04-23 | 2002-10-31 | Yokogawa Electric Corp | Multi-point signal output device |
| JP2007055488A (en) * | 2005-08-25 | 2007-03-08 | Kawasaki Heavy Ind Ltd | Flap of vehicle |
| JP4676281B2 (en) * | 2005-08-25 | 2011-04-27 | 川崎重工業株式会社 | Vehicle flap |
| JP2007272873A (en) * | 2006-03-30 | 2007-10-18 | Power Integrations Inc | Method and apparatus for in-rush current limiting circuit |
| JP2008099426A (en) * | 2006-10-11 | 2008-04-24 | Yokogawa Electric Corp | Switch circuit |
| JP2009060722A (en) * | 2007-08-31 | 2009-03-19 | Hoshizaki Electric Co Ltd | Rush-current preventing circuit and power supply device |
| JP2009268244A (en) * | 2008-04-24 | 2009-11-12 | Canon Inc | Rush current reduction circuit and power supply unit having the same |
| WO2015084333A1 (en) * | 2013-12-03 | 2015-06-11 | Hewlett-Packard Development Company, L.P. | Limiting inrush of current to a capacitor based on an interval |
| US9318972B2 (en) | 2014-03-10 | 2016-04-19 | Fujitsu Limited | Power circuit |
| KR102654693B1 (en) * | 2022-11-15 | 2024-04-04 | 한화시스템 주식회사 | Inrush current limiting apparatus for avionics equipment receiving AC power at power interrupt status and electric power supply having the same |
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| Publication number | Publication date |
|---|---|
| JP3256412B2 (en) | 2002-02-12 |
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